CN107808868B - 芯片封装结构及其制造方法 - Google Patents
芯片封装结构及其制造方法 Download PDFInfo
- Publication number
- CN107808868B CN107808868B CN201710952866.6A CN201710952866A CN107808868B CN 107808868 B CN107808868 B CN 107808868B CN 201710952866 A CN201710952866 A CN 201710952866A CN 107808868 B CN107808868 B CN 107808868B
- Authority
- CN
- China
- Prior art keywords
- die pad
- die
- power switch
- switch tube
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims description 31
- 239000008393 encapsulating agent Substances 0.000 claims description 16
- 239000005022 packaging material Substances 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 7
- 238000004080 punching Methods 0.000 abstract description 9
- 238000012858 packaging process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
公开了一种芯片封装结构包括:引线框,引线框包括多个引脚以及第一管芯垫和第二管芯垫;第一管芯和第二管芯,第一管芯和第二管芯的第一表面分别固定在第一管芯垫和第二管芯垫上,第二表面分别包括多个焊盘以及多条键合线,多条键合线包括各自一端连接至第一管芯的多个焊盘的第一组键合线,以及各自一端连接至第二管芯的多个焊盘的第二组键合线,其中,引线框的多个引脚和第一管芯垫位于主平面上,第二管芯垫相对于主平面凹陷,第一组键合线中的至少一条键合线跨越第二管芯或第二组键合线中的至少一条键合线,第一管芯为控制芯片,第二管芯为功率开关管,避免封装过程中产生的键合线冲丝的现象。
Description
技术领域
本发明涉及半导体技术领域,更具体地,涉及芯片封装结构及其制造方法。
背景技术
在芯片封装结构中,引线键合技术已经获得广泛的应用。现有的芯片封装结构包括引线框以及位于引线框上的一个或多个芯片。在芯片封装结构内部,采用引线键合实现芯片之间以及芯片与引线框之间的电连接。
图1示出根据现有技术的芯片封装结构的俯视图。图2a和2b示出根据现有技术的芯片封装结构的不同实例的侧视图。在该封装结构100中,采用双列直插式封装技术封装芯片120和130。引线框110和多个引脚111以及彼此分离的管芯垫112和113。芯片120和130分别固定在管芯垫112和113上,分别包括多个焊盘121和多个焊盘131。多条引线140用于将芯片120和130彼此连接,以及将芯片112和113的至少一部分焊盘连接至引脚111。在该芯片封装结构100中,管芯垫112和113彼此分离且位于引线框110的主平面上,如图2a所示。在进一步改进的封装结构中,管芯垫112和113彼此分离且相对于引线框110的主平面凹陷,以便于引线跨越,如图2b所示。
在上述的封装结构中,管芯垫112和113始终位于同一平面上,芯片120和130的表面大致齐平。在引线键合的过程中,如果需要引线交叉或跨越芯片,则彼此相邻的键合线由于距离较近,容易造成冲丝现象。同时在注入封装料的过程中,由于位于同一平面会有两条或者多条键合线相交叉、相邻的键合线距离较近,而封装料一般从左右两侧注入,从而增加冲丝现象的产生。最终会造成芯片良品率降低,芯片的使用寿命减少,制造成本提高等问题。
发明内容
有鉴于此,本发明的目的在于提供一种芯片封装结构及其制造方法,其中将引线框的至少两个管芯垫设置在不同的平面上以避免引线交叉时的接触,从而解决封装过程中的冲丝问题以及提高芯片良品率。
根据本发明的一方面,提供一种芯片封装结构,包括:引线框,所述引线框包括多个引脚以及第一管芯垫和第二管芯垫;第一管芯和第二管芯,所述第一管芯和所述第二管芯的第一表面分别固定在所述第一管芯垫和所述第二管芯垫上,第二表面分别包括多个焊盘;以及多条键合线,所述多条键合线包括各自一端连接至所述第一管芯的多个焊盘的第一组键合线,以及各自一端连接至所述第二管芯的多个焊盘的第二组键合线,从而将所述第一管芯和所述第二管芯彼此连接以及与所述多个引脚相连接,其中,所述引线框的多个引脚和所述第一管芯垫位于主平面上,所述第二管芯垫相对于所述主平面凹陷,所述第一组键合线中的至少一条键合线横跨所述第二管芯或所述第二组键合线中的至少一条键合线;其中,所述芯片封装结构为开关电源组件,所述第一管芯为控制芯片,所述第二管芯为功率开关管。
优选地,其中,所述第二管芯垫的凹陷深度大于所述功率开关管的厚度。
优选地,其中,所述功率开关管的横向尺寸大于所述控制芯片的横向尺寸。
优选地,其中,所述功率开关管的焊盘数量小于所述控制芯片的焊盘数量。
优选地,其中,所述控制芯片的栅极驱动端经由键合线与所述功率开关管的栅极相连接,所述功率开关管的源极经由键合线与管脚相连接,漏极经由导电粘结层固定在所述第二管芯垫上。
优选地,其中,所述控制芯片的栅极驱动端经由键合线与所述功率开关管的栅极相连接,所述功率开关管的源极经由键合线与管脚相连接,漏极经由导电粘结层固定在所述第二管芯垫上。
优选地,所述第二管芯垫的至少一部分延伸至所述第一管芯垫下方。
优选地,还包括:封装料,用于覆盖所述控制芯片、功率开关管、所述多条键合线,以及所述引线框的至少一部分。
优选地,其中,所述封装料形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多条引脚从所述封装料的侧面伸出。
优选地,其中,所述芯片封装结构为双列直插式封装。
根据本发明的另一方面,提供一种制造芯片封装结构的方法,包括:在引线框的第一管芯垫和第二管芯垫上放置控制芯片和功率开关管,所述引线框的多个引脚和所述第一管芯垫位于主平面上,所述第二管芯垫相对于所述主平面凹陷;采用多条键合线进行键合,将所述控制芯片和所述功率开关管彼此连接以及与所述多个引脚相连接;以及采用封装料覆盖所述控制芯片、功率开关管、所述多条键合线,以及所述引线框的至少一部分,其中,所述多条键合线包括各自一端连接至所述控制芯片的多个焊盘的第一组键合线,以及各自一端连接至所述功率开关管的多个焊盘的第二组键合线,所述第一组键合线中的至少一条键合线跨越所述功率开关管或所述第二组键合线中的至少一条键合线。
优选地,其中,所述放置的步骤包括将所述控制芯片和所述功率开关管的第一表面分别固定在所述第一管芯垫和所述第二管芯垫上。
优选地,其中,所述放置的步骤包括将所述第二管芯垫从所述引线框的侧面插入至所述第一管芯垫和所述第二管芯垫之间的位置。
优选地,其中,所述第二管芯垫的凹陷深度大于所述功率开关管的厚度。
优选地,其中,所述功率开关管的横向尺寸大于所述控制芯片的横向尺寸。
优选地,其中,所述功率开关管的焊盘数量小于所述控制芯片的焊盘数量。
优选地,其中,所述键合的步骤包括,将所述控制芯片的栅极驱动端经由键合线与所述功率开关管的栅极相连接,以及,将所述功率开关管的源极经由键合线与管脚相连接,漏极经由导电粘结层固定在所述第二管芯垫上。
优选地,其中,在所述覆盖的步骤中,所述封装料形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多条引脚从所述封装料的侧面伸出。
优选地,其中,所述芯片封装结构为双列直插式封装。
根据本发明实施例的芯片封装结构中,包括位于引线框两侧的第一管芯垫和第二管芯垫,其中所述引线框的多个引脚和所述第一管芯垫位于主平面上,所述第二管芯垫相对于主平面凹陷。由于该芯片封装结构中,两侧的第一管芯垫和第二管芯垫不在同一平面上,从而位于两侧的第一管芯垫和第二管芯垫上的多条键合线也不在同一平面上。因此,在引线键合的过程中,不会出现在同一平面上跨芯片引线,避免多条键合线相交叉或者相邻的键合线距离较近,从而不易造成冲丝现象;在注入封装料的过程中,封装料从芯片封装结构左右两侧注入,不会出现由于封装料对多条引线的影响,避免相邻或者相交叉的多条引线接触而产生的短路,从而减少冲丝现象的发生。本发明的芯片封装结构不仅提高了引线键合的质量和速度,而且大大降低了产品潜在的失效几率,提高了加工过程中的成品率,从而提高的产品的质量和可靠性。
优选地,第二管芯垫的至少一部分延伸至第一管芯垫的下方,因此可以放置更大尺寸的功率开关管,可以提高芯片的驱动能力。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1示出根据现有技术芯片封装结构的俯视图;
图2a和2b示出根据现有技术的芯片封装结构的不同实施例的侧视图。
图3、图4和图5分别示出根据本发明的实施例的芯片封装结构的立体透视图、俯视图和侧视图;
图6示出了本发明实施例的芯片封装结构的制造流程图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。此外,可能未示出某些公知的部分。为了简明起见,可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解,在描述器件的结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将器件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形,本文将采用“A直接在B上面”或“A在B上面并与之邻接”的表述方式。在本申请中,“A直接位于B中”表示A位于B中,并且A与B直接邻接,而非A位于B中形成的掺杂区中。
在本申请中,术语“冲丝”是指在引线框上固定芯片以及进行引线键合之后,在注入封装料的过程中,彼此相邻的引线由于封装料的冲击而彼此接触导致短路的现象。
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。
图3、图4和图5分别示出根据本发明的实施例的芯片封装结构的立体透视图、俯视图和侧视图。为了清楚起见,在图中采用虚线示出封装材料150的周边,实际上封装材料150覆盖所述第一管芯、第二管芯、所述多条键合线140,以及所述引线框110的至少一部分。
本发明的芯片封装结构200包括:引线框110,所述引线框110包括多个引脚111以及第一管芯垫112和第二管芯垫113,引线框110可以由铜组成,并且通过在冲压形成引线框的不同部分;第一管芯和第二管芯,所述第一管芯和所述第二管芯的第一表面分别固定在所述第一管芯垫112和所述第二管芯垫113上,第二表面分别包括多个焊盘;以及多条键合线140,所述多条键合线包括各自一端连接至所述第一管芯的多个焊盘的第一组键合线,以及各自一端连接至所述第二管芯的多个焊盘的第二组键合线,从而将所述第一管芯和所述第二管芯彼此连接以及与所述多个引脚111相连接,其中,所述引线框110的多个引脚111和所述第一管芯垫112位于主平面上,所述第二管芯垫113相对于所述主平面凹陷,所述第一组键合线中的至少一条键合线141跨越所述第二管芯或所述第二组键合线中的至少一条键合线。其中,所述芯片封装结构200为开关电源组件,第一管芯为控制芯片120,第二管芯为功率开关管130。在本实施例中,所述的功率开关管130为功率MOSFET。第一管芯垫112和第二管芯垫113彼此分离。在代替的实施例中,第一管芯垫112和第二管芯垫113可以整体形成。
引线框110的多个引脚111可以包含7个引脚,其中1个引脚与第一管芯垫112相连接,2个引脚与第二管芯垫113相连接。第一管芯垫112与控制芯片120的粘接以及第二管芯垫113与功率开关管130的粘接为绝缘粘结,该绝缘粘接的材料可为环氧树脂,该绝缘粘接材料可以采用点胶工艺(Dispensing)形成在第一管芯垫112以及第二管芯垫113上,形成的环氧树脂具有一定的厚度,从而确保该芯片的性能。
所述第二管芯垫113的凹陷深度大于所述功率开关管130的厚度,使得所述位于所述控制芯片120的多个焊盘与所述功率开关管130的多个焊盘不在同一表面,从而使得第一组键合线与控制芯片120相连接的一端以及第二组键合线与功率开关管130相连接的一端不在同一平面内,用于避免交叉的键合线之间的相互接触而造成的键合线之间的短路。所述功率开关管130的横向尺寸大于所述控制芯片120的横向尺寸。所述功率开关管130的焊盘数量小于所述控制芯片120的焊盘数量,例如,所述控制芯片120的焊盘121可以为8个,分为两列平行排列;所述功率开关管130的焊盘131可以为2个,位于功率开关管130的第二表面的横向两端。
第二管芯垫113的至少一部分延伸至第一管芯垫112的下方,使得控制芯片120至少部分地堆叠在功率开关管130的上方,在本实施例中,功率开关管130的面积增大,从而提高芯片的驱动能力。
根据本发明实施例的芯片封装结构中,包括位于引线框110两侧的第一管芯垫112和第二管芯垫113,其中所述引线框110的多个引脚111和所述第一管芯垫112位于主平面上,所述第二管芯垫113相对于主平面凹陷。由于该芯片包装结构中,两侧的第一管芯垫112和第二管芯垫113不在同一平面上,从而位于两侧的第一管芯垫112和第二管芯垫113上的多条键合线140也不在同一平面上。因此,在引线键合的过程中,不会出现在同一平面上的跨芯片引线,避免多条键合线140相接触或者相邻的键合线距离较近,从而避免造成冲丝现象;在注入封装料的过程中,封装料从芯片封装结构左右两侧注入,避免出现由于封装料对多条引线的影响,相邻或者交叉的多条键合线140相接触而产生的短路,从而减少冲丝现象的发生。本发明的芯片封装结构不仅提高了引线键合的质量和速度,而且大大降低了产品潜在的失效几率,提高了加工过程中的成品率,从而提高的产品的质量和可靠性。
所述芯片封装结构为开关电源组件,所述控制芯片120的栅极驱动端经由键合线与所述功率开关管130的栅极相连接,所述功率开关管130的源极经由键合线与管脚相连接,漏极经由导电粘结层固定在所述第二管芯垫113上。导电粘结层在第二管芯垫113和功率开关管130之间导电导热,例如提供引导热路径和电连接路径。
此外,本发明的芯片封装结构,还包括:封装料150,用于覆盖所述控制芯片120、功率开关管130、所述多条键合线140,以及所述引线框110的至少一部分。其中,所述封装料150形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多条引脚从所述封装料150的侧面伸出。其中,所述芯片封装结构为双列直插式封装。本发明所使用的封装料可以是环氧树脂聚合物,将已完成引线键合的芯片和模块化工艺的引线框架完全包装,使用该塑封方式具有材料成本低和重量轻等优点。使用环氧树脂聚合物封装的交连后聚合物性能稳定不变性、离子纯并且加工温度高达250℃。环氧树脂的重要的参数是吸潮少,并且可加入填充剂以减少膨胀系数(TCE),使其与引线框和芯片的热膨胀系数相匹配,从而可以保证该芯片的性能。
图6示出了本发明实施例的芯片封装结构的制造流程图,该封装结构的制造流程图包括:
在步骤S01,通过冲压工艺形成引线框110,在引线框110上放置控制芯片120和功率开关管130,所述控制芯片120位于所述引线框110的主平面上,所述功率开关管130相对于所述主平面凹陷。
所述引线框110包括多个引脚111以及第一管芯垫112和第二管芯垫113,所述引线框110的多个引脚111和所述第一管芯垫112位于主平面上,所述第二管芯垫113相对于所述主平面凹陷,所述放置的步骤包括将所述控制芯片120和所述功率开关管130的第一表面分别固定在所述第一管芯垫112和所述第二管芯垫113上。
其中,所述第二管芯垫113的凹陷深度大于所述功率开关管130的厚度。其中,所述功率开关管130的横向尺寸大于所述控制芯片120的横向尺寸。所述功率开关管130的焊盘数量小于所述控制芯片120的焊盘数量。
在该步骤中,如果第二管芯垫113的至少一部分延伸至第一管芯垫112的下方,则将功率开关管130从引线框110的侧面插入至第一管芯垫112和第二管芯垫113之间的位置。然后,在第一管芯垫112上固定控制芯片120,使得控制芯片120至少部分地堆叠在功率开关管130的上方。
在步骤S02,多条键合线140进行引线键合。采用多条键合线140进行键合,将所述控制芯片120和所述功率开关管130彼此连接以及与所述多个引脚111相连接。其中,所述多条键合线140包括各自一端连接至所述控制芯片120的多个焊盘的第一组键合线,以及各自一端连接至所述功率开关管130的多个焊盘的第二组键合线,所述第一组键合线中的至少一条键合线141跨越所述功率开关管130或所述第二组键合线中的至少一条键合线。
所述键合的步骤包括,将所述控制芯片120的栅极驱动端经由键合线与所述功率开关管的栅极相连接,以及,将所述功率开关管130的源极经由键合线与管脚相连接,漏极经由导电粘结层固定在所述第二管芯垫113上。
在步骤S03,采用封装料150覆盖所述控制芯片120、功率开关管130、所述多条键合线140,以及所述引线框110的至少一部分。
在所述覆盖的步骤中,所述封装料150形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多条引脚111从所述封装料150的侧面伸出。其中,所述芯片封装结构为双列直插式封装。
应当说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (17)
1.一种芯片封装结构,包括:
引线框,所述引线框包括多个引脚以及第一管芯垫和第二管芯垫;
第一管芯和第二管芯,所述第一管芯和所述第二管芯的第一表面分别固定在所述第一管芯垫和所述第二管芯垫上,第二表面分别包括多个焊盘;以及
多条键合线,所述多条键合线包括各自一端连接至所述第一管芯的多个焊盘的第一组键合线,以及各自一端连接至所述第二管芯的多个焊盘的第二组键合线,从而将所述第一管芯和所述第二管芯彼此连接以及与所述多个引脚相连接,
其中,所述引线框的多个引脚和所述第一管芯垫位于主平面上,所述第二管芯垫相对于所述主平面凹陷,所述第二管芯垫的至少一部分延伸至所述第一管芯垫下方;
所述第一组键合线中的至少一条键合线跨越所述第二管芯或所述第二组键合线中的至少一条键合线;
其中,所述芯片封装结构为开关电源组件,所述第一管芯为控制芯片,所述第二管芯为功率开关管。
2.根据权利要求1所述的芯片封装结构,其中,所述第二管芯垫的凹陷深度大于所述功率开关管的厚度。
3.根据权利要求1所述的芯片封装结构,其中,所述功率开关管的横向尺寸大于所述控制芯片的横向尺寸。
4.根据权利要求1所述的芯片封装结构,其中,所述功率开关管的焊盘数量小于所述控制芯片的焊盘数量。
5.根据权利要求1所述的芯片封装结构,其中,所述控制芯片的栅极驱动端经由键合线与所述功率开关管的栅极相连接,所述功率开关管的源极经由键合线与引脚相连接,漏极经由导电粘结层固定在所述第二管芯垫上。
6.根据权利要求1所述的芯片封装结构,还包括:封装料,用于覆盖所述控制芯片、功率开关管、所述多条键合线,以及所述引线框的至少一部分。
7.根据权利要求6所述的芯片封装结构,其中,所述封装料形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多个引脚从所述封装料的侧面伸出。
8.根据权利要求6所述的芯片封装结构,其中,所述芯片封装结构为双列直插式封装。
9.一种制造芯片封装结构的方法,包括:
在引线框的第一管芯垫和第二管芯垫上放置控制芯片和功率开关管,所述引线框的多个引脚和所述第一管芯垫位于主平面上,所述第二管芯垫相对于所述主平面凹陷;所述第二管芯垫的至少一部分延伸至所述第一管芯垫下方;
采用多条键合线进行键合,将所述控制芯片和所述功率开关管彼此连接以及与所述多个引脚相连接;以及
采用封装料覆盖所述控制芯片、功率开关管、所述多条键合线,以及所述引线框的至少一部分,
其中,所述多条键合线包括各自一端连接至所述控制芯片的多个焊盘的第一组键合线,以及各自一端连接至所述功率开关管的多个焊盘的第二组键合线,
所述第一组键合线中的至少一条键合线跨越所述功率开关管或所述第二组键合线中的至少一条键合线。
10.根据权利要求9所述的方法,其中,
所述放置的步骤包括将所述控制芯片和所述功率开关管的第一表面分别固定在所述第一管芯垫和所述第二管芯垫上。
11.根据权利要求10所述的方法,其中,所述放置的步骤包括将所述功率开关管从所述引线框的侧面插入至所述第一管芯垫和所述第二管芯垫之间的位置。
12.根据权利要求10所述的方法,其中,所述第二管芯垫的凹陷深度大于所述功率开关管的厚度。
13.根据权利要求10所述的方法,其中,所述功率开关管的横向尺寸大于所述控制芯片的横向尺寸。
14.根据权利要求10所述的方法,其中,所述功率开关管的焊盘数量小于所述控制芯片的焊盘数量。
15.根据权利要求10所述的方法,其中,所述键合的步骤包括,将所述控制芯片的栅极驱动端经由键合线与所述功率开关管的栅极相连接,以及,将所述功率开关管的源极经由键合线与引脚相连接,漏极经由导电粘结层固定在所述第二管芯垫上。
16.根据权利要求15所述的方法,其中,在所述覆盖的步骤中,所述封装料形成彼此相对的第一表面和第二表面,以及连接所述第一表面和所述第二表面的侧面,所述多个引脚从所述封装料的侧面伸出。
17.根据权利要求16所述的方法,其中,所述芯片封装结构为双列直插式封装。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710952866.6A CN107808868B (zh) | 2017-10-13 | 2017-10-13 | 芯片封装结构及其制造方法 |
US16/152,533 US10971437B2 (en) | 2017-10-13 | 2018-10-05 | Chip package structure and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710952866.6A CN107808868B (zh) | 2017-10-13 | 2017-10-13 | 芯片封装结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107808868A CN107808868A (zh) | 2018-03-16 |
CN107808868B true CN107808868B (zh) | 2020-03-10 |
Family
ID=61584949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710952866.6A Active CN107808868B (zh) | 2017-10-13 | 2017-10-13 | 芯片封装结构及其制造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10971437B2 (zh) |
CN (1) | CN107808868B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10714418B2 (en) * | 2018-03-26 | 2020-07-14 | Texas Instruments Incorporated | Electronic device having inverted lead pins |
CN112400229B (zh) | 2018-07-12 | 2023-12-19 | 罗姆股份有限公司 | 半导体器件 |
CN108878394A (zh) * | 2018-07-27 | 2018-11-23 | 杭州士兰微电子股份有限公司 | 功率封装结构及其引线框 |
CN111341747A (zh) * | 2018-12-19 | 2020-06-26 | 恩智浦美国有限公司 | 用以改进爬电距离的引线缩短 |
US11348866B2 (en) * | 2020-06-16 | 2022-05-31 | Infineon Technologies Austria Ag | Package and lead frame design for enhanced creepage and clearance |
CN115732490B (zh) * | 2022-11-17 | 2023-11-17 | 海信家电集团股份有限公司 | 智能功率模块和设备 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102986025A (zh) * | 2011-04-05 | 2013-03-20 | 松下电器产业株式会社 | 密封型半导体装置及其制造方法 |
CN107078127A (zh) * | 2014-11-07 | 2017-08-18 | 三菱电机株式会社 | 电力用半导体装置及其制造方法 |
CN206480618U (zh) * | 2017-02-16 | 2017-09-08 | 杰华特微电子(杭州)有限公司 | 应用于功率器件的集成电路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6680219B2 (en) * | 2001-08-17 | 2004-01-20 | Qualcomm Incorporated | Method and apparatus for die stacking |
TWI254437B (en) | 2003-12-31 | 2006-05-01 | Advanced Semiconductor Eng | Leadless package |
CN102394232A (zh) | 2011-11-29 | 2012-03-28 | 杭州矽力杰半导体技术有限公司 | 一种引线框架及应用其的芯片倒装封装装置 |
CN102376671A (zh) | 2011-11-29 | 2012-03-14 | 杭州矽力杰半导体技术有限公司 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
CN102842564B (zh) | 2012-09-12 | 2014-06-25 | 矽力杰半导体技术(杭州)有限公司 | 集成开关电源的倒装封装装置及其倒装封装方法 |
CN103400819B (zh) | 2013-08-14 | 2017-07-07 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及其制备方法和应用其的封装结构 |
CN103531560A (zh) | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | 芯片的封装结构及其制造方法 |
CN103730444B (zh) | 2014-01-20 | 2017-06-27 | 矽力杰半导体技术(杭州)有限公司 | 封装组件及其制造方法 |
US9472528B2 (en) * | 2014-06-05 | 2016-10-18 | Freescale Semiconductor, Inc. | Integrated electronic package and method of fabrication |
CN105097571B (zh) | 2015-06-11 | 2018-05-01 | 合肥矽迈微电子科技有限公司 | 芯片封装方法及封装组件 |
CN105261611B (zh) | 2015-10-15 | 2018-06-26 | 矽力杰半导体技术(杭州)有限公司 | 芯片的叠层封装结构及叠层封装方法 |
-
2017
- 2017-10-13 CN CN201710952866.6A patent/CN107808868B/zh active Active
-
2018
- 2018-10-05 US US16/152,533 patent/US10971437B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102986025A (zh) * | 2011-04-05 | 2013-03-20 | 松下电器产业株式会社 | 密封型半导体装置及其制造方法 |
CN107078127A (zh) * | 2014-11-07 | 2017-08-18 | 三菱电机株式会社 | 电力用半导体装置及其制造方法 |
CN206480618U (zh) * | 2017-02-16 | 2017-09-08 | 杰华特微电子(杭州)有限公司 | 应用于功率器件的集成电路 |
Also Published As
Publication number | Publication date |
---|---|
US20190115291A1 (en) | 2019-04-18 |
US10971437B2 (en) | 2021-04-06 |
CN107808868A (zh) | 2018-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107808868B (zh) | 芯片封装结构及其制造方法 | |
US9379048B2 (en) | Dual-flag stacked die package | |
EP2677539B1 (en) | Process for manufacture of a semiconductor device | |
US7714455B2 (en) | Semiconductor packages and methods of fabricating the same | |
US9368434B2 (en) | Electronic component | |
US9412684B2 (en) | Top exposed semiconductor chip package | |
US7629676B2 (en) | Semiconductor component having a semiconductor die and a leadframe | |
TWI696253B (zh) | 模壓智慧電源模組 | |
US8426953B2 (en) | Semiconductor package with an embedded printed circuit board and stacked die | |
US10283409B2 (en) | Integrated clip and lead and method of making a circuit | |
US20150145123A1 (en) | Power semiconductor module and method of manufacturing the same | |
US8633511B2 (en) | Method of producing semiconductor device packaging having chips attached to islands separately and covered by encapsulation material | |
US8217517B2 (en) | Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other | |
US20130256920A1 (en) | Semiconductor device | |
US9343427B2 (en) | Manufacturing method of semiconductor device and semiconductor device manufactured thereby | |
CN110892526B (zh) | 半导体装置的制造方法 | |
US8378468B2 (en) | Semiconductor device and method of manufacturing the same | |
US9117741B2 (en) | Semiconductor device | |
JP2013187268A (ja) | 半導体モジュール | |
US20080088037A1 (en) | Semiconductor package and method for manufacturing the same | |
CN210926000U (zh) | 一种引线框架 | |
KR101363463B1 (ko) | 도전성 잉크를 가진 플립 칩 mlp | |
KR20020045495A (ko) | 봉지형 반도체 장치 및 이에 사용되는 리드 프레임 | |
CN116895627A (zh) | 半导体器件封装件及其制造方法 | |
CN116779576A (zh) | 一种半导体组件及半导体器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |