CN107078127A - 电力用半导体装置及其制造方法 - Google Patents
电力用半导体装置及其制造方法 Download PDFInfo
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- CN107078127A CN107078127A CN201480083227.5A CN201480083227A CN107078127A CN 107078127 A CN107078127 A CN 107078127A CN 201480083227 A CN201480083227 A CN 201480083227A CN 107078127 A CN107078127 A CN 107078127A
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- power semiconductor
- lead
- lead frame
- semiconductor element
- packaging body
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 238000000034 method Methods 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 229920005989 resin Polymers 0.000 claims abstract description 93
- 239000011347 resin Substances 0.000 claims abstract description 93
- 238000004806 packaging method and process Methods 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 230000003746 surface roughness Effects 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 206010027439 Metal poisoning Diseases 0.000 claims 1
- 239000010931 gold Substances 0.000 description 40
- 239000000463 material Substances 0.000 description 10
- 238000003825 pressing Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002706 hydrostatic effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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Abstract
具有:电力用半导体元件;控制元件;第1及第2引线框,它们分别保持电力用半导体元件和控制元件;第1金属配线,其将电力用半导体元件和第1引线框电连接;第2金属配线,其将电力用半导体元件和控制元件电连接;以及封装体,其对它们进行覆盖,第1引线框包含有:芯片焊盘,其具有搭载有电力用半导体元件的搭载面;以及第1内部引线,其具有与第1金属配线的一端连接的连接面,在封装体的表面中的与沿搭载面的方向相交叉的侧面,在第1及第2引线框没有从此处凸出的侧面部分,形成有与其他区域相比表面粗糙度大的树脂注入口痕迹,树脂注入口痕迹在从沿搭载面的方向观察时,相对于连接面而形成在第1金属配线所在侧的相反侧。
Description
技术领域
本发明涉及一种电力用半导体装置及其制造方法,特别是涉及通过封装体进行了封装的电力用半导体装置及其制造方法。
背景技术
在半导体装置之中,电力用半导体装置被用于在铁路车辆、混合动力车辆、电动汽车等车辆、家电设备以及工业用机器等中对较大的电力进行控制、整流。电力用半导体装置由于在其使用时电力用半导体元件会发热,因此要求高的散热性。另外,由于施加大于或等于几百V的高电压,因此对于电力用半导体装置,在该电力用半导体装置与外部之间要求高的绝缘性。
在这里,IPM(Intelligent Power Module)为电力用半导体元件和控制用半导体元件(下面,简称为控制元件)进行了一体化的模块。就IPM而言,在配线材料使用引线框的情况下,电力用半导体元件和控制元件搭载于被物理地切分开的2个引线框之上。具体地说,电力用半导体元件及控制元件搭载于分别在引线框设置的芯片焊盘之上。电力用半导体元件经由电力用金属细线而与引线框电连接,控制元件经由金属配线与引线框电连接。如上所述的IPM通常是通过传递模塑成型而得到树脂封装,作为封装体而构成的。
在日本特开2004-172239号公报中记载有下述的树脂封装型半导体装置及其制法,即,将控制用支撑板支撑于比散热器高的位置,对接线用引线细线强力地施加由超声波热压接引起的按压力,将该接线用引线细线坚固地分别粘接至控制元件和控制用引线端子。
专利文献1:日本特开2004-172239号公报
发明内容
但是,通常在制作IMP时的传递模塑成型所使用的模具处,树脂的注入口(栅极)设置为与对封装体的侧面进行成型的内周面相连。因此,在IMP中作为半导体元件的配线而使用线径细的金属细线的情况下,即使在如上述地增强了由超声波热压接引起的按压力的情况下,在传递模塑成型时也会由于从模塑树脂受到的流动阻力而使金属细线容易变形。在该金属细线发生了变形的情况下,有时例如金属细线与其他导电部接触而发生导线短路等不良情况。
本发明是为了解决上述的课题而提出的。本发明的主要目的是提供一种对金属细线的变形进行抑制的电力用半导体装置及其制造方法。
本发明所涉及的电力用半导体装置,其具有:电力用半导体元件;控制元件,其对所述电力用半导体元件进行控制;第1引线框及第2引线框,它们分别保持所述电力用半导体元件和所述控制元件;第1金属配线,其将所述电力用半导体元件和所述第1引线框电连接;第2金属配线,其将所述电力用半导体元件和所述控制元件电连接;以及封装体,其对所述第1引线框及所述第2引线框的一部分、所述电力用半导体元件、所述控制元件、所述第1金属配线及所述第2金属配线进行覆盖。所述第1引线框包含有:芯片焊盘,其搭载有所述电力用半导体元件;第1内部引线,其与所述芯片焊盘相连,并且配置于所述封装体的内部,具有与所述第1金属配线的一端连接的连接面;以及第1外部引线,其与所述第1内部引线相连,并且位于与所述芯片焊盘相反侧,配置在所述封装体的外部。所述第2引线框包含有:第2内部引线,其搭载有所述控制元件,配置在所述封装体的内部;以及第2外部引线,其与所述第2内部引线相连,并且配置在所述封装体的外部。在所述封装体的表面中的与沿所述芯片焊盘的搭载有所述电力用半导体元件的搭载面的方向相交叉的侧面,在所述第1引线框及所述第2引线框没有从此处凸出的侧面部分,形成有与所述侧面的其他区域相比表面粗糙度大的树脂注入口痕迹。树脂注入口痕迹在从沿所述搭载面的方向观察时,相对于所述第1内部引线的所述连接面而形成在所述第1金属配线所在侧的相反侧。
发明的效果
根据本发明,能够提供一种对金属细线的变形进行抑制的电力用半导体装置及其制造方法。
附图说明
图1是用于说明本实施方式所涉及的电力用半导体装置的后视图。
图2是图1中的线段II-II处的剖视图。
图3是用于说明本实施方式所涉及的电力用半导体装置的俯视图。
图4是用于说明本实施方式所涉及的电力用半导体装置的侧视图。
图5是本实施方式所涉及的电力用半导体装置的制造方法的流程图。
图6是用于说明本实施方式所涉及的电力用半导体装置的制造方法的剖视图。
图7是用于说明在本实施方式所涉及的电力用半导体装置的制造方法中使用的模具的图。
图8是用于说明本实施方式所涉及的电力用半导体装置的图。
图9是用于说明本实施方式所涉及的电力用半导体装置的剖视图。
图10是用于说明本实施方式所涉及的电力用半导体装置的变形例的侧视图。
具体实施方式
下面,参照附图对本发明的实施方式进行说明。此外,在下面的附图中,对相同或相当的部分标注相同的标号,不重复进行其说明。
参照图1~图9,对本实施方式所涉及的电力用半导体装置及其制造方法进行说明。
电力用半导体元件1可以是任意的电力用半导体元件,例如是RC-IGBT(ReverseConducting-Insulated Gate Bipolar Transistor)。在该情况下,在电力用半导体元件1的表面之上,例如形成有源极电极(未图示)和栅极电极(未图示)。控制元件2是构成用于对电力用半导体元件1进行控制的电子电路的任意的半导体元件。
如图2所示,第1引线框3具有在封装体9的内部设置的芯片焊盘3a及第1内部引线3b、和向封装体9的外部露出的第1外部引线3c。
芯片焊盘3a具有以能够搭载电力用半导体元件1的方式设置的搭载面3d,在该搭载面之上经由焊料11而与电力用半导体元件1焊料接合,对该电力用半导体元件1进行保持。焊料11例如是无铅(Pb)焊料。此外,电力用半导体元件1和芯片焊盘3a的接合也可以使用导电性粘接剂等导电性接合材料来代替焊料11。
第1内部引线3b形成为与芯片焊盘3a相连,具有与后面记述的Al导线5连接的连接面3e。第1内部引线3b具有例如在与上述搭载面垂直的方向上相对于芯片焊盘3a弯曲的部分。换言之,连接面3e相对于上述搭载面具有规定的高度。在这里,规定的高度是指,例如比电力用半导体元件1的厚度(就电力用半导体元件1而言,是后面记述的Al导线5所接合的焊盘表面相对于上述搭载面的高度)高。
第1外部引线3c形成为与第1内部引线3b相连,例如设置为在上述垂直的方向上相对于上述搭载面3d的高度与上述连接面3e相等。在这里,规定的高度是指,例如比电力用半导体元件1的厚度(就电力用半导体元件1而言,是后面记述的Al导线5所接合的焊盘表面相对于上述搭载面的高度)高。
第2引线框4具有在封装体9的内部设置的第2内部引线4a、和向封装体9的外部露出的第2外部引线4b。
第2内部引线4a具有以能够搭载控制元件2的方式设置的搭载面,在该搭载面之上经由导电性粘接剂12而与控制元件2接合,对该控制元件2进行保持。第2外部引线4b形成为与第2内部引线4a相连。
电力用半导体元件1和第1引线框3经由第1金属配线而电连接。第1金属配线只要能够将电力用半导体元件1和第1引线框3电连接即可,可以具有任意的结构,也可以是由包含从例如铝(Al)、铜(Cu)、银(Ag)及其他任意金属中选择的至少一者的金属材料或者合金材料构成的导线。第1金属配线是例如将Al作为主要构成材料的Al导线5。在电力用半导体元件1为RC-IGBT的情况下,Al导线5的位于与例如第1引线框3的连接面3e连接的一端的相反侧的另一端电连接至源极电极。
Al导线5也可以在例如1个源极电极和1个第1引线框3之间形成多个。在Al导线5和第1引线框3之间,形成有填充有封装体9的区域。
电力用半导体元件1与控制元件2、以及控制元件2与第2引线框4分别经由第2金属配线电连接。第2金属配线只要能够将电力用半导体元件1与控制元件2、以及控制元件2与第2引线框4分别电连接即可,可以具有任意的结构,也可以是由包含从例如金(Au)、Cu、Ag及其他任意金属中选择的至少一者的金属材料或者合金材料构成的导线。第2金属配线是例如将Au作为主要构成材料的Au导线6。在电力用半导体元件1为RC-IGBT的情况下,Au导线6将例如电力用半导体元件1的栅极电极和控制元件2电连接。Au导线6也可以在例如1个栅极电极和1个控制元件2之间、以及1个控制元件2和1个第2引线框4之间分别形成多个。
图3是用于说明电力用半导体装置10的除封装体9以外的结构部件的俯视配置的俯视图。如图3所示,Al导线5和Au导线6设置为在俯视观察电力用半导体装置10时,沿某个方向排列。就例如电力用半导体元件1而言,与Al导线5接合的部分相对于与Au导线6接合的部分,位于该Al导线5所接合的第1引线框3侧。Al导线5和Au导线6形成为,从后面记述的树脂注入口痕迹13观察时,沿Al导线5的延伸方向,Au导线6和控制元件2相连。特别是,与树脂注入口痕迹13最接近的Al导线5形成为,在俯视观察时从树脂注入口痕迹13向控制元件2延伸。换言之,与树脂注入口痕迹13最接近的Al导线5的延伸方向形成为,沿与连接有该Al导线5的电力用半导体元件1连接的Au导线6的延伸方向。
Al导线5设置为线径比Au导线6粗,例如Au导线6的线形为大于或等于20μm而小于或等于60μm,与此相对,Al导线5的线形为大于或等于100μm而小于或等于500μm。
第1引线框3的芯片焊盘3a隔着绝缘膜8而配置在作为散热板的金属板7之上。金属板7的相对于与绝缘膜8连接的面而位于相反侧的面(露出面)向封装体9的外部露出。构成金属板7的材料可以设为热导率高的任意材料,例如是Al、Cu等。构成绝缘膜8的材料可以设为,作为芯片焊盘3a和金属板7的粘接剂而起作用、并且具有电绝缘性、且热导率高的任意材料,例如是导热性的环氧树脂。此外,构成绝缘膜8的材料既可以是热塑性树脂,也可以是热硬化性树脂。另外,在绝缘膜8由树脂构成的情况下,绝缘膜8也可以包含有由氧化硅(SiO2)、氧化铝(Al2O3)及氮化硼(BN)构成的组中的至少一者作为填料。
封装体9对电力用半导体元件1、控制元件2、芯片焊盘3a、第1内部引线3b、第2内部引线4a、第2外部引线4b、Al导线5、Au导线6、金属板7的一部分、及绝缘膜8进行封装。构成封装体9的材料可以设为具有电绝缘性的任意材料,例如是环氧树脂。封装体9可以具有任意形状。俯视观察电力用半导体装置10时的封装体9的外形例如是方形,第1引线框3及第2引线框4从彼此相对的一对边(侧面)分别凸出。即,电力用半导体装置10是作为DIP(DualInline Package)型封装而设置的。
如图3所示,就电力用半导体装置10而言,电力用半导体元件1、控制元件2、第1引线框3及第2引线框4也可以分别形成有多个。在该情况下,多个电力用半导体元件1及多个第1引线框3例如分别在金属板7及绝缘膜8之上沿特定的方向排列地配置。另外,多个控制元件2及多个第2引线框4例如分别沿该特定的方向排列地配置。(另外,多个第1引线框3设置为在与例如搭载面3d垂直的方向上,相对于金属板7的露出面的高度分别相等。多个第2引线框4设置为在与例如搭载面3d垂直的方向上,相对于金属板7的露出面的高度分别相等。)
图4是用于针对电力用半导体装置10说明形成于封装体9的侧面部分9A处的后面记述的树脂注入口痕迹13、和用虚线表示的配置在封装体9的内部的第1引线框3等结构部件之间的位置关系的侧视图。参照图3及图4,在封装体9的表面中的、从沿芯片焊盘3a的搭载有电力用半导体元件1的搭载面3d的方向观察的侧面,即,第1引线框3及第2引线框4没有从此处凸出的侧面部分9A,形成有树脂注入口痕迹13。树脂注入口痕迹13是将在通过传递模塑成型而对封装体9进行成型时如图6所示由于在模具20形成的注入口23及浇道24而产生的树脂剩余部分14(参照图9)剖切而形成的(详细内容将在后面记述)。树脂注入口痕迹13在封装体9的侧面部分9A形成为面粗糙度(Rz)大于或等于20μm的区域。
树脂注入口痕迹13在与沿上述搭载面3d的方向交叉的方向上,相对于连接面3e形成在Al导线5所在侧的相反侧。换言之,在将电力用半导体装置10配置为金属板7与电力用半导体元件1相比位于铅垂方向的下方的状态下,树脂注入口痕迹13设置为与连接面3e相比位于铅垂方向的下方。
优选为,树脂注入口痕迹13设置为,在与搭载面3d垂直的方向上,与绝缘膜8相比位于芯片焊盘3a侧。换言之,树脂注入口痕迹13设置为,在将金属板7相对于电力用半导体元件1而配置在铅垂方向下方时,该树脂注入口痕迹13与绝缘膜8相比位于铅垂方向上方。
如图3所示,优选为,在从沿上述搭载面3d的方向观察电力用半导体装置10时,树脂注入口痕迹13与电力用半导体元件1相比形成在第1外部引线3c侧。优选为,树脂注入口痕迹13形成为,在多个第1引线框3的排列方向上,与多个第1引线框3的各连接面3e并排。
另外,优选的是,形成为在俯视观察电力用半导体装置10时,从树脂注入口痕迹13观察,沿Al导线5的延伸方向,Al导线5与Au导线6相连。例如,形成为至少是设置在与树脂注入口痕迹13最接近的位置的Al导线5和Au导线6沿Al导线5的延伸方向而相连。
接下来,参照图5~图9,对本实施方式所涉及的电力用半导体装置的制造方法进行说明。
图6是用于说明本实施方式所涉及的电力用半导体装置的制造方法的各工序的剖视图。首先,准备由电力用半导体元件1、控制元件2、第1引线框3、第2引线框4、Al导线5及Au导线6形成的封装对象件30(工序(S10))。具体地说,首先准备电力用半导体元件1及第1引线框3,在第1引线框3的芯片焊盘3a之上使用无Pb焊料11而固接电力用半导体元件1。另外,准备控制元件2及第2引线框4,在第2引线框4的第2内部引线4a之上使用导电性粘接剂12而固接控制元件2。接着,在电力用半导体元件1和第1引线框3之间形成Al导线5。具体地说,使Al导线5的一个端部与第1内部引线3b的连接面3e接合,使另一个端部与电力用半导体元件1的源极电极接合。另外,在控制元件2和第2内部引线4a之间形成Au导线6。然后,在电力用半导体元件1和控制元件2之间形成Au导线6。由此,准备图6(a)所示的封装对象件30。
然后,形成金属板7和绝缘膜8层叠的层叠体。
接着,参照图6(b),在模具20的内部配置封装对象件30(工序(S20))。模具20的内部(腔室)具有与电力用半导体装置10的封装体9的外形相对应的形状。模具20由上模具21和下模具22构成。在模具20形成有用于向模具20的内部注入树脂的注入口23、和使树脂流通至注入口23的浇道24。
首先,在模具20的内部配置金属板7和绝缘膜8的层叠体。具体地说,在下模具22的规定位置将该层叠体配置为,金属板7与下模具22的腔室的底面接触。接着,以使芯片焊盘3a重叠于绝缘膜8之上的方式配置封装对象件30。由此,封装对象件30在模具20的内部配置为,第1外部引线3c和第2外部引线4b相对于模具20的内部而配置在外侧。
注入口23在面向模具20内部的模具20的内周面中的、从沿搭载面3d的方向观察时的内周侧面,设置在不与第1引线框3和第2引线框4交叉的侧面部分。而且,注入口23在从沿搭载面3d的方向观察时,相对于第1内部引线3b的与Al导线5的一端连接的连接面3e,形成在Al导线5所在侧的相反侧。而且,此时,注入口23在从沿搭载面3d的方向观察时,设置在不与Au导线6重叠的位置。从不同的观点来说就是,注入口23在从沿搭载面3d的方向观察时,与电力用半导体元件1相比设置在第1外部引线3c侧。
参照图6(c),在模具20的内部配置封装对象件30之后,通过上模具21和下模具22将第1外部引线3c的至少一部分和第2外部引线4b的至少一部分夹持,由此使封装对象件30、金属板7及绝缘膜8的周围由模具20封闭。此时,绝缘膜8成为半硬化状态。
接着,参照图7及图8,向模具20的内部注入树脂(工序(S30))。图7是用于说明在本工序(S30)中模具20内部的在沿搭载面3d的方向上的树脂的流动的图。图8是用于说明在本工序(S30)中模具20内部的在与搭载面3d垂直的方向上的树脂的流动的图。
首先,使处于半硬化状态的固态的树脂通过流通至被加热后的模具20的内部而熔融。如图7所示,从注入口23向模具20的内部注入的树脂首先到达第1内部引线3b之上的Al导线5,然后以芯片焊盘3a之上的电力用半导体元件1、Au导线6及第2内部引线4a之上的控制元件2的顺序流动。另外,如图8所示,从注入口23注入的熔融树脂从注入口23向铅垂方向的下方(从芯片焊盘3a侧朝向金属板7侧的方向)流动。此时,处于半硬化状态的绝缘膜8由模具20加热而成为熔融状态,因此由从熔融树脂承受流体静压的芯片焊盘3a向金属板7的方向对绝缘膜8进行加压。而且,从注入口23注入的熔融树脂还从注入口23向铅垂方向的上方流动。换言之,熔融树脂表面的法线矢量朝向将Al导线5向上推的方向。
接着,在模具20的内部使树脂硬化而形成封装体9。此时,芯片焊盘3a和金属板7隔着绝缘膜8而被固接。
接着,参照图6(d),从模具20取出封装体9。此时,从注入口23将在浇道24的内部硬化的树脂(树脂剩余部分14)与封装体9相连地取出。
接着,将上述树脂剩余部分14从封装体9去除(工序(S40))。参照图9,将树脂剩余部分14在铅垂方向上从上方向下方(从芯片焊盘3a侧朝向金属板7侧的方向)通过按压部件40进行按压,由此能够将树脂剩余部分14从封装体9分离而去除。如上所述,能够得到图4所示的本实施方式所涉及的电力用半导体装置10。
下面,对本实施方式所涉及的电力用半导体装置及其制造方法的作用效果进行说明。
就本实施方式所涉及的电力用半导体装置10而言,树脂注入口痕迹13在从沿搭载面3d的方向观察时,相对于连接面3e而形成在Al导线5所在侧的相反侧。换言之,在本实施方式所涉及的电力用半导体装置的制造方法中,用于向模具20的内部注入树脂的注入口23设置于面向模具20内部的模具20的内周面中的、不与第1引线框3或第2引线框4交叉的侧面部分,在从沿搭载面3d的方向观察时,相对于连接面3e而形成在Al导线5所在侧的相反侧。
因此,在向模具20的内部注入树脂的工序(S30)中,能够使从注入口23向模具20的内部注入的熔融树脂以将与该注入口23相比位于铅垂方向上方的Al导线5向上方推压的方式流动。因此,能够在向模具20注入树脂时利用树脂的流动而抑制Al导线5被向沿搭载面3d的方向(例如多个Al导线5相邻的方向)推倒等Al导线5的变形。
由此,电力用半导体装置10能够抑制与Al导线5的变形相伴的泄漏等异常的发生,以高成品率进行制造。另外,电力用半导体装置的制造方法能够抑制与Al导线5的变形相伴的泄漏等异常的发生,因此能够以高成品率制造电力用半导体装置10。
另外,注入口23在从沿搭载面3d的方向观察时,相对于连接面3e而形成在Al导线5所在侧的相反侧,因此在将树脂剩余部分14从封装体9去除时,能够通过将树脂剩余部分14在铅垂方向上从上方向下方(从芯片焊盘3a侧朝向金属板7侧的方向)按压,从而将树脂剩余部分14从封装体9去除。
在从沿搭载面3d的方向观察时,注入口23相对于连接面3e而形成在Al导线5所在侧(铅垂方向的上方)的情况下,与本实施方式相比,用于去除树脂剩余部分14的工时增多。具体地说,为了去除树脂剩余部分14,需要使用具有能够在铅垂方向上从下方向上方对树脂剩余部分14进行按压的按压部件的去除装置,通过该按压部件将树脂剩余部分14从下方向上方按压而从电力用半导体装置10去除树脂剩余部分14,然后从上述去除装置将电力用半导体装置10取出,然后从按压部件将树脂剩余部分14废弃。
即,根据本实施方式所涉及的电力用半导体装置的制造方法,能够容易地从电力用半导体装置10将树脂剩余部分14去除,能够抑制制造成本的增加。
另外,如果设置为在与搭载面3d垂直的方向上,树脂注入口痕迹13与绝缘膜8相比位于第1引线框3侧,则在向模具20的内部注入树脂的工序(S30)中,能够使从注入口23向模具20的内部注入的熔融树脂,以将与该注入口23相比位于铅垂方向下方的芯片焊盘3a向金属板7按压的方式流动。此时,通过熔融树脂而使芯片焊盘3a隔着在本工序(S30)中成为熔融状态的绝缘膜8朝向金属板7受到加压,因此能够抑制由熔融树脂的流动而引起的芯片焊盘3a和金属板7之间的位置偏移等,能够通过使树脂及绝缘膜8硬化,从而将芯片焊盘3a、绝缘膜8及金属板7稳定地固接。
另外,如果在从沿上述搭载面3d的方向观察电力用半导体装置10时,树脂注入口痕迹13与电力用半导体元件1相比形成在第1外部引线3c侧,则在向模具20的内部注入树脂的工序(S30)中,能够使注入口23和Au导线6之间的距离比注入口23和Al导线5之间的距离长。即,能够使得熔融树脂到达至Au导线6的时间比到达至Al导线5的时间长。
因此,向模具20的内部注入的树脂能够在从注入口23到达Au导线6为止由模具20进一步加热而成为熔融粘度充分低的状态。因此,能够抑制Au导线6由于熔融树脂的流动而变形。
此外,通常在传递模塑成型中刚刚从注入口向模具的内部注入的树脂由于加热不充分而处于熔融粘度高的状态。因此,如果处于这种状态的树脂与线径细的Au导线接触,则向Au导线施加的阻力高,所以Au导线容易变形。与此相对,如果像上述那样设置,则能够抑制Au导线6由于熔融树脂的流动而变形。其结果,电力用半导体装置10使由Au导线6的变形引起的导线短路等不良情况得到抑制,因此能够以高成品率制造电力用半导体装置10。
另外,只要形成为在俯视观察电力用半导体装置10时,从树脂注入口痕迹13观察,Al导线5和Au导线6沿Al导线5的延伸方向排列,则在向模具20的内部注入树脂的工序(S30)中,能够使熔融树脂沿Al导线5及Au导线6的延伸方向流动。其结果,相比于熔融树脂在与Au导线6的延伸方向交叉的方向上流动的情况,能够抑制由于被熔融树脂按压而引起的Au导线6的变形,能够以高成品率制造电力用半导体装置10。
此外,在Al导线5和Au导线6分别形成有多个的情况下,只要至少是在与树脂注入口痕迹13最接近的位置设置的Al导线5和Au导线6形成为沿Al导线5的延伸方向相连即可。如果像上述那样设置,则虽然设置在与注入口23最接近的位置的Au导线6在向模具20的内部注入树脂的工序(S30)中最容易承受熔融树脂的流动阻力,但熔融树脂沿该Au导线6的延伸方向而流动,因此能够抑制该Au导线6的变形。
就本实施方式所涉及的电力用半导体装置10而言,树脂注入口痕迹13形成有1个,但并不限于此。参照图10,树脂注入口痕迹13也可以形成有多个。图10是用于说明在作为电力用半导体装置10的变形例而形成有多个树脂注入口痕迹13的情况下的树脂注入口痕迹13、和用虚线表示的配置于封装体9的内部的第1引线框3等结构部件之间的位置关系的侧视图。换言之,在模具20处注入口23也可以形成有多个。在该情况下,多个树脂注入口痕迹13也可以在从沿搭载面3d的方向观察时,在与搭载面3d平行的方向上隔开间隔设置。这样也能够实现与上述的本实施方式所涉及的电力用半导体装置10等同的效果。另外,并不限于此,只要将多个注入口23各自以与上述的注入口23等同的结构来设置,就能够实现与上述的本实施方式所涉及的电力用半导体装置10等同的效果。
如上所述,对本发明的实施方式进行了说明,但应理解为此次公开的实施方式在所有方面都是例示,并不是限制性内容。本发明的范围通过权利要求示出,意在包含与权利要求等同的含义以及范围的所有变更。
标号的说明
1电力用半导体元件,2控制元件,3第1引线框,3a芯片焊盘,3b第1内部引线,3c第1外部引线,3d搭载面,3e连接面,4第2引线框,4a第2内部引线,4b第2外部引线,5、6导线,7金属板,8绝缘膜,9封装体,9A侧面部分,10电力用半导体装置,11焊料,12导电性粘接剂,13树脂注入口痕迹,14树脂剩余部分,20模具,21上模具,22下模具,23注入口,24浇道,30封装对象件,40按压部件。
Claims (5)
1.一种电力用半导体装置,其具有:
电力用半导体元件;
控制元件,其对所述电力用半导体元件进行控制;
第1引线框及第2引线框,它们分别保持所述电力用半导体元件和所述控制元件;
第1金属配线,其将所述电力用半导体元件和所述第1引线框电连接;
第2金属配线,其将所述电力用半导体元件和所述控制元件电连接;以及
封装体,其对所述第1引线框及所述第2引线框的一部分、所述电力用半导体元件、所述控制元件、所述第1金属配线及所述第2金属配线进行覆盖,
所述第1引线框包含有:芯片焊盘,其搭载有所述电力用半导体元件;第1内部引线,其与所述芯片焊盘相连,并且配置于所述封装体的内部,具有与所述第1金属配线的一端连接的连接面;以及第1外部引线,其与所述第1内部引线相连,并且位于与所述芯片焊盘相反侧,配置在所述封装体的外部,
所述第2引线框包含有:第2内部引线,其搭载有所述控制元件,配置在所述封装体的内部;以及第2外部引线,其与所述第2内部引线相连,并且配置在所述封装体的外部,
在所述封装体的表面中的与沿所述芯片焊盘的搭载有所述电力用半导体元件的搭载面的方向相交叉的侧面,在所述第1引线框及所述第2引线框没有从此处凸出的侧面部分,形成有与所述侧面的其他区域相比表面粗糙度大的树脂注入口痕迹,
所述树脂注入口痕迹在从沿所述搭载面的方向观察时,相对于所述第1内部引线的所述连接面而形成在所述第1金属配线所在侧的相反侧。
2.根据权利要求1所述的电力用半导体装置,其中,
还具有金属板,该金属板隔着绝缘膜与所述芯片焊盘的位于所述搭载面相反侧的面连接,
所述金属板的至少一部分向所述封装体的外部露出,
所述树脂注入口痕迹设置为,在与所述搭载面垂直的方向上,与所述绝缘膜相比位于所述芯片焊盘侧。
3.根据权利要求1或2所述的电力用半导体装置,其中,
形成为,在俯视观察所述电力用半导体装置时,从所述树脂注入口痕迹观察,所述第2金属配线和所述控制元件沿所述第1金属配线的延伸方向排列。
4.一种电力用半导体装置的制造方法,该电力用半导体装置构成为,包含有电力用半导体元件的封装对象件由封装体进行了封装,
该电力用半导体装置的制造方法具有下述工序:
准备所述封装对象件的工序;
将所述封装对象件配置于模具的内部的工序;以及
向所述模具的内部注入成为所述封装体的树脂的工序,
所述准备的工序包含下述工序:
准备第1引线框的工序,该第1引线框包含有芯片焊盘、第1内部引线以及第1外部引线,该芯片焊盘搭载有所述电力用半导体元件,该第1内部引线与所述芯片焊盘相连,该第1内部引线配置于所述封装体的内部,该第1外部引线与所述第1内部引线相连,并且该第1外部引线位于与所述芯片焊盘相反侧,配置在所述封装体的外部;
准备第2引线框的工序,所述第2引线框包含有第2内部引线以及第2外部引线,该第2内部引线搭载有对所述电力用半导体元件进行控制的控制元件,配置在所述封装体的内部,该第2外部引线与所述第2内部引线相连,并且该第2外部引线配置在所述封装体的外部;
形成第1金属配线的工序,该第1金属配线将所述电力用半导体元件和所述第1引线框电连接;以及
形成第2金属配线的工序,该第2金属配线将所述电力用半导体元件和所述控制元件电连接,
在所述配置的工序中,用于向所述模具的内部注入所述树脂的注入口在面向所述模具内部的所述模具的内周面中的、与沿所述芯片焊盘的搭载有所述电力用半导体元件的搭载面的方向相交叉的内周侧面,设置在不与所述第1引线框或所述第2引线框交叉的内周侧面部分,而且,所述注入口在从沿所述搭载面的方向观察时,相对于所述第1内部引线的与所述第1金属配线的一端连接的连接面而形成在所述第1金属配线所在侧的相反侧,
在注入所述树脂的工序中,从所述注入口向所述模具的内部注入所述树脂。
5.根据权利要求4所述的电力用半导体装置的制造方法,其中,
在配置所述封装对象件的工序中,将金属板和绝缘膜层叠的层叠体以所述绝缘膜向所述模具的内部露出的方式配置于所述模具的内部,然后以所述芯片焊盘的位于所述搭载面相反侧的面与绝缘膜重叠的方式配置所述封装对象件,
所述注入口设置为,在与所述搭载面垂直的方向上,与所述绝缘膜相比位于所述芯片焊盘侧。
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