CN107611041B - 具有夹具对准凹口的半导体封装和相关方法 - Google Patents

具有夹具对准凹口的半导体封装和相关方法 Download PDF

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CN107611041B
CN107611041B CN201710172718.2A CN201710172718A CN107611041B CN 107611041 B CN107611041 B CN 107611041B CN 201710172718 A CN201710172718 A CN 201710172718A CN 107611041 B CN107611041 B CN 107611041B
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lead frame
die
notch
clip
recess
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CN107611041A (zh
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马可·艾伦·马翰伦
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Amkor Technology Inc
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Amkor Technology Inc
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Abstract

具有夹具对准凹口的半导体封装和相关方法。在一个实施例中,一种电子组件可包括引线框架及第一半导体裸片。引线框架可包括引线框架顶部侧、与引线框架顶部侧相对的引线框架底部侧,及在引线框架顶部侧处的顶部凹口。顶部凹口可包括顶部凹口基底,顶部凹口基底位于引线框架顶部侧与引线框架底部侧之间,且界定顶部凹口的凹口长度;且顶部凹口还可包括顶部凹口第一侧壁,顶部凹口第一侧壁沿着凹口长度从引线框架顶部侧延伸到顶部凹口基底。第一半导体裸片可包括裸片顶部侧、与裸片顶部侧相对且安装到引线框架顶部侧上的裸片底部侧,及裸片周边。顶部凹口可位于裸片周边的外侧。本文中还揭示其它实例及相关方法。

Description

具有夹具对准凹口的半导体封装和相关方法
技术领域
本发明大体来说涉及电子装置,且更特定来说,涉及具有夹具对准凹口的半导体封装和相关方法。
相关申请案交叉参考
本申请案主张于2016年7月11日申请的美国专利申请案第15/207,462号的优先权,所述美国专利申请案的内容特此以全文引用的方式并入本文中。
背景技术
现有半导体封装及用于生产此些封装的方法可遭受不一致,例如,归因于在形成或耦合此些封装的封装元件时的变化性。例如,在将导电夹具附接到引线框架时,可由于此夹具的夹具尾长度及/或夹具弯曲角度的制造或工具磨损变化而影响所述导电夹具与半导体裸片之间的平面对准及/或耦合。因此,期望具有解决之前所述问题以及其它问题同时成本有效且容易并入制造流程中的半导体封装结构及方法。
发明内容
本发明的一态样提供一种电子组件,其包括:引线框架顶部平面;引线框架底部平面,其与所述引线框架顶部平面平行;引线框架,其包括:引线框架顶部侧,其包括:引线框架顶端,所述引线框架顶部平面沿着所述引线框架顶端延伸;引线框架底部侧,其包括:引线框架底端,所述引线框架底部平面沿着所述引线框架底端延伸;及顶部凹口,其包括:顶部凹口基底,其位于所述引线框架顶部平面与所述引线框架底部平面之间,且界定所述顶部凹口的凹口长度;及顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;及第一半导体裸片,其包括:裸片顶部侧;裸片底部侧,其安装在所述引线框架顶部侧上;及裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;其中所述顶部凹口位于所述裸片周边外部。所述电子组件,其进一步包括:夹具,其包括:夹具尾,其具有插入到所述顶部凹口中的夹具边缘;及夹具顶,其耦合到所述夹具尾;其中:所述夹具尾从所述顶部凹口突出越过所述引线框架顶部侧;且所述夹具顶的夹具顶底部耦合到所述裸片顶部侧。所述电子组件,其中:所述顶部凹口基底与所述顶部凹口第一侧壁包括所述引线框架顶部侧的相应部分。所述电子组件,其中:所述顶部凹口包括:凹口第二侧壁,其跨越所述顶部凹口基底与所述凹口第一侧壁相对;其中所述凹口第二侧壁比所述顶部凹口第一侧壁更接近所述第一半导体裸片。
本发明还提供一种电子组件,其包括:引线框架,其包括:引线框架顶部侧;引线框架底部侧,其与所述引线框架顶部侧相对;及顶部凹口,其位于所述引线框架顶部侧且包括:顶部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间,且界定所述顶部凹口的凹口长度;及顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;及第一半导体裸片,其包括:裸片顶部侧;裸片底部侧,其与所述裸片顶部侧相对且安装在所述引线框架顶部侧上;及裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;其中所述顶部凹口位于所述裸片周边外部。所述电子组件,其进一步包括:夹具,其包括:夹具尾,其具有插入到所述顶部凹口中的夹具边缘,使得所述夹具边缘的底部在所述引线框架顶部侧下方;其中:所述夹具尾从所述顶部凹口突出越过所述引线框架顶部侧;且所述顶部凹口基底相对于所述引线框架顶部侧的深度防止所述夹具边缘的所述底部与所述顶部凹口基底直接接触。所述电子组件中,所述夹具边缘沿着所述夹具边缘的长度直接接触所述顶部凹口第一侧壁。所述电子组件中,所述夹具边缘通过焊接材料熔接到所述凹口,所述焊接材料在所述夹具边缘的所述底部与所述顶部凹口基底之间延伸。所述电子组件中,所述夹具包括耦合到所述夹具尾的夹具顶;且所述夹具顶的夹具顶底部耦合到所述裸片顶部侧。所述电子组件中,所述裸片顶部侧包括:栅极端子,其耦合到所述引线框架顶部侧在所述引线框架的引线处;及源极端子或漏极端子中的一者,其通过熔接结构耦合到所述夹具顶底部。所述电子组件进一步包括:第二半导体裸片,其位于所述第一半导体裸片上方;其中:所述夹具包括耦合到所述夹具尾的夹具顶;且所述夹具顶的夹具顶底部耦合到所述第二半导体裸片的顶部侧。所述电子组件中,所述顶部凹口基底与所述顶部凹口第一侧壁由相应蚀刻表面界定。所述电子组件中,所述顶部凹口基底及所述顶部凹口第一侧壁贯穿所述凹口长度为连续的。所述电子组件中,所述裸片底部侧包括:栅极端子,其在所述引线框架的第一引线处耦合到所述引线框架顶部侧;及源极端子或漏极端子中的一者,其通过熔接结构耦合到所述引线框架的第二引线或焊盘中的至少一者。所述电子组件中,所述顶部凹口包括:凹口第二侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;其中所述凹口第二侧壁比所述顶部凹口第一侧壁更接近所述第一半导体裸片。所述电子组件中,所述引线框架包括在所述引线框架底部侧处具有底部凹口的引线,所述底部凹口包括:底部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间;及底部凹口侧壁,其邻近所述底部凹口基底从所述引线框架底部侧延伸到所述底部凹口基底;其中底部凹口的深度比所述顶部凹口的深度大。所述电子组件中,所述引线框架包括引线,所述引线具有:第一引线支脚,其具有界定所述顶部凹口第一侧壁的第一区段的第一支脚内端;及第二引线支脚,其具有界定所述顶部凹口第一侧壁的第二区段的第二支脚内端。所述电子组件,其中:所述顶部凹口第一侧壁在所述第一支脚内端与所述第二支脚内端之间为不连续的。所述电子组件中,所述顶部凹口基底在所述第一支脚内端与所述第二支脚内端之间为不连续的。
本发明还提供一种方法,其包括:将第一半导体裸片安装在引线框架的具有顶部凹口的第一侧上;及将夹具从所述顶部凹口耦合到所述第一半导体裸片的裸片顶部侧;其中:所述引线框架包括:引线框架顶部侧,其包括:引线框架顶端,引线框架顶部平面沿着其延伸;引线框架底部侧,其包括:引线框架底端,所述引线框架底部平面沿着其延伸;及顶部凹口,其包括:顶部凹口基底,其位于所述引线框架顶部平面与所述引线框架底部平面之间,且界定所述顶部凹口的凹口长度;及顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;所述第一半导体裸片包括:裸片顶部侧;裸片底部侧,其安装在所述引线框架顶部侧上;及裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;所述夹具包括插入到所述顶部凹口中的夹具边缘;且所述夹具从所述顶部凹口突出越过所述引线框架顶部侧到所述裸片顶部侧。
附图说明
图1呈现根据本发明的实施例的电子组件的剖面侧视图。
图2呈现电子组件的引线框架的引线的部分的透视图,展示其处的顶部凹口的部分。
图3呈现电子组件的引线框架的另一引线的部分的透视图,展示其处的顶部凹口的部分。
图4说明图2的透视图,具有耦合到顶部凹口的夹具。
图5说明根据本发明的实施例的电子组件的剖面侧视图。
图6说明根据本发明的实施例的电子组件的剖面侧视图。
图7呈现用于提供电子组件的方法的流程图。
具体实施方式
以下论述通过提供其实例来呈现本发明的各种方面。此些实例并非限制性,且因此本发明的各种方面的范围应未必受所提供实例的任何特定特性限制。在以下论述中,短语“举例来说”、“例如”及“示范性”并非限制性且通常与“通过实例且非限制的方式”、“例如且非限制性”及其类似者同义。
为说明的简洁及清楚起见,绘图说明构造的一般方式,且众所周知的特征及技术的描述及细节可被忽略以避免不必要模糊本发明。另外,绘图中的元件未必按比例绘制。例如,图中的元件中的一些元件的尺寸可相对于其它元件经放大以帮助提高对本发明的实施例的理解。不同图中的相同参考编号表示相同元件。
如本文中所使用,术语“及/或”和“或”包含相关联所列物项中的一或多者的任何及全部组合。如本文中所使用,除非上下文另有明确指示,否则单数形式意欲包含复数形式。另外,术语“在…时”意指某动作至少在起始动作的持续时间的某一部分内。
将进一步理解,术语“包括”及/或“包含”在本说明书中使用时规定所述特征、数值、步骤、操作、元件及/或组件的存在,但不排除存在或添加一或多个其它特征、数值、步骤、操作、元件、组件及/或其群组。
应理解,术语“第一”、“第二”等可在本文中用于描述各种元件,且这些元件应不受这些术语限制。这些术语仅用于将一个元件与另一元件区分开。因此,例如,下文所论述第一部件、第一元件、第一区、第一层及/或第一区段可被称作第二部件、第二元件、第二区、第二层及/或第二区段,而不脱离本发明的教示内容。
类似地,各种空间术语(例如,“上部”、“下部”、“侧”、“顶部”、“底部”、“在…上方”、“在…下方”及其类似者)可用于以相对方式将一个元件与另一元件区分开。然而,应理解,元件可以不同方式定向,例如,装置可转向侧面使得其“顶”表面水平定向且其“侧”表面垂直定向,而不脱离本发明的教示内容。
术语“耦合”及其类似者应广泛地理解且指以电方式、机械方式或其它方式连接两个或多于两个元件或信号。耦合(无论机械、电或其它方式)可达任何时间长度,例如,永久或半永久或仅达片刻。此外,应理解,当元件A被称作为“连接到”或“耦合到”元件B,元件A可直接连接到元件B或间接地连接到元件B(例如,中间元件C(及/或其它元件)可定位在元件A与元件B之间)。类似地,除非另有规定,如本文中所使用,词语“在…上方”或“在…上”包含定向、布置或关系,其中规定元件可直接或间接物理接触。
对“一个实施例”或“实施例”的提及意指结合所述实施例描述的特定特征、结构或特性包含于本发明的至少一个实施例中。因此,在本说明书通篇中的各处出现的短语“在一个实施例中”或“在实施例中”未必全部指代同一实施例,但在一些状况下可能。
词语“约”、“大约”或“基本上”的使用意指预期元件的值接近于所述值或位置。然而,如此项技术中众所周知,始终存在阻止值或位置如确切规定的较小偏差。
此外,在一或多个实施例中,特定特征、结构或特性可以任何适合方式组合,如所属领域的技术人员将明了。
进一步理解,下文中适当地说明及描述的实施例可具有实施例及/或可在不存在本文中未明确揭示的任何元件的情况下实践。
在一个实施例中,一种电子组件可包括引线框架及第一半导体裸片。所述引线框架可包括引线框架顶部侧、与所述引线框架顶部侧相对的引线框架底部侧,及在所述引线框架顶部侧处的顶部凹口。所述顶部凹口可包括顶部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间,且界定所述顶部凹口的凹口长度;且还可包括顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底。所述第一半导体裸片可包括裸片顶部侧、与所述裸片顶部侧相对且安装到所述引线框架顶部侧上的裸片底部侧,及位于所述裸片顶部侧与所述裸片底部侧之间且界定裸片周边的裸片侧壁。所述顶部凹口可位于所述裸片周边的外侧。
在一个实施例中,电子组件可包括引线框架、引线框架顶部平面、与引线框架顶部平面平行的引线框架底部平面。引线框架可包括引线框架顶部侧,其包括所述引线框架顶部平面沿着其延伸的引线框架顶端;引线框架底部侧,其包括所述引线框架底部平面沿着其延伸的引线框架底端。所述引线框架还可包括顶部凹口,所述顶部凹口包括:顶部凹口基底,其位于所述引线框架顶部平面与引线框架底部平面之间,且界定所述顶部凹口的凹口长度的;及顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底。所述第一半导体裸片可包括裸片顶部侧、安装到所述引线框架顶部侧上的裸片底部侧,及裸片侧壁,所述裸片侧壁位于所述裸片顶部侧与所述裸片底部侧之间且界定裸片周边。所述顶部凹口可位于所述裸片周边的外侧。
在一个实施方案中,用于提供电子组件的方法可包括:将第一半导体裸片安装在引线框架的具有顶部凹口的第一侧上;将夹具从顶部凹口耦合到所述第一半导体裸片的裸片顶部侧。引线框架可包括引线框架顶部侧,其包括引线框架顶部平面沿着其延伸的引线框架顶端;及引线框架底部侧,其包括所述引线框架底部平面沿着其延伸的引线框架底端。所述引线框架还可包括顶部凹口,所述顶部凹口包括:顶部凹口基底,其位于所述引线框架顶部平面与引线框架底部平面之间,且界定所述顶部凹口的凹口长度;及顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底。所述第一半导体裸片可包括裸片顶部侧、安装到所述引线框架顶部侧上的裸片底部侧,及裸片侧壁,所述裸片侧壁位于所述裸片顶部侧与所述裸片底部侧之间且界定裸片周边。所述夹具可包括插入到所述顶部凹口中的夹具边缘。所述夹具可从所述顶部凹口突出越过所述引线框架顶部侧到所述裸片顶部侧。
本文中进一步解释其它实例及实施例。此些实例及实施例可在图中、权利要求书中及/或本文发明中找到。
转向图式,图1表示根据本发明的一个实施例的电子组件100的剖面侧视图。图2表示电子组件100的引线框架110的引线117的部分的透视图,展示其处的顶部凹口120的部分。图3呈现电子组件100的引线框架110的引线116的部分的透视图,展示其处的顶部凹口130的部分。图4说明具有耦合到顶部凹口120的夹具150的图2的透视图。在一些实施方案中,电子组件100可包括半导体基于引线框架的封装,其在一些实施方案中经配置(例如)用于高功率及/或高电流要求。
如在图1到2中可见,引线框架110包括引线框架顶部侧111及与引线框架顶部侧111相对的引线框架底部侧112。引线框架顶部侧111包含引线框架110的顶端,其中此顶端可包括引线框架110的最顶点或顶表面。引线框架底部侧112包含引线框架110的底端,其中此底端可包括引线框架110的最低点或最低表面。引线框架110界定引线框架顶部平面1111,其沿着引线框架110的顶端延伸;且引线框架底部平面1122,其可平行于引线框架顶部平面1111且沿着引线框架110的底端延伸。
在本实施例中,引线框架110还可包括焊盘115,及引线116到117。引线116到117从中心区105延伸到电子组件100的周边106。焊盘115在本说明中展示为位于中心区105处,但在相同或其它实例中,所述焊盘可为或可包括引线,所述引线(例如)沿与图1中所呈现的横截面平面非平面及/或正交的方向延伸到周边106。如在图2到4中可见,引线116到117可各自包括多个引线支脚,所述引线支脚通过其间的桥接件耦合在一起。引线框架110进一步包括顶部凹口120,所述顶部凹口从引线框架顶部侧111延伸到引线117中。
半导体裸片190位于引线框架110上方,其中裸片侧191使用熔接结构183安装到引线框架顶部侧111上且在焊盘115上方。因此,裸片190及顶部凹口120两者位于同一引线框架顶部侧111上。裸片侧192背对引线框架110,且裸片侧壁193在裸片侧192与裸片侧191之间延伸,从而界定半导体裸片190的裸片周边。引线框架110可用于将裸片190介接到电子组件100的外侧,且可包括导电材料,例如铜及/或其合金。
顶部凹口120位于半导体裸片190的裸片周边的外侧,因此可用于接纳导电夹具150。在本实施例中,顶部凹口120可在引线框架顶部侧111处接达且包括顶部凹口基底125、顶部凹口侧壁121及顶部凹口侧壁122。顶部凹口基底125位于引线框架顶部侧111与引线框架底部侧112之间,因此相对于引线框架顶部侧111凹陷。顶部凹口基底125还位于引线框架顶部平面1111与引线框架底部平面1122之间。
顶部凹口侧壁121沿着凹口长度217从引线框架顶部侧111延伸到顶部凹口基底125。顶部凹口侧壁122类似于顶部凹口侧壁121,但跨越顶部凹口基底125与其相对,使得顶部凹口侧壁122比顶部凹口侧壁121更接近于裸片190。然而,在一些实例中,顶部凹口侧壁122可为任选的,使得顶部凹口基底125可朝向裸片190从顶部凹口侧壁121延伸到引线117的边缘,类似于引线116的顶部凹口130的配置。
在一些实施方案中,顶部凹口120可通过蚀刻引线框架110来形成,其中此蚀刻可(例如)经由化学蚀刻或经由激光蚀刻来实施以界定顶部凹口侧壁121、顶部凹口侧壁122及/或顶部凹口基底125的蚀刻表面。在一些实施方案中,此化学蚀刻可包括蚀刻剂,例如,氯化铁、磷酸铵及/或CuClAHAS(氯化铜-盐酸水溶液)。在一些实施方案中,此激光蚀刻可包括激光蚀刻,例如,运用LDI(激光定义成像)的LEEP过程(改进型激光蚀刻过程)。顶部凹口120还可(例如)通过冲压或压模、烧蚀、锯切、水冲,及/或研磨引线框架110来机械形成。在一些实施例中,类似于顶部凹口120的顶部凹口也可通过弯曲引线框架110来形成。尽管图往往将顶部凹口侧壁121、顶部凹口侧壁122及顶部凹口基底125的表面及结展示为基本上平面且正交,但此些表面及结可包括非平面度及/或可视为弧形,例如,U形状或V形状,此取决于缩放水平及/或所使用的化学或机械形成过程。
如图1及2所见,引线117包括引线支脚1171,其中其内端界定顶部凹口侧壁121的侧壁区段2211。引线117还包括引线支脚2172,其中其内端界定顶部凹口侧壁121的侧壁区段2212。在本实例中,顶部凹口侧壁121贯穿凹口长度217为连续的,包括在引线边缘1171及2172的内端之间延伸(从侧壁区段2211到侧壁区段2212)的侧壁区段2213。在本实例中,顶部凹口基底125贯穿凹口长度217也为连续的。然而,可存在其中顶部凹口侧壁121可为不连续(沿着凹口长度217包括间断段,例如通过省略侧壁区段2213)的实施例。也可存在其中顶部凹口基底125可为不连续(沿着凹口长度217包括间断端)的实施例。
如图1及3中所见,在本实施例中,引线116可类似于引线117,且包括顶部凹口130。顶部凹口130经配置以如本文中针对夹具150描述为经接纳在顶部凹口120(图1、2、4)中一样接纳夹具140(图1)的夹具尾141的夹具边缘142。顶部凹口130包括顶部凹口基底135及顶部凹口侧壁131,其可分别类似于顶部凹口120的顶部凹口基底125及顶部凹口侧壁121(图1到2)。引线116包括引线支脚1161,其中其内端界定顶部凹口侧壁131的侧壁区段3311。引线116还包括引线支脚3172,其中其内端界定顶部凹口侧壁131的侧壁区段3312。在本实例中,顶部凹口侧壁131在引线支脚1161及3172的内端之间为不连续的,其中侧壁区段3311及3312可为共面的但彼此通过间隙间隔或分离开。在本实例中,顶部凹口基底135在引线支脚1161及3172的内端之间也为不连续的,其中基底区段3351及3352可为共面但彼此通过间隙间隔或分离开。然而,可存在其中顶部凹口侧壁131可为连续,及/或其中顶部凹口基底135可为连续的实施例。
图1到4展示引线116及117,其包括在引线框架底部侧112处的相应底部凹口,例如,引线117的底部凹口171及172,及引线116的底部凹口161。例如,底部凹口171包括底部凹口基底,其位于引线框架顶部侧111与引线框架底部侧112之间,且借此相对于引线框架底部侧112凹陷。底部凹口171还包括底部凹口侧壁,其从引线框架底部侧112延伸到其底部凹口基底,且邻近其底部凹口基底。底部凹口172及161还包括类似相应底部凹口基底及底部凹口侧壁。在一些实例中,底部凹口171、172及/或161的底部凹口基底及/或底部凹口侧壁可除其在引线框架底部侧112处的位置外可与本文中所描述的顶部凹口侧壁及顶部凹口基底(例如,顶部凹口120及130的那些)类似的。底部凹口171、172及161可包括或用作用于加强囊封剂101与引线框架110之间的粘合或卡扣的锁定特征。在一些实施方案中,底部凹口171、172、及/或161的深度可比顶部凹口120或130中的任一者的深度大。
如图1及4中所见,夹具150包括夹具尾151,所述夹具尾具有插入到顶部凹口120中的夹具边缘152,其中夹具尾151的其余部分从顶部凹口120突出越过引线框架顶部侧111。夹具边缘152通过顶部凹口120中的熔接结构181熔接到引线框架110,其中此熔接结构181可在夹具边缘152的底部与顶部凹口基底125之间延伸。在一些实例中,熔接结构181可完全填充顶部凹口120。在同一或其它实例中,熔接结构181可能过充满顶部凹口120且可在引线框架顶部侧111的至少一部分上延伸。在一些实例中,熔接结构181可为焊膏、环氧材料或导电烧结材料。在相同或其它实例中,熔接结构181可经由激光或超声波附接来形成。
夹具150还包括夹具顶155,所述夹具顶以其间的角度或弯曲耦合到夹具尾151,其中夹具150可弯曲、冲压或以其它方式由导电材料形成,所述导电材料在一些实施方案中可与关于引线框架110的材料所描述的材料中的一或多者相似或相同。在本实施例中,夹具顶155的夹具顶底部156经由熔接结构182耦合到裸片190的裸片侧192,所述熔接结构位于所述夹具顶底部与所述裸片侧之间。可存在其中熔接结构182及/或183可包括类似于上文关于熔接结构181所描述的材料中的一或多者的材料的实例。
顶部凹口120可考虑到夹具尾151的长度的变化以防止此些变化影响夹具150在裸片190及/或在引线框架110上方对准或耦合。例如,在一些实施方案中,当熔接结构181及182经回焊时,如果夹具尾151由于(例如)制造变化而比需要的长,那么夹具边缘152的底部可视需要凹陷低于引线框架顶部侧111的高度且凹陷到顶部凹口120中,借此防止夹具边缘152到达夹具150的底部且使所述夹具倾斜。因此,顶部凹口基底125相对于引线框架顶部侧111的深度可防止夹具边缘152的底部直接接触顶部凹口基底125,借此缓和夹具在夹具边缘152周围倾斜,其原本可能造成非平面对准及/或夹具顶底部156与裸片侧192之间的减少耦合,及/或熔接结构182的不一致的厚度。顶部凹口基底125的深度及/或顶部凹口侧壁121的高度的范围可介于从大约至少10微米到引线框架110的厚度的一半,借此适应夹具尾长度的制造或容限变化。例如,如果引线框架110为大约200微米厚,那么顶部凹口120可高达100微米深度。
在一些实施例中,裸片190可包括电力装置,例如,场效晶体管(FET)裸片,其可具有源极端子、栅极端子及漏极端子。裸片190包括在裸片侧192处的裸片端子196,其可通过熔接结构182耦合到夹具顶底部156。裸片190还包括在裸片侧191的裸片端子197,其可通过熔接结构183耦合到引线框架110。裸片190进一步包括在裸片侧192处的裸片端子198,其经展示通过连接器耦合到引线框架110的引线116,所述连接器在本实施例中包括耦合到顶部凹口130的夹具140,但在其它实施例中可包括其它连接器类型,例如线接合线或线带。在一些实施方案中,裸片端子196可包括裸片190的源极端子,而裸片端子197可包括裸片190的漏极端子。然而,可存在其中端子196可包括裸片190的漏极端子而裸片端子197可包括裸片190的源极端子的实施方案。裸片端子198可包括裸片190的栅极端子。
如图1及4的实施例中所见,夹具150的夹具边缘152可在插入到顶部凹口120中时直接接触顶部凹口侧壁121。例如,夹具边缘152可沿着及/或贯穿夹具边缘152的基本上整个长度而抵靠顶部凹口侧壁121。夹具边缘152的此定位准许顶部凹口侧壁121充当用于辅助使夹具150相对于引线框架110及/或裸片190对齐的支架。另外,夹具边缘152在顶部凹口120内及/或抵靠顶部凹口侧壁121的此定位可限制夹具150在(例如)熔接结构181的回焊期间侧倾或拔除。
图5说明根据本发明的一个实施例的电子组件500的剖面侧视图。电子组件500类似于上文所描述的电子组件100,使得对电子组件100的相应描述适用于电子组件500,且还包括堆叠于裸片190上方的裸片590。电子组件500包含具有凹口120及130的引线框架110,及上文关于电子组件100所描述的夹具150,而且还包括安装在夹具150的夹具顶155上方的裸片590的底部侧,及在裸片590上方的夹具540。夹具540类似于夹具140,但其夹具尾541较长以适应裸片190上方的裸片590的堆叠高度,且其夹具顶545的底部改为通过熔接结构582耦合到裸片590的顶部侧。
图6表示根据本发明的一个实施例的电子组件600的剖面侧视图。电子组件600类似于上文所论述的电子组件100,使得对电子组件100的对应描述适用于电子组件600。引线框架610类似于引线框架110(图1到5),但经配置以支持裸片190以覆晶或翻转裸片形式安装在其上,其中裸片侧192及对应的裸片端子196及198耦合到引线框架610的顶部侧。裸片端子198在本实例中耦合到引线616,其中引线616可类似于引线116或117(图1到5),例如,通过延伸到电子组件600的周边,但不需要包括顶部凹口,如顶部凹口120或130(图1到5)。裸片端子196在本实例中耦合到裸片焊盘615,所述裸片焊盘可类似于裸片焊盘115(图1到5),及/或可为类似于延伸到电子组件600的周边的引线616的引线。电子组件600可因此包括引线上芯片配置。本实例还展示将裸片190耦合到引线117的夹具150,其中经由顶部凹口120将夹具尾151锚定于其处。由于裸片190在图6中相对于图1到5的实施例翻转,因此夹具顶155改为耦合到裸片侧191及其端子197。
在图6的本实例中,裸片端子196及198分别经由熔接结构184及182耦合到裸片焊盘615及引线616。在一些实例中,熔接结构184及182可包括焊料,及/或可经由焊料模板图案化定义。可存在其中熔接结构184及/或182可包括耦合到裸片焊盘615或引线616的相应覆晶凸块的实例,其中此些覆晶凸块可包括焊料凸块及/或金属柱。
尽管电子组件600在图6中经展示成非堆叠配置,但可存在其中电子组件600可包括类似于图5的配置的堆叠裸片配置,其中裸片590将安装在夹具顶155上方,其中引线616将包括顶部凹口(如同顶部凹口120或130(图1到5))及/或其中夹具540将把裸片590耦合到引线616的此顶部凹口的实施例。
图7呈现用于提供电子组件的方法700的流程图。在一些实施例中,方法700的电子组件可类似于如本文中图1到6所展示的电子组件100、500及/或600中的一或多者,或类似于其变化或组合。
方法700的框710包括将第一半导体裸片安装在包括第一顶部凹口的引线框架的第一侧上。例如,第一半导体裸片可类似于如安装在引线框架110(图1、5)上的裸片190。作为另一实例,第一半导体裸片可类似于如安装在引线框架610(图6)上的裸片190,或另外以(例如)引线上芯片配置安装的覆晶,使得其多个端子接触引线框架的第一侧。
方框710的引线框架可类似于引线框架110(图1到5)、引线框架510(图5)、引线框架610(图6),或其变化形式。引线框架可包括具有引线框架顶部平面沿着其延伸的顶端的引线框架顶部侧,例如上文关于引线框架顶部侧111(图1到5)或引线框架610的顶部侧(图6)及对应引线框架顶端1111(图1到6)描述为实例。类似地,引线框架可包括具有引线框架底部平面沿着其延伸的底端的引线框架底部侧,例如上文关于引线框架底部侧112(图1到5)或引线框架610(图6)的底部顶部侧及对应的引线框架底端1122(图1到6)描述为实例。
方框710的引线框架还可在其顶部侧具有第一顶部凹口,其中此第一顶部凹口可包括顶部凹口基底及顶部凹口第一侧壁。顶部凹口基底可位于引线框架顶部平面与引线框架底部平面之间,且可界定第一顶部凹口的凹口长度。顶部凹口第一侧壁可沿着顶部凹口长度从引线框架顶部侧及/或引线框架顶部平面延伸到顶部凹口基底。第一顶部凹口还可任选地包括顶部凹口第二侧壁,所述顶部凹口第二侧壁还可沿着顶部凹口长度从引线框架顶部侧及/或引线框架顶部平面延伸到顶部凹口基底,其中此顶部凹口第二侧壁跨越顶部凹口基底面向顶部凹口第一侧壁。取决于实施例,顶部凹口基底、顶部凹口第一侧壁及/或顶部凹口第二侧壁可为连续或不连续的。在一些实施方案中,第一顶部凹口可类似于顶部凹口120或130,及其相应顶部凹口基底125或135,及/或其相应侧壁121、122或131(图1到6)。
方法700的方框720包括:将第一夹具从第一顶部凹口耦合第一半导体裸片的裸片顶部侧。第一夹具可包括夹具尾,其具有耦合到裸片顶部侧的夹具顶,及夹具边缘,其耦合到引线框架的第一顶部凹口,其中第一夹具的夹具尾可从第一顶部凹口突出且耦合到夹具顶。在一些实例中,第一夹具可类似于本文中所描述的夹具140(图1)、夹具150(图1、4到6),及/或夹具540(图5)。例如,第一夹具可类似于夹具150(图1、4到6),具有耦合到顶部凹口120的夹具尾151的夹具边缘152,且具有耦合到裸片190的裸片侧192的夹具顶155。在相同或其它实例中,第一夹具可类似于夹具140(图1),具有耦合到顶部凹口130的夹具尾141的夹具边缘142,且具有耦合到裸片190的裸片侧192的夹具顶145。
方法700的方块730包括:将第二半导体裸片安装在第一半导体裸片上面的第一夹具上方。在一些实例中,第二半导体裸片可类似于安装在夹具150的夹具顶155上方且在裸片190上面的裸片590(图5)。
方法700的方框740包括:将第二夹具从引线框架的第二顶部凹口耦合到第二半导体裸片的顶部侧。在一些实例中,第二夹具可类似于夹具540,所述夹具具有耦合到裸片590的顶部侧的夹具顶545及耦合到顶部凹口130的夹具边缘142(图5)。此第二夹具可具有夹具尾,所述夹具尾比第一夹具的夹具尾长以适应第一及第二半导体裸片的堆叠配置的高度。
如本文中所述,本发明的范围并不限于所论述的特定实例方法方框(或相关联结构)。例如,在一些实施方案中,可将各种方框(或其部分)从实例方法700移除或添加到所述实例方法,可重新排序各种方框(或其部分),可修改各种方框(或其部分)等,例如,方框730及/或740可为任选的。
虽然关于特定优选实施例及实例实施例描述本发明的标的物,但前述图式及其描述仅描绘标的物的说明性实施例,且因此并不应认为对其范围的限制。显而易见,所属领域的技术人员将明了许多替代方案及变化,例如,本文中所描述的顶部凹口的特定实施方案可变化,其中(例如)顶部凹口120到130可彼此互换。作为另一实例,本文中所描述的结构及元件可与其它衬底类型一起使用,包含在其顶部侧处具有一或多个顶部凹口及耦合在此(些)顶部凹口与相应半导体裸片之间耦合的对应夹具的层压板或其它衬底。尽管本说明主要将QFN/MLF或QFP引线框架衬底用于说明目的,但应理解,在提供相同或类似益处的同时将这些概念应用于其它引线框架衬底(例如,可布线-MLF(RtMLF)或模制互连系统(MIS))以及层压衬底设计是可能的。在层压设计的状况下,仍可利用引线框架来实现导电引线接头形成且互连到安装在层压衬底上的装置。
如权利要求书在下文中反映,发明性方面可在于不足单个之前所揭示实施例的所有特征。因此,下文中所表达的权利要求书特此明确并入图式的此详细说明中,其中每一权利要求独自作为本发明的单独实施例。此外,虽然本文中所描述的一些实施例包含一些但非包含在其它实施例中的其它特征,但不同实施例的特征的组合意欲在本发明的范围内且意欲形成不同实施例,如所属领域的技术人员将理解。

Claims (20)

1.一种电子组件,其包括:
引线框架顶部平面;
引线框架底部平面,其与所述引线框架顶部平面平行;
引线框架,其包括:
引线框架顶部侧,其包括:
引线框架顶端,所述引线框架顶部平面沿着所述引线框架顶端延伸;
引线框架底部侧,其包括:
引线框架底端,所述引线框架底部平面沿着所述引线框架底端延伸;及
顶部凹口,其包括:
顶部凹口基底,其位于所述引线框架顶部平面与所述引线框架底部平面之间,且界定所述顶部凹口的凹口长度;及
顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;
第一半导体裸片,其包括:
裸片顶部侧;
裸片底部侧,其安装在所述引线框架顶部侧上;及
裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;
其中所述顶部凹口位于所述裸片周边外部;
夹具,其包括:
夹具尾,其具有插入到所述顶部凹口中的夹具边缘,使得所述夹具边缘的底部在所述引线框架顶部侧下方;及
夹具顶,其耦合到所述夹具尾;
其中:
所述夹具顶附接到所述第一半导体裸片;
所述夹具尾从所述顶部凹口突出越过所述引线框架顶部侧;
所述夹具边缘的所述底部以一角度接触所述顶部凹口第一侧壁;
所述顶部凹口基底位在相对于所述引线框架顶部侧的一深度处;且
所述深度避免所述夹具边缘的所述底部与所述顶部凹口基底直接接触。
2.根据权利要求1所述的电子组件,其进一步包括:
熔接结构,其延伸在所述夹具边缘的所述底部和所述顶部凹口基底之间,其中所述熔接结构熔接所述夹具边缘于所述顶部凹口中。
3.根据权利要求1所述的电子组件,其中:
所述顶部凹口基底与所述顶部凹口第一侧壁包括所述引线框架顶部侧的相应部分;及
所述夹具边缘的所述底部是完全在所述引线框架顶部侧下方。
4.根据权利要求2所述的电子组件,其中:
所述顶部凹口包括:
顶部凹口第二侧壁,其跨越所述顶部凹口基底与所述顶部凹口第一侧壁相对;
所述凹口第二侧壁比所述顶部凹口第一侧壁更接近所述第一半导体裸片;及
所述熔接结构延伸以物理性接触所述顶部凹口第二侧壁。
5.一种电子组件,其包括:
引线框架,其包括:
引线框架顶部侧;
引线框架底部侧,其与所述引线框架顶部侧相对;及
顶部凹口,其位于所述引线框架顶部侧且包括:
顶部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间,且界定所述顶部凹口的凹口长度;及
顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;
第一半导体裸片,其包括:
裸片顶部侧;
裸片底部侧,其与所述裸片顶部侧相对且安装在所述引线框架顶部侧上;及
裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;
其中所述顶部凹口位于所述裸片周边外部;及
夹具,其包括:
夹具尾,其具有插入到所述顶部凹口中的夹具边缘,使得所述夹具边缘的底部在所述引线框架顶部侧下方;
其中:
所述夹具尾从所述顶部凹口突出越过所述引线框架顶部侧;
所述夹具边缘的所述底部以一角度接触所述顶部凹口第一侧壁;
所述顶部凹口基底位在距离所述引线框架顶部侧的一深度处;且
所述深度避免所述夹具边缘的所述底部与所述顶部凹口基底直接接触。
6.根据权利要求5所述的电子组件,其中所述顶部凹口基底是不连续的。
7.根据权利要求5所述的电子组件,其中:
所述夹具边缘包括远离所述第一半导体裸片的第一转角以及接近所述第一半导体裸片的第二转角;且
所述夹具边缘沿着所述夹具边缘的所述第一转角直接接触所述顶部凹口第一侧壁。
8.根据权利要求5所述的电子组件,其中:
所述夹具边缘通过焊接材料熔接到所述顶部凹口,所述焊接材料在所述夹具边缘的所述底部与所述顶部凹口基底之间延伸。
9.根据权利要求5所述的电子组件,其中:
所述夹具包括耦合到所述夹具尾的夹具顶;且
所述夹具顶的夹具顶底部耦合到所述裸片顶部侧。
10.根据权利要求9所述的电子组件,其中:
所述裸片顶部侧包括:
栅极端子,其耦合到所述引线框架顶部侧在所述引线框架的引线处;及
源极端子或漏极端子中的一者,其通过熔接结构耦合到所述夹具顶底部。
11.根据权利要求5所述的电子组件,其进一步包括:
第二半导体裸片,其位于所述第一半导体裸片上方;
其中:
所述夹具包括耦合到所述夹具尾的夹具顶;且
所述夹具顶的夹具顶底部耦合到所述第二半导体裸片的顶部侧。
12.根据权利要求5所述的电子组件,其中:
所述顶部凹口基底与所述顶部凹口第一侧壁由相应蚀刻表面界定。
13.根据权利要求5所述的电子组件,其中:
所述顶部凹口基底及所述顶部凹口第一侧壁贯穿所述凹口长度为连续的。
14.根据权利要求5所述的电子组件,其中:
所述裸片底部侧包括:
栅极端子,其在所述引线框架的第一引线处耦合到所述引线框架顶部侧;及
源极端子或漏极端子中的一者,其通过熔接结构耦合到所述引线框架的第二引线或焊盘中的至少一者。
15.根据权利要求5所述的电子组件,其中:
所述顶部凹口包括:
顶部凹口第二侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述
顶部凹口基底;
其中所述顶部凹口第二侧壁比所述顶部凹口第一侧壁更接近所述第一半导体裸片。
16.根据权利要求5所述的电子组件,其中:
所述引线框架包括在所述引线框架底部侧处具有底部凹口的引线,所述底部凹口包括:
底部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间;及
底部凹口侧壁,其邻近所述底部凹口基底从所述引线框架底部侧延伸到所述底部凹口基底;
其中底部凹口的深度比所述顶部凹口的深度大。
17.一种电子组件,其包括:
引线框架,其包括:
引线框架顶部侧;
引线框架底部侧,其与所述引线框架顶部侧相对;及
顶部凹口,其位于所述引线框架顶部侧且包括:
顶部凹口基底,其位于所述引线框架顶部侧与所述引线框架底部侧之间,且界定所述顶部凹口的凹口长度;及
顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;
第一半导体裸片,其包括:
裸片顶部侧;
裸片底部侧,其与所述裸片顶部侧相对且安装在所述引线框架顶部侧上;及
裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;及
囊封剂,其囊封所述第一半导体裸片的至少部分以及所述引线框架的至少部分,其中:
所述顶部凹口位在所述裸片周边外侧;且
所述引线框架包括引线,所述引线包括:
第一引线支脚,其具有界定所述顶部凹口第一侧壁的第一区段的第一支脚内端;及
第二引线支脚,其具有界定所述顶部凹口第一侧壁的第二区段的第二支脚内端;
所述顶部凹口第一侧壁是不连续的以形成在所述第一支脚内端和所述第二支脚内端之间的间隙;且
所述囊封剂插入所述间隙中。
18.根据权利要求17所述的电子组件,其还包括:
夹具,其包括夹具尾,所述夹具尾具有插入到所述顶部凹口中的夹具边缘;
其中:
所述夹具边缘包括底部侧;
所述夹具边缘的所述底部以一角度接触所述顶部凹口第一侧壁;
所述顶部凹口基底位在相对于所述引线框架顶部侧的一深度处;且
所述深度避免所述夹具边缘的所述底部与所述顶部凹口基底直接接触。
19.根据权利要求17所述的电子组件,其中:
所述顶部凹口基底在所述第一支脚内端与所述第二支脚内端之间为不连续的。
20.一种制造电子组件的方法,其包括:
将第一半导体裸片安装在引线框架的具有顶部凹口的第一侧上;及
将夹具从所述顶部凹口耦合到所述第一半导体裸片的裸片顶部侧;
其中:
所述引线框架包括:
引线框架顶部侧,其包括:
引线框架顶端,引线框架顶部平面沿着其延伸;
引线框架底部侧,其包括:
引线框架底端,所述引线框架底部平面沿着其延伸;及
顶部凹口,其包括:
顶部凹口基底,其位于所述引线框架顶部平面与所述引线框架底部平面之间,且界定所述顶部凹口的凹口长度;及
顶部凹口第一侧壁,其沿着所述凹口长度从所述引线框架顶部侧延伸到所述顶部凹口基底;
所述第一半导体裸片包括:
裸片顶部侧;
裸片底部侧,其安装在所述引线框架顶部侧上;及
裸片侧壁,其位于所述裸片顶部侧与所述裸片底部侧之间,且界定裸片周边;
其中:
所述夹具包括插入到所述顶部凹口中的夹具边缘,使得所述夹具边缘的底部在所述引线框架顶部侧下方;
所述夹具边缘的所述底部以一角度接触所述顶部凹口第一侧壁;
所述顶部凹口基底位在距离所述引线框架顶部侧的一深度处;
所述深度避免所述夹具边缘的所述底部与所述顶部凹口基底直接接触;且
所述夹具从所述顶部凹口突出越过所述引线框架顶部侧到所述裸片顶部侧。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102222146B1 (ko) * 2018-04-10 2021-03-05 제엠제코(주) 저비용 전도성 금속 구조체를 이용한 반도체 패키지
US11189550B2 (en) 2018-04-10 2021-11-30 Jmj Korea Co., Ltd. Low-cost semiconductor package using conductive metal structure
US10593640B2 (en) * 2018-04-18 2020-03-17 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
WO2019229828A1 (ja) * 2018-05-29 2019-12-05 新電元工業株式会社 半導体モジュール
CN111261596A (zh) * 2018-12-03 2020-06-09 杰米捷韩国株式会社 利用多个夹件结构的半导体封装及其制造方法
DE102019112979A1 (de) * 2019-05-16 2020-11-19 Infineon Technologies Ag Clip mit Verriegelungsausnehmung
US11069600B2 (en) * 2019-05-24 2021-07-20 Infineon Technologies Ag Semiconductor package with space efficient lead and die pad design
EP3905324A1 (en) * 2020-05-01 2021-11-03 Nexperia B.V. A semiconductor device and a method of manufacture
US11482504B2 (en) 2020-09-16 2022-10-25 Micron Technology, Inc. Edge-notched substrate packaging and associated systems and methods
JP2022146340A (ja) * 2021-03-22 2022-10-05 株式会社東芝 半導体装置
US20230170322A1 (en) * 2021-11-29 2023-06-01 Texas Instruments Incorporated Gang clip with mount compound arrester

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101375382A (zh) * 2003-08-14 2009-02-25 宇芯(毛里求斯)控股有限公司 半导体器件封装及其制造方法
CN103367178A (zh) * 2012-03-27 2013-10-23 德州仪器公司 堆叠半导体封装

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994412A (en) * 1990-02-09 1991-02-19 Motorola Inc. Self-centering electrode for power devices
US5277356A (en) * 1992-06-17 1994-01-11 Rohm Co., Ltd. Wire bonding method
TW374952B (en) * 1997-03-24 1999-11-21 Seiko Epson Corp Semiconductor device substrate, lead frame, semiconductor device and the manufacturing method, circuit substrate and the electronic machine
JPH113953A (ja) * 1997-06-10 1999-01-06 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP3285815B2 (ja) * 1998-03-12 2002-05-27 松下電器産業株式会社 リードフレーム,樹脂封止型半導体装置及びその製造方法
TW459357B (en) * 1999-08-20 2001-10-11 Rohm Co Ltd Electronic part and method of fabricating thereof
JP3429246B2 (ja) * 2000-03-21 2003-07-22 株式会社三井ハイテック リードフレームパターン及びこれを用いた半導体装置の製造方法
US6353257B1 (en) * 2000-05-19 2002-03-05 Siliconware Precision Industries Co., Ltd. Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention
US8236612B2 (en) * 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP4149439B2 (ja) * 2002-07-01 2008-09-10 株式会社ルネサステクノロジ 半導体装置
EP1892537B1 (en) * 2002-07-29 2011-05-25 Yamaha Corporation Three-axis magnetic sensor
US7005325B2 (en) * 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration
US7394150B2 (en) * 2004-11-23 2008-07-01 Siliconix Incorporated Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
US7443015B2 (en) * 2005-05-05 2008-10-28 Stats Chippac Ltd. Integrated circuit package system with downset lead
TWI285415B (en) * 2005-08-01 2007-08-11 Advanced Semiconductor Eng Package structure having recession portion on the surface thereof and method of making the same
US7537965B2 (en) * 2006-06-21 2009-05-26 Delphi Technologies, Inc. Manufacturing method for a leadless multi-chip electronic module
JP2008071927A (ja) * 2006-09-14 2008-03-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7972906B2 (en) * 2008-03-07 2011-07-05 Fairchild Semiconductor Corporation Semiconductor die package including exposed connections
KR101014915B1 (ko) * 2009-02-23 2011-02-15 주식회사 케이이씨 반도체 패키지 및 그 제조 방법
US8586419B2 (en) * 2010-01-19 2013-11-19 Vishay-Siliconix Semiconductor packages including die and L-shaped lead and method of manufacture
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US9184117B2 (en) * 2010-06-18 2015-11-10 Alpha And Omega Semiconductor Incorporated Stacked dual-chip packaging structure and preparation method thereof
US8519525B2 (en) * 2010-07-29 2013-08-27 Alpha & Omega Semiconductor, Inc. Semiconductor encapsulation and method thereof
TWI459528B (zh) * 2010-09-07 2014-11-01 Alpha & Omega Semiconductor 金屬鍵接的半導體封裝及其方法
US8513693B2 (en) * 2011-08-08 2013-08-20 Intellectual Discovery Co., Ltd. Miniature leadless surface mount lamp with dome and reflector cup
JP2013041950A (ja) * 2011-08-12 2013-02-28 Sharp Corp 発光装置
KR101905535B1 (ko) * 2011-11-16 2018-10-10 엘지이노텍 주식회사 발광 소자 패키지 및 이를 구비한 조명 장치
US8951847B2 (en) * 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
JP6078948B2 (ja) * 2012-01-20 2017-02-15 日亜化学工業株式会社 発光装置用パッケージ成形体及びそれを用いた発光装置
JP5947107B2 (ja) * 2012-05-23 2016-07-06 ルネサスエレクトロニクス株式会社 半導体装置
TWI503929B (zh) * 2012-07-09 2015-10-11 萬國半導體股份有限公司 底部源極的功率裝置及製備方法
US20140063744A1 (en) * 2012-09-05 2014-03-06 Texas Instruments Incorporated Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance
US9013028B2 (en) * 2013-01-04 2015-04-21 Texas Instruments Incorporated Integrated circuit package and method of making
US8884415B2 (en) * 2013-02-28 2014-11-11 Nxp B.V. IC package with stainless steel leadframe
JP6484396B2 (ja) * 2013-06-28 2019-03-13 日亜化学工業株式会社 発光装置用パッケージ及びそれを用いた発光装置
DE102013224581A1 (de) * 2013-11-29 2015-06-03 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zu seiner Herstellung
TWI560816B (en) * 2014-07-07 2016-12-01 Alpha & Omega Semiconductor Embedded package and packaging method
JP6413412B2 (ja) * 2014-07-11 2018-10-31 日亜化学工業株式会社 半導体発光装置及びその製造方法
KR101631232B1 (ko) * 2014-12-15 2016-06-27 제엠제코(주) 클립을 이용한 적층 패키지

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101375382A (zh) * 2003-08-14 2009-02-25 宇芯(毛里求斯)控股有限公司 半导体器件封装及其制造方法
CN103367178A (zh) * 2012-03-27 2013-10-23 德州仪器公司 堆叠半导体封装

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