CN103367178A - 堆叠半导体封装 - Google Patents
堆叠半导体封装 Download PDFInfo
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Abstract
本发明描述一种制造堆叠半导体封装的方法,所述堆叠半导体封装至少具有引线框、安装于所述引线框上方且焊接到所述引线框的第一裸片和安装于所述第一裸片上方且焊接到所述第一裸片的第一夹具。所述方法包含以垂直堆叠关系定位所述引线框、第一裸片和第一夹具,以及以不可相对于所述引线框横向移位的关系用非焊接方式锁定所述第一夹具。还揭示一种堆叠半导体封装和一种在制造堆叠半导体封装时生产的中间产品。
Description
技术领域
背景技术
多芯片模块(MCM)是将多个半导体裸片封装在同一衬底上的集成电路封装。MCM传统上具有并排安装在衬底上的裸片。然而,近期,已开发出垂直堆叠半导体裸片的MCM。此些垂直堆叠的裸片具有比常规MCM小的占据面积,且常常用于例如蜂窝式电话和平板计算机等芯片空间非常宝贵的应用中。堆叠裸片通常例如通过转移模制法囊封于保护性环氧树脂中。
发明内容
附图说明
图1是堆叠半导体封装子组合件的透视图。
图2是图1的堆叠半导体封装子组合件的横截面正视图。
图3是图1的堆叠半导体封装子组合件的一部分的横截面图。
图4是图1的堆叠半导体封装子组合件在其回焊加热、线接合连接、囊封及单一化之后的透视图(部分以幻象展示)。
图5是经完全囊封及单一化的堆叠半导体封装的透视图,但仅以虚线展示囊封层的一部分。
图6是经完全囊封及单一化的堆叠半导体封装的透视图,其展示整个囊封层。
图7是制造堆叠半导体封装的方法的流程图。
图8是形成图6的堆叠半导体封装的一部分的半导体裸片的透视图。
具体实施方式
在常规平坦MCM中,各裸片最初并排定位且通过一层下伏焊膏固持于衬底上的适当位置处。焊膏的粘性足以防止裸片在将组合件转移到回焊炉时移动。接着在回焊炉中加热引线框和裸片,此使得焊膏液化且接合到衬底和裸片的表面。当熔融焊料冷却时,裸片与衬底牢固地附接到彼此。
申请人已发现在生产半导体封装时存在问题,其中多个堆叠裸片通过夹具连接到引线框,且其中所述裸片和夹具以焊料相连接。为生产此种堆叠裸片封装,最初将裸片和夹具在彼此之上堆叠在引线框上,其中一层焊膏定位在第一裸片与引线框之间以及每一裸片与夹具之间。可能归因于裸片/夹具堆叠的高度,焊膏的粘着性不足以防止裸片和夹具相对于引线框以及相对于彼此的横向位移。此相对横向位移通常在将引线框/裸片/夹具组合件移动到回焊炉时发生。引线框裸片与夹具之间的此种相对横向移动常常导致所得堆叠裸片封装中的缺陷。申请人还发现,可通过机械锁定特征来防止此种横向位移和相关联的缺陷。
图1至6和8大体展示堆叠半导体封装110的各种特征且展示其制作方式。如图5中最佳所示,堆叠半导体封装110可包含引线框12和第一裸片30,第一裸片30堆叠在引线框12上且通过第一焊料层81A附接到引线框12。封装110还可包含第一夹具40,第一夹具40堆叠在第一裸片30上且通过第二焊料层82A附接到第一裸片。第一夹具40通过不同于焊料的结构被机械锁定以防止相对于引线框12的横向位移。半导体封装110可包含堆叠于第一裸片30与夹具40顶部上的另一(其它)裸片和夹具,其中所述夹具各自通过非焊料结构以及通过一层焊料而锁定于适当位置。堆叠半导体封装110还可包含囊封层100。
在描述堆叠半导体封装110的各种特征时,申请人已使用例如上、下、底部、上方及下方等位置/方向性参考术语,所述术语有时是参考相对于地球表面的定向而使用。此种术语并不以所述意义使用于本申请案中。确切地说,例如上、下等术语仅以相对意义用来指示物体或表面相对于结构中的其它物体或表面的位置,所述结构最初如图式中所示而定向。以此意义使用时,汽车“顶部”即使在随后将汽车上下颠倒位于沟中时仍可称为汽车的“顶部”。
在上文已大体描述了堆叠半导体封装110之后,现在将描述其构造的进一步细节以及生产方法。图1说明堆叠半导体封装子组合件10,其包含引线框12,引线框12是较大引线框薄片11的一部分。为说明性目的,图1中所示的引线框薄片11的唯一部分是围绕引线框12的外围附接的部分。在稍后对堆叠半导体封装子组合件10进行单一化期间,将引线框薄片11的定位于锯道(saw street)AA、BB、CC和DD外部的部分从子组合件10分离。引线框12包含前部部分13、顶部表面14以及底部表面16(图2)。引线框12包含居中定位的裸片焊垫18和多个外围定位的引线20。第一裸片30安装于引线框的裸片焊垫18上。第一裸片在形状上可相对平坦且成矩形,且包含顶部表面32和底部表面34(图2)。第一裸片30在其顶部表面32上具有数个接触焊垫36,包含在第一夹具40下方的大接触焊垫37。
第一夹具40具有顶部表面42和底部表面44(图2)。第一夹具具有主体部分45,所述主体部分45适于定位在第一裸片30的顶部上且进一步包含第一支脚部分46,所述第一支脚部分46从主体部分45向下延伸且接合多个引线20。在一些实施例中,第一夹具40包含系杆(tie bar)48,所述系杆48从第一夹具40的一个横向侧向外突出。
第二裸片50(图1、2和8)可相对平坦且成矩形,其安装于第一夹具40的顶部表面42上。第二裸片50包含顶部表面52、底部表面54和位于顶部表面52中的多个接触焊垫56,包含定位于第二夹具60下方的大接触焊垫57。
具有顶部表面62和底部表面64(图2)的第二夹具60具有定位于顶部第二裸片50上的主体部分65。第二夹具60还包含支脚部分66,所述支脚部分66与主体部分65一体地形成且自其向下突出,接合多个外围定位的引线20。在一些实施例中,系杆部分68从第二夹具60的侧部横向向外突出。
第三裸片70可在紧邻第一裸片30前部的位置处安装于引线框裸片焊垫18上。第三裸片70具有顶部表面72、顶部表面74(图1)和多个接触焊垫76。
引线框12、第一裸片30、第一夹具40、第二裸片50、第二夹具60和第三裸片70通过多个焊料层而被固持于图5的最终堆叠裸片半导体封装110中的适当位置。为了提供焊料层,将多个焊膏层施加到现将描述的各种组件。
在将第一裸片30安装到裸片焊垫18上之前,将第一焊膏层81施加到裸片焊垫18的顶部表面。所述焊膏具有适度的粘着性,且因此倾向于将第一裸片30固持于裸片焊垫18上的适当位置。当然,将理解,并非将第一焊膏层81放置于裸片焊垫18上,可改为将焊膏层施加到第一裸片30的底部表面34上。也可相对于其余焊膏层、裸片和夹具的描述来理解此情形。接下来,将第二焊膏层82施加到第一裸片30的顶部表面32上,且将第一夹具40安装于其上。接下来,将第三焊膏层83施加到第一夹具40的顶部表面42上,且接着将第二裸片50安装于第一夹具40上。接着将第四焊膏层84施加到第二裸片50的顶部表面52上,且将第二夹具60定位于第二裸片50上。接下来,将第五焊膏层85施加到第一裸片30之前的裸片焊垫18。然后,将第三裸片70安装到居中定位的裸片焊垫18上,从而将第五焊膏层85夹于其与裸片焊垫18之间。除了被夹于裸片与邻近引线框和夹具之前的焊膏层81至85之外,还可用焊膏涂布各组件的其它部分,以提供组件的机械和/或电连接。举例来说,夹具40、60的支脚部分以及其接合的引线20可具有施加于其间的焊膏层(未图示)。
为使焊膏层81至85与邻近表面结合,必须将焊膏加热到自由流动温度且随后冷却。如前文所指出,申请人已发现,当堆叠半导体封装子组合件10移动到回焊炉时,焊膏层81至85的粘着性不足以防止各组件在横向上(即,在前后方向90和/或左右方向91上)的中等移位。此种横向移位可导致随后生产的堆叠半导体封装110中的缺陷。此种缺陷可包含某些组件的表面之间的不足电接触或不当地接触的组件区域之间的短路。
申请人已开发多种技术来防止组件的此种横向移位。这些技术是在将子组合件10移动到回焊炉之前实施。图2中最佳地说明用于防止横向移位的一种技术。根据此技术,通过其表面部分与一组引线20的表面部分之间的邻接接合来以横向固定关系固持第一夹具40和第二夹具60。在图2中,通过第一夹具支脚部分46接合的若干引线20中的每一者具备半蚀刻部(half etch)21。这些半蚀刻部21可定位成纵向对准,使得支脚部分46的末端突起47收纳于或多或少连续的半蚀刻部凹槽或沟槽内。因此,半蚀刻部21的凹入表面与末端突起47的表面共同作用以形成机械锁定件,所述机械锁定件积极地防止第一夹具40相对于引线框12的横向位移。以此方式使夹具40稳定还帮助使夹具40安装于其上的第一裸片30在横向上稳定。可以相同方式使第二夹具60稳定。第二夹具支脚部分66的末端突起67收纳于一系列半蚀刻部23中,所述半蚀刻部23提供于另一组引线20中。因此,可防止第二夹具60相对于引线框12横向移位,这还使第二夹具60安装于其上的第二裸片50在横向上稳定。再次,由半蚀刻23形成的凹部与末端突起67的表面部分之间的邻接表面彼此邻接以防止横向移位。
图3和4说明用于防止第一夹具40横向移位的另一技术。在一些实施例中,第一夹具40具有与其一体形成的横向突出的系杆48。通常在用于安装并另外处置夹具40的拾取和放置操作期间使用系杆48。在此实施例中,系杆48还用来使夹具40在横向上稳定。系杆48向外延伸越过引线20,使得系杆48的末端部分定位于引线20中的一者的正上方。将UV固化环氧树脂49施加于引线20与系杆48的末端之间。接下来,将UV固化环氧树脂49暴露于UV光,此导致环氧树脂固化且将系杆48牢牢地附接到引线20。此附接形成用于将第一夹具40固持于第一裸片32顶部上的横向稳定位置的另一类型的机械接合。如图4中所说明,第二夹具60上的系杆68向外延伸越过第一夹具40。因此,可将定位于系杆68与第一夹具40的顶部表面42之间的UV可固化环氧树脂69暴露于UV光以固化环氧树脂69并将系杆68粘附到第一夹具40。由于环氧树脂69所形成的机械锁定件,可防止第二夹具60横向移位。
由表面的邻接接合或上述表面的UV可固化环氧树脂附接形成的机械锁定件可单独或组合地使用以使第一夹具40和第二夹具60以及第一裸片30和第二裸片50横向上稳定。当然,将了解,可在仅含有一个夹具或含有任何数目个夹具的裸片堆叠中使用这些相同的夹具稳定化技术。
接下来,将稳定化的堆叠半导体封装组合件10连同引线框薄片11上的其它等同子组合件一起移动到回焊炉(未图示),在回焊炉处,将整个引线框薄片11和所附接的组件加热到例如约100℃与250℃之间的回焊温度,持续约8分钟到25分钟的时间段。加热导致第一、第二、第三、第四和第五焊膏层81至85中的焊料液化,且与裸片和夹具的邻近表面接合。从回焊炉出来的结构因此与进入回焊炉的子组合件10的结构大体相同,只是焊膏层81至85现在成为焊料层81A、82A、83A、84A、85A。接下来,如图5所说明,将三个裸片上的接触焊垫36、56和76通过接合线86附接到彼此和/或附接到引线20。线接合的技术已为所属领域众所周知,且因此本文将不再描述。接下来,将包含图1的引线框12的引线框薄片11移动到转移模具。在转移模具中,用囊封材料100覆盖包含引线框12以及相关联的夹具和裸片的引线框薄片11。囊封材料100在图4中用虚线指示。接下来,沿着在图1中的AA、BB、CC和DD处所示的模切道(die street)单一化此经囊封的组合件,以提供图6的具有多个暴露引线20的多个等同的堆叠半导体封装110。
所属领域的技术人员将了解,可用各种材料来构造引线框12、裸片30、50、70和夹具40、50。在一个示范性和非限制性实施例中,每一裸片顶部具有镍/金化合物的表面涂层,且每一夹具是由铜制成。引线框可由铜薄片形成。焊膏可为铟铅。
尽管本文中已详细描述堆叠半导体封装和制造堆叠半导体封装的方法的说明性实施例,但应理解,可另外以各种方式体现和使用本发明中阐述的发明概念。除了由现有技术限制的范围以外,所附权利要求书既定解释为包含此种变化。
Claims (20)
1.一种制造堆叠半导体封装的方法,所述堆叠半导体封装至少具有引线框、安装于所述引线框上方且焊接到所述引线框的第一裸片和安装于所述第一裸片上方且焊接到所述第一裸片的第一夹具,所述方法包括:
以垂直堆叠关系定位所述引线框、第一裸片和第一夹具;以及
以不可相对于所述引线框横向移位的关系用非焊接方式锁定所述第一夹具。
2.根据权利要求1所述的制造堆叠半导体封装的方法,其包括:
将第一焊膏层施加到所述引线框的顶部表面和所述第一裸片的底部表面中的一者;
将所述第一裸片定位在所述引线框上,其中所述第一焊膏层夹于所述引线框的所述顶部表面与所述第一裸片的所述底部表面之间;
将第二焊膏层施加到所述第一裸片的顶部表面和所述第一夹具的底部表面中的一者;以及
将所述第一夹具定位在所述第一裸片上,其中所述第二焊膏层定位于所述第一裸片的所述顶部表面与所述第一夹具的所述底部表面之间,且其中所述第一夹具的支脚部分延伸到所述引线框。
3.根据权利要求2所述的方法,其包括:
将第三焊膏层施加到所述第一夹具的顶部表面和第二裸片的底部表面中的一者;
将所述第二裸片定位在所述第一夹具上,其中所述第三焊膏层定位于所述第一夹具的所述顶部表面与所述第二裸片的底部表面之间;
将第四焊膏层施加到所述第二裸片的顶部表面和第二夹具的底部表面中的一者;
将所述第二夹具定位在所述第二裸片上,其中所述第四焊膏层定位于所述第二裸片的所述顶部表面与所述第二夹具的所述底部表面之间,且其中所述第二夹具的支脚部分延伸到所述引线框;以及
以不可相对于所述引线框横向移位的关系用非焊接方式锁定所述第二夹具。
4.根据权利要求3所述的方法,其包括:
将第五焊膏层施加到所述引线框的顶部表面和第三裸片的底部表面中的一者;以及
将所述第三裸片定位在所述引线框上,其中所述第五焊膏层定位于所述引线框的所述顶部表面与所述第三裸片的所述底部表面之间。
5.根据权利要求4所述的方法,其包括:
将所述第三裸片上的接触焊垫线接合连接到所述引线框;
在回焊炉中加热所述引线框、所述第一、第二和第三裸片及所述第一和第二夹具以及所有所述焊膏层;
将所述第一、第二和第三裸片以及所述第一和第二夹具囊封于囊封化合物中;以及
从引线框薄片和囊封化合物的邻近部分单一化所述引线框和定位于其上方的相关联的囊封化合物。
6.根据权利要求2所述的方法,其包括:
回焊加热所述第一和第二焊膏层以用焊接方式将所述引线框附接到所述第一裸片且将所述第一裸片附接到所述第一夹具。
7.根据权利要求1所述的方法,其中所述以不可相对于所述引线框横向移位的关系用非焊接方式锁定所述第一夹具包括将所述第一夹具的所述支脚部分的表面部分定位成与所述引线框的表面部分成邻接关系。
8.根据权利要求7所述的方法,其中将所述第一夹具的所述支脚部分的表面部分定位成与所述引线框的表面部分成邻接关系包括将所述第一夹具和所述引线框中的一者上的突起放置在所述第一夹具和所述引线框中的另一者上的凹部中。
9.根据权利要求1所述的方法,其中所述以不可相对于所述引线框横向移位的关系用非焊接方式锁定所述第一夹具包括:
将UV可固化环氧树脂施加于所述第一夹具的一部分与所述引线框的一邻近部分之间;以及
将UV光源引导到所述UV可固化环氧树脂上。
10.根据权利要求9所述的方法,其中所述将UV可固化环氧树脂施加于所述第一夹具的一部分与所述引线框的一邻近部分之间包括将UV可固化环氧树脂施加于所述第一夹具的系杆部分与所述引线框的一邻近部分之间。
11.一种用于在生产堆叠半导体封装中使用的中间产品,其包括:
引线框;
第一裸片,其堆叠于所述引线框上,其中第一焊膏层定位于两者之间;
第一夹具,其堆叠于所述第一裸片上,其中第二焊膏层定位于两者之间;并且其中所述第一夹具以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
12.根据权利要求11所述的中间产品,其包括:
第二裸片,其堆叠于所述第一夹具上,其中第三焊膏层定位于两者之间;
第二夹具,其堆叠于所述第二裸片上,其中第四焊膏层定位于两者之间;并且其中所述第二夹具以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
13.根据权利要求12所述的中间产品,其包括:
第三裸片,其堆叠于所述引线框上,其中第五焊膏层定位于两者之间。
14.根据权利要求11所述的中间产品,其中所述第一夹具是通过所述第一夹具和所述引线框上的邻接表面而以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
15.根据权利要求11所述的中间产品,其中所述第一夹具是通过定位于所述第一夹具和所述引线框的邻近表面部分之间的UV可固化环氧树脂而以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
16.一种堆叠半导体封装,其包括:
引线框;
第一裸片,其堆叠于所述引线框上且通过定位于两者之间的第一焊料层附接到所述引线框;
第一夹具,其堆叠于所述第一裸片上且通过定位于两者之间的第二焊料层附接到所述第一裸片;并且
其中所述第一夹具还以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
17.根据权利要求16所述的堆叠半导体封装,其中所述第一夹具是通过所述第一夹具和所述引线框上的邻接表面而以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
18.根据权利要求17所述的堆叠半导体封装,其中所述第一夹具和所述引线框上的所述邻接表面包括所述引线框和所述第一夹具中的一者上的突出表面以及所述引线框和所述第一夹具中的另一者上的凹入表面。
19.根据权利要求16所述的堆叠半导体封装,其中所述第一夹具是通过定位于所述第一夹具和所述引线框的邻近表面部分之间的UV可固化环氧树脂而以非焊接方式被锁定以抵抗相对于所述引线框的横向位移。
20.根据权利要求19所述的堆叠半导体封装,其中所述第一夹具和所述引线框的所述邻近表面部分包括所述第一夹具的系杆部分和所述引线框的邻近于所述第一夹具的所述系杆部分的部分。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107611041A (zh) * | 2016-07-11 | 2018-01-19 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
CN107710402A (zh) * | 2015-06-10 | 2018-02-16 | 威世通用半导体有限责任公司 | 带有导电夹具且夹具偏移小的半导体管芯安装用引线框架 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI453831B (zh) | 2010-09-09 | 2014-09-21 | 台灣捷康綜合有限公司 | 半導體封裝結構及其製造方法 |
KR101388737B1 (ko) * | 2012-04-12 | 2014-04-25 | 삼성전기주식회사 | 반도체 패키지, 반도체 모듈, 및 그 실장 구조 |
US9966330B2 (en) | 2013-03-14 | 2018-05-08 | Vishay-Siliconix | Stack die package |
US9589929B2 (en) * | 2013-03-14 | 2017-03-07 | Vishay-Siliconix | Method for fabricating stack die package |
US9171828B2 (en) | 2014-02-05 | 2015-10-27 | Texas Instruments Incorporated | DC-DC converter having terminals of semiconductor chips directly attachable to circuit board |
US9184121B2 (en) * | 2014-02-05 | 2015-11-10 | Texas Instruments Incorporated | Stacked synchronous buck converter having chip embedded in outside recess of leadframe |
KR101569769B1 (ko) * | 2014-02-19 | 2015-11-17 | 제엠제코(주) | 반도체 패키지 및 이를 위한 클립 구조체, 이의 제조 방법 |
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US20150348881A1 (en) * | 2014-05-29 | 2015-12-03 | Texas Instruments Incorporated | Solder Coated Clip And Integrated Circuit Packaging Method |
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US9324640B1 (en) | 2014-11-04 | 2016-04-26 | Texas Instruments Incorporated | Triple stack semiconductor package |
DE102014118628A1 (de) * | 2014-12-15 | 2016-06-16 | Infineon Technologies Ag | Bondingschlip, Träger und Verfahren zum Herstellen eines Bondingclips |
KR101631232B1 (ko) * | 2014-12-15 | 2016-06-27 | 제엠제코(주) | 클립을 이용한 적층 패키지 |
US20160276185A1 (en) * | 2015-03-17 | 2016-09-22 | Texas Instruments Incorporated | Method and apparatus for making integrated circuit packages |
DE102016107792B4 (de) | 2016-04-27 | 2022-01-27 | Infineon Technologies Ag | Packung und halbfertiges Produkt mit vertikaler Verbindung zwischen Träger und Klammer sowie Verfahren zum Herstellen einer Packung und einer Charge von Packungen |
DE102017209780A1 (de) | 2016-06-17 | 2017-12-21 | Infineon Technologies Ag | Durch flussfreies Löten hergestelltes Halbleiterbauelement |
KR200484570Y1 (ko) * | 2016-09-13 | 2017-10-23 | 제엠제코(주) | 클립 구조체를 이용한 반도체 패키지 |
US10373895B2 (en) * | 2016-12-12 | 2019-08-06 | Infineon Technologies Austria Ag | Semiconductor device having die pads with exposed surfaces |
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US11081366B2 (en) | 2018-12-05 | 2021-08-03 | Texas Instruments Incorporated | MCM package isolation through leadframe design and package saw process |
US11073572B2 (en) * | 2019-01-17 | 2021-07-27 | Infineon Technologies Ag | Current sensor device with a routable molded lead frame |
JP7286450B2 (ja) * | 2019-07-10 | 2023-06-05 | 新光電気工業株式会社 | 電子装置及び電子装置の製造方法 |
US11177197B2 (en) * | 2019-09-25 | 2021-11-16 | Texas Instruments Incorporated | Semiconductor package with solder standoff |
US11791247B2 (en) | 2020-09-30 | 2023-10-17 | Semiconductor Components Industries, Llc | Concealed gate terminal semiconductor packages and related methods |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1041065A (zh) * | 1988-09-09 | 1990-04-04 | 莫托罗拉公司 | 功率器件的自对准电报 |
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
CN1157774C (zh) * | 2000-09-21 | 2004-07-14 | 株式会社东芝 | 半导体器件的制造方法和半导体器件 |
US20050199985A1 (en) * | 2004-01-29 | 2005-09-15 | Tan Xiaochun | Semiconductor device with interlocking clip |
CN1790697A (zh) * | 2004-09-16 | 2006-06-21 | 半导体元件工业有限责任公司 | 强大的功率半导体封装 |
US20110309454A1 (en) * | 2010-06-18 | 2011-12-22 | Yueh-Se Ho | Combined packaged power semiconductor device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7238551B2 (en) * | 2004-11-23 | 2007-07-03 | Siliconix Incorporated | Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys |
US7394150B2 (en) * | 2004-11-23 | 2008-07-01 | Siliconix Incorporated | Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys |
US8035221B2 (en) * | 2007-11-08 | 2011-10-11 | Intersil Americas, Inc. | Clip mount for integrated circuit leadframes |
US8564110B2 (en) * | 2009-10-27 | 2013-10-22 | Alpha & Omega Semiconductor, Inc. | Power device with bottom source electrode |
US20120228696A1 (en) * | 2011-03-07 | 2012-09-13 | Texas Instruments Incorporated | Stacked die power converter |
US9842797B2 (en) * | 2011-03-07 | 2017-12-12 | Texas Instruments Incorporated | Stacked die power converter |
US9048338B2 (en) * | 2011-11-04 | 2015-06-02 | Infineon Technologies Ag | Device including two power semiconductor chips and manufacturing thereof |
-
2012
- 2012-03-27 US US13/431,758 patent/US8883567B2/en active Active
-
2013
- 2013-03-27 CN CN2013101029303A patent/CN103367178A/zh active Pending
- 2013-03-27 CN CN201910308752.7A patent/CN110246768A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1041065A (zh) * | 1988-09-09 | 1990-04-04 | 莫托罗拉公司 | 功率器件的自对准电报 |
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
CN1157774C (zh) * | 2000-09-21 | 2004-07-14 | 株式会社东芝 | 半导体器件的制造方法和半导体器件 |
US20050199985A1 (en) * | 2004-01-29 | 2005-09-15 | Tan Xiaochun | Semiconductor device with interlocking clip |
CN1790697A (zh) * | 2004-09-16 | 2006-06-21 | 半导体元件工业有限责任公司 | 强大的功率半导体封装 |
US20110309454A1 (en) * | 2010-06-18 | 2011-12-22 | Yueh-Se Ho | Combined packaged power semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107710402A (zh) * | 2015-06-10 | 2018-02-16 | 威世通用半导体有限责任公司 | 带有导电夹具且夹具偏移小的半导体管芯安装用引线框架 |
CN107611041A (zh) * | 2016-07-11 | 2018-01-19 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
CN107611041B (zh) * | 2016-07-11 | 2023-03-28 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
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