CN219917157U - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN219917157U CN219917157U CN202320093604.XU CN202320093604U CN219917157U CN 219917157 U CN219917157 U CN 219917157U CN 202320093604 U CN202320093604 U CN 202320093604U CN 219917157 U CN219917157 U CN 219917157U
- Authority
- CN
- China
- Prior art keywords
- conductive
- integrated circuit
- clip
- semiconductor integrated
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 230000000295 complement effect Effects 0.000 claims abstract description 27
- 230000008878 coupling Effects 0.000 claims abstract description 25
- 238000010168 coupling process Methods 0.000 claims abstract description 25
- 238000005859 coupling reaction Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000005476 soldering Methods 0.000 abstract description 13
- 238000006073 displacement reaction Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005755 formation reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/40175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/40177—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/405—Material
- H01L2224/40505—Material at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8412—Aligning
- H01L2224/84136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/84138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8434—Bonding interfaces of the connector
- H01L2224/84345—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Abstract
本公开涉及半导体器件。半导体器件,包括:衬底,衬底包括裸片焊盘旁边的导电焊盘;半导体集成电路芯片,被安装至衬底的裸片焊盘;导电夹具,位于半导体集成电路芯片和导电焊盘之间的桥状位置中,导电夹具具有面向半导体集成电路芯片和导电焊盘的耦合表面;焊料材料层,被施加在桥状位置中的导电夹具的耦合表面处,焊料材料层将导电夹具电耦合至半导体集成电路芯片并且电耦合至导电焊盘;以及一对互补定位结构,包括在导电夹具中的腔体和在半导体集成电路芯片和导电焊盘中的至少一项中的突起,互补定位结构相互接合。互补定位结构相互接合以将导电夹具保持在桥状位置中以避免焊接期间的位移。由此,提供了改进的半导体器件。
Description
技术领域
本说明书涉及半导体器件。一个或多个实施例可以有利地被应用于功率半导体器件。
背景技术
具有塑料封装的各种类型的半导体器件,包括:衬底(引线框),其上布置有一个或多个半导体集成电路芯片或裸片;将(多个)半导体芯片耦合到衬底中的引线(外部焊盘)的导电结构(导线、带、夹片);以及绝缘封装(例如,树脂)模制在因此形成的组件上以完成器件的塑料主体。
在功率半导体器件中,从高功率部分传输到器件的输出焊盘的电流可能是显著的,并且为了该目的而使用带或夹片来代替导线。导线仍可以被用于提供到器件中的低功率部分(例如,控制器)的电耦合。基本上使用引线接合工艺放置带。用夹片附着设备放置夹片,并且使用焊膏将夹片连接到焊盘和裸片。被应用在烘箱中固化的焊料以提供夹片与焊盘和裸片的牢固连接。
传统的夹片附着设备有助于在芯片放置中获得足够的精度,因为夹片被应用于裸片和焊盘上,此后组件被转移到烘箱中用于焊料固化。在该处理和固化过程期间,夹片可以从期望的正确位置移位。这可能导致最终产品有缺陷。焊料厚度和夹片在流体状态下“漂浮”在焊料上的趋势也可能基于不期望的过度夹片倾斜。
在本领域中需要有助于充分解决前述问题。
实用新型内容
本公开至少解决了上述问题中的一个或多个问题。
根据本公开的一个方面,提供了一种半导体器件,包括:衬底,衬底包括裸片焊盘旁边的导电焊盘;半导体集成电路芯片,被安装至衬底的裸片焊盘;导电夹具,位于半导体集成电路芯片和导电焊盘之间的桥状位置中,导电夹具具有面向半导体集成电路芯片和导电焊盘的耦合表面;焊料材料层,被施加在桥状位置中的导电夹具的耦合表面处,焊料材料层将导电夹具电耦合至半导体集成电路芯片并且电耦合至导电焊盘;以及一对互补定位结构,包括在导电夹具中的腔体和在半导体集成电路芯片和导电焊盘中的至少一项中的突起,互补定位结构相互接合。
在一些实施例中,半导体器件进一步包括另一对互补定位结构。
在一些实施例中,一对互补定位结构包括导电夹具中的腔体和导电焊盘中的突起。
在一些实施例中,腔体包括盲孔。
在一些实施例中,突起包括柱形凸起。
在一些实施例中,凸起包括多个柱形凸起的堆叠。
在一些实施例中,半导体器件进一步包括在半导体集成电路芯片和导电焊盘中的至少一项上的、在与一对互补定位结构间隔开的位置处的间隔结构,其中间隔结构被配置为将导电夹具保持离半导体集成电路芯片和导电焊盘一距离。
在一些实施例中,间隔结构是柱形凸起。
在一些实施例中,半导体集成电路芯片是功率半导体集成电路,其中导电夹具的大小和尺寸被配置为承载由功率半导体集成电路产生的电流。
由此,提供了改进的半导体器件。
附图说明
现在将参考附图仅以举例的方式描述一个或多个实施例,其中:
图1是功率半导体器件的透视图;
图2是沿图1的线II-II的截面图,涉及传统功率半导体器件;
图3是沿图1的线II-II的截面图,涉及根据本说明书的实施例的功率半导体器件;
图4是由箭头IV指示的图3的部分的视图,以放大的比例再现;
图5是对应于图4的视图,示出了本说明书的实施例的可能的有利发展;以及
图6是根据本说明书实施例的功率半导体器件的平面图。
具体实施方式
一个或多个实施例可以涉及一种方法。
一个或多个实施例可以涉及对应的半导体器件。
一个或多个实施例可以提供以下优点中的一个或多个优点:在整个组装过程中,通过有效地抵消不期望的移动(例如,旋转)来促进准确的夹片定位;并且可以适当地控制焊料厚度。
在一个实施例中,一种方法包括:在衬底中的裸片焊盘上布置至少一个半导体芯片,衬底包括裸片焊盘旁边的至少一个导电焊盘;将至少一个导电夹具定位在至少一个半导体芯片与至少一个导电焊盘之间的桥状位置中,其中在桥状位置中,至少一个导电夹具具有面向至少一个半导体芯片和至少一个导电焊盘的耦合表面;以及将处于桥状位置中的至少一个导电夹具焊接到至少一个半导体芯片和至少一个导电焊盘,以在其间提供电耦合,其中焊接是经由所述耦合表面处的焊接材料进行的。该方法进一步包括,在将至少一个导电夹具定位在至少一个半导体芯片与至少一个导电焊盘之间的桥状位置中之前,提供至少一对互补定位结构,该至少一对互补定位结构包括在至少一个导电夹具中的腔体和在至少一个半导体芯片与至少一个导电焊盘中的至少一个中的突起,其中随着在至少一个导电夹具处于所述桥状位置中,在所述焊接期间,互补定位结构相互接合并且将至少一个导电夹具维持在所述桥状位置中。
在一个实施例中,一种器件包括:在衬底中的裸片焊盘上的至少一个半导体芯片,衬底包括裸片焊盘旁边的至少一个导电焊盘;定位在至少一个半导体芯片与至少一个导电焊盘之间的桥状位置中的至少一个导电夹具,至少一个导电夹具具有面向至少一个半导体芯片和至少一个导电焊盘的耦合表面;焊料材料,施加在桥状位置中的至少一个导电夹具的所述耦合表面处,焊料材料将至少一个导电夹具电耦合到至少一个半导体芯片并且电耦合到至少一个导电焊盘;以及至少一对互补定位结构,其包括在所述至少一个导电夹具中的腔体和在至少一个半导体芯片和至少一个导电焊盘中的至少一个中的突起,互补定位结构相互接合。
除非另外指示,否则不同附图中的对应数字和符号通常指代对应部分。
附图是为了清楚地说明实施例的相关方面而绘制的,并且不必按比例绘制。
在附图中画出的特征的边缘不一定指示特征范围的终止。
在随后的描述中示出了一个或多个具体细节,目的在于提供对本描述的实施例的示例的深入理解。可以在没有一个或多个具体细节的情况下,或者利用其他方法、组件、材料等来获得实施例。在其他情况下,没有详细示出或描述已知的结构、材料或操作,从而不会模糊实施例的某些方面。
在本说明书的框架中对“实施例”或“一个实施例”的引用旨在指示关于该实施例描述的特定配置、结构或特性被包括在至少一个实施例中。因此,可能出现在本说明书的一个或多个点中的诸如“在实施例中”或“在一个实施例中”的短语不一定指一个和同一个实施例。
此外,在一个或多个实施例中,特定的构象、结构或特性可以以任何适当的方式被组合。
本文使用的标题/参考仅仅是为了方便而提供的,并且因此不限定保护范围或实施例的范围。
为了简单和易于解释,在整个说明书中,在各个附图中用相同的附图标记指示相同的部分或元件,并且对于每个附图将不重复相对应的描述。
在半导体器件的当前制造工艺中,同时制造多个器件以在最终的分割中被分离成单个的单个器件。为了简单和易于解释,下面的描述将涉及制造单个器件。
图1是具有塑料封装的功率半导体器件10的示例。
如本领域中常规的那样,器件10包括衬底(引线框)12,其上布置有一个或多个半导体集成电路芯片或裸片。本文所使用的术语芯片/多个芯片和裸片/多个裸片被认为是同义的。
附图示出了半导体功率器件10的示例,其包括附着到引线框12中的第一裸片焊盘121A上的低功率部分(例如,控制器集成电路裸片141)和附着到引线框12中的一个或多个裸片焊盘122A上的高功率部分(例如,一个或多个功率集成电路裸片142),其中引线12B的阵列围绕裸片焊盘121A、122A并且具有安装于其上的裸片141和142。
名称“引线框”(或“引线框架”)目前被用于(例如,参见美国专利和商标局的USPC合并词汇表)以指示为集成电路芯片或裸片提供支撑的金属框,以及将裸片或芯片中的集成电路互连到其它组件或触点的电引线。
实质上,引线框包括导电结构(或引线,例如12B)的阵列,其从轮廓位置沿半导体芯片或裸片(例如141、142)的方向向内延伸,从而由裸片焊盘(例如121A、122A)形成导电结构的阵列,裸片焊盘被配置为具有附着到其上的至少一个半导体芯片或裸片。这可以经由诸如裸片附着粘合剂1420(例如,裸片附着膜(DAF))的常规手段。
图1所示的器件旨在使用例如焊料材料被安装在诸如印刷电路板(PCB-在图中不可见)的衬底上。
导电结构被提供以将(多个)半导体芯片141、142电耦合到引线框12中选定的引线(外部焊盘)12B。
如图所示,这些导电结构包括将低功率部分(芯片141)耦合到选定的引线12B和高功率部分(一个或多个芯片142)的引线接合图案16。这些引线接合图案16被耦合到芯片141和142的前表面或顶表面处提供的裸片焊盘1410。
相反,所谓的夹片18被用于将高功率部分(一个或多个芯片142)耦合到用作器件10的(功率)输出焊盘的选定的引线12B。
使用夹片18代替被包括在引线接合图案16中的引线(用于提供到低功率部分(例如,控制器141)的电耦合)考虑到从高功率部分142传输到功率半导体器件中的输出焊盘的电流可能相当大的事实。如上所述,诸如导线16的导线仍然被用于向设备中的低功率部分(例如,控制器)提供电耦合。
绝缘封装20(例如,环氧树脂)被模制在因此形成的组件上,以完成器件10的塑料主体。
虽然所示的器件10包括两个夹片18,但是某些器件可以仅包括一个夹片或多于两个夹片。
如本文所解释的,这种器件结构在本领域中是常规的,这使得本文不需要提供更详细的描述。
总之,出于本文的目的,生产如本文所讨论的器件10包括:将至少一个半导体芯片142布置在衬底12中的裸片焊盘12A上,衬底12包括通过即,与裸片焊盘12A相邻或并排)裸片焊盘12A的至少一个导电焊盘12B;以及将至少一个导电夹具18定位在至少一个半导体芯片142与至少一个导电焊盘12B之间的桥状位置中。
在这种桥状位置中,导电夹具18具有面向半导体芯片142和导电焊盘12B的耦合表面。
位于所述桥状位置中的导电夹具18被焊接到半导体芯片142和导电焊盘12B,以在其间提供电耦合。
如图所示,经由在所述耦合表面处分配的焊接材料22(以本领域技术人员已知的方式)来实现焊接。焊接材料22被固化(以本领域技术人员本身已知的方式),例如经由在烘箱中热处理。
如所讨论的,使用夹片附着设备放置诸如夹片18的夹片,并且使用焊膏22将夹片连接到焊盘和裸片。在炉中固化的焊料被应用以提供夹片18到焊盘(例如12B)和裸片(例如142)的牢固连接。
常规的夹片附着设备有助于在芯片放置中实现足够精度,因为夹片18被桥状地应用在诸如裸片142的裸片和诸如焊盘/引线12A的相应焊盘/引线之间:这种情况被认为是简单的;在某些器件中,单独的夹片18可以被耦合到例如多个焊盘/引线。
在夹片放置之后,将组件转移到烘箱中用于焊料固化。在该处理和固化过程期间,夹片可能从期望的正确位置移位,这可能导致有缺陷的最终产品。
焊料22的厚度和夹片在流体状态下“漂浮”在焊料22上的趋势也可能基于不期望的过度夹片倾斜。
通过在夹片和引线框设计中添加固定特征,可以试图抵消不期望的夹片移动(位移)。
平滑处理也可以有助于在夹片放置中实现非常精确的夹片居中。
也可以考虑选择抵消不期望的夹片浮动特性的焊膏材料。
由于各种原因,这些解决方案中没有一个看起来完全令人满意。
例如,添加到夹片/引线框设计的某些特征可能是占用空间的,这可能建议减小焊盘尺寸和/或使用更大的封装尺寸来获得空间,这两者都不是有吸引力的/期望的。
所涉及的部件的处理已经是相当温和的过程,并且在这些方向上的进一步改进是难以想象的。
选择不同于常规使用的焊膏材料在热性能和电性能方面可能具有负面影响。
本文所考虑的示例利用了被配置用于在半导体器件制造工艺中形成所谓的柱形凸起的设备(例如,引线接合设备)的当前可用性。
在常规的引线接合中(例如,如被用于提供先前论述的引线接合图案16),在引线金属材料诸如例如,铝(Al)、铜(Cu)和金(Au)的末端处形成球,其被接合到裸片焊盘。然后,导线向形成第二引线接合的引线延伸。
如果引线在第一次接合之后终止,则仅在裸片焊盘上形成“凸起”。这样的凸起可以被用于互连到例如使用热声波或热压缩工艺倒装到衬底上的裸片。
在本文所考虑的示例中,一个或多个柱形凸起100被形成于期望将夹片18耦合到其上的焊盘/引线12B上。一个或多个对应的凹槽或腔体102被形成为例如夹片18中面向焊盘/引线12B的表面处的圆柱形(盲)孔,使得一个凸起或多个凸起100可以穿透到这些凹槽或腔体102中。凸起100/腔体102对可以例如被定位在图1所示的区域180处。
因此,每个凸起100/腔体102对可以提供居中特征,其抵消夹片18相对于焊盘12B(以及相对于衬底12和芯片或多个芯片142)的不期望的相互位移。
因此,本文所示的方法包括在焊接之前提供至少一对互补定位结构,诸如导电夹具18中的腔体102和导电焊盘12B中的突起100。
互补定位结构100、102响应于导电夹具18被定位在期望的桥状位置中而相互接合。
因此,互补定位结构100、102在焊接过程(例如经由在烘箱中热固化而输送和固结的焊膏)期间将夹片18保持在这种桥状位置中,以抵消不期望的位移和“漂浮”到熔融状态的焊膏上。
在夹片或每个夹片中提供至少两对凸起100/腔体102(例如,见图6)有利地抵消夹片18相对于焊盘12B、衬底12和(多个)芯片142的相互旋转。
可以使用例如金或(较不昂贵的)铜材料的其它常规引线接合技术在焊盘12B上产生并且接合诸如柱形凸起100的柱形凸起。
夹片18上的凹陷或腔体120可以在生产夹片时产生,例如在夹片冲压(金属材料,诸如例如铜)以在其上提供期望的形状期间。
如图4和5中可见,可以产生多个堆起/堆叠的柱形凸起100以提供锚定“柱”,其被配置为将某一长度穿入相应凹陷102中(例如,直到凹陷102的末端表面)。
如图5所示,可以形成一个或多个“间隔”柱形凸起100',其在夹片18中没有凹陷配对物,以保持夹片18(稍微)远离焊盘12B,从而在夹片18和焊盘12A之间提供受控宽度的间隙。
这种间隙可以被焊料材料22穿透。发现这种布置在控制(最小)焊料厚度和抵抗不期望的夹片倾斜方面是有益的。
本文提出的示例有助于在组装过程期间保持精确的夹片“居中”,从而抵消不期望的移位(平移、旋转、倾斜)。可以适当地控制焊料厚度。
在本文所呈现的示例中,定位结构100(例如,柱状凸起)被形成为从引线框12中的焊盘/引线12B突出并且接合夹片18中的相应腔体102(例如,盲孔)。
至少在原理上,这种定位结构100也可以被形成在或仅被形成在裸片焊盘处,诸如芯片或裸片142的前表面或顶表面处提供的裸片焊盘1410处(如本领域中常规的)。
此外,也可以(或仅)在夹片18的表面上提供例如图中所示的柱形突起100’的间隔柱形突起。
应当注意,从焊盘/引线突出并且结合夹片18中的相应腔体102(例如,盲孔)的(多个)锚定结构100的存在在最终器件中也将是明显的,即使甚至在焊料材料22被提供在夹片18与夹片被焊接到的焊盘12B之间之后。
在不违背基本原则的情况下,细节和实施例可以相对于仅通过示例描述的内容而改变,甚至显著改变,而不脱离保护范围。
本公开的技术方案是本文提供的实施例的技术教导的整体部分。
保护范围由本公开的技术方案确定。
根据本公开的第一方面,提供了一种方法,包括:将半导体集成电路芯片布置在衬底的裸片焊盘上,所述衬底包括所述裸片焊盘旁边的导电焊盘;提供一对互补定位结构,所述互补定位结构包括在导电夹具中的腔体和在所述半导体集成电路芯片或所述导电焊盘中的至少一项中的突起;将所述至少一个导电夹具定位在所述半导体集成电路芯片和所述导电焊盘之间的桥状位置中,其中所述互补定位结构相互接合;其中所述导电夹具在所述桥状位置中具有面向所述半导体集成电路芯片和所述导电焊盘的耦合表面;以及将在所述桥状位置中的所述导电夹具焊接至所述半导体集成电路芯片和所述导电焊盘以在所述半导体集成电路芯片和所述导电焊盘之间提供电耦合,其中焊接是经由在所述耦合表面处的焊接材料进行的。
在一些实施例中,其中提供所述一对互补定位结构包括提供至少两对互补定位结构,其中所述至少两对互补定位结构在所述焊接期间抵消所述至少一个导电夹具相对于所述桥状位置的旋转。
在一些实施例中,其中提供所述一对互补定位结构包括在所述导电夹具中形成所述腔体以及在所述导电焊盘中形成所述突起。
在一些实施例中,其中所述腔体包括盲孔。
在一些实施例中,其中所述突起包括柱形凸起。
在一些实施例中,其中所述突起包括多个柱形凸起的堆叠。
在一些实施例中,方法进一步包括,在所述焊接之前,在所述半导体集成电路芯片和所述导电焊盘中的至少一项上,在与所述一对互补定位结构间隔开的位置处提供间隔结构,其中所述间隔结构被配置为在所述焊接期间将所述导电夹具保持离所述半导体集成电路芯片和所述导电焊盘中的一项或多项一距离。
在一些实施例中,其中所述间隔结构包括柱形凸起。
Claims (9)
1.一种半导体器件,其特征在于,包括:
衬底,所述衬底包括裸片焊盘旁边的导电焊盘;
半导体集成电路芯片,被安装至所述衬底的所述裸片焊盘;
导电夹具,位于半导体集成电路芯片和所述导电焊盘之间的桥状位置中,所述导电夹具具有面向所述半导体集成电路芯片和所述导电焊盘的耦合表面;
焊料材料层,被施加在所述桥状位置中的所述导电夹具的所述耦合表面处,所述焊料材料层将所述导电夹具电耦合至所述半导体集成电路芯片并且电耦合至所述导电焊盘;以及
一对互补定位结构,包括在所述导电夹具中的腔体和在所述半导体集成电路芯片和所述导电焊盘中的至少一项中的突起,所述互补定位结构相互接合。
2.根据权利要求1所述的半导体器件,其特征在于,进一步包括另一对互补定位结构。
3.根据权利要求1所述的半导体器件,其特征在于,所述一对互补定位结构包括所述导电夹具中的所述腔体和所述导电焊盘中的所述突起。
4.根据权利要求1所述的半导体器件,其特征在于,所述腔体包括盲孔。
5.根据权利要求1所述的半导体器件,其特征在于,所述突起包括柱形凸起。
6.根据权利要求1所述的半导体器件,其特征在于,所述突起包括多个柱形凸起的堆叠。
7.根据权利要求1所述的半导体器件,其特征在于,进一步包括在所述半导体集成电路芯片和所述导电焊盘中的至少一项上的、在与所述一对互补定位结构间隔开的位置处的间隔结构,其中所述间隔结构被配置为将所述导电夹具保持离所述半导体集成电路芯片和所述导电焊盘一距离。
8.根据权利要求7所述的半导体器件,其特征在于,所述间隔结构是柱形凸起。
9.根据权利要求1所述的半导体器件,其特征在于,所述半导体集成电路芯片是功率半导体集成电路,其中所述导电夹具的大小和尺寸被配置为承载由所述功率半导体集成电路产生的电流。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT102022000001646 | 2022-02-01 | ||
IT202200001646 | 2022-02-01 | ||
US18/102,147 | 2023-01-27 | ||
US18/102,147 US20230245994A1 (en) | 2022-02-01 | 2023-01-27 | Method of manufacturing semiconductor devices and corresponding semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN219917157U true CN219917157U (zh) | 2023-10-27 |
Family
ID=80999633
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202320093604.XU Active CN219917157U (zh) | 2022-02-01 | 2023-01-31 | 半导体器件 |
CN202310048484.6A Pending CN116544125A (zh) | 2022-02-01 | 2023-01-31 | 制造半导体器件的方法和对应的半导体器件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202310048484.6A Pending CN116544125A (zh) | 2022-02-01 | 2023-01-31 | 制造半导体器件的方法和对应的半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20230245994A1 (zh) |
EP (1) | EP4220692A1 (zh) |
CN (2) | CN219917157U (zh) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110750A (ja) | 2000-09-29 | 2002-04-12 | Mitsubishi Electric Corp | 電子部品の製造方法並びに接続構造 |
US20070284703A1 (en) | 2006-06-07 | 2007-12-13 | Lite-On Semiconductor Corporation | Semiconductor package structure |
JP2015142072A (ja) | 2014-01-30 | 2015-08-03 | 株式会社東芝 | 半導体装置 |
-
2023
- 2023-01-27 US US18/102,147 patent/US20230245994A1/en active Pending
- 2023-01-30 EP EP23153878.6A patent/EP4220692A1/en active Pending
- 2023-01-31 CN CN202320093604.XU patent/CN219917157U/zh active Active
- 2023-01-31 CN CN202310048484.6A patent/CN116544125A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
CN116544125A (zh) | 2023-08-04 |
US20230245994A1 (en) | 2023-08-03 |
EP4220692A1 (en) | 2023-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6369454B1 (en) | Semiconductor package and method for fabricating the same | |
KR100285664B1 (ko) | 스택패키지및그제조방법 | |
JP2844316B2 (ja) | 半導体装置およびその実装構造 | |
US6897552B2 (en) | Semiconductor device wherein chips are stacked to have a fine pitch structure | |
US6624006B2 (en) | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip | |
TWI496262B (zh) | 多導線架封裝 | |
US6310395B1 (en) | Electronic component with anodically bonded contact | |
US6879037B2 (en) | Semiconductor device and a method of manufacturing the same | |
JP2005506690A (ja) | 積層パッケージ | |
US6750080B2 (en) | Semiconductor device and process for manufacturing the same | |
KR100389230B1 (ko) | 개별반도체장치및그제조방법 | |
US7923835B2 (en) | Package, electronic device, substrate having a separation region and a wiring layers, and method for manufacturing | |
JP2000294715A (ja) | 半導体装置及び半導体装置の製造方法 | |
KR19990069447A (ko) | 반도체 패키지와 그 제조방법 | |
CN107534036B (zh) | 用于具有垂直堆叠的芯片和组件的电子系统的引线框架 | |
KR100343150B1 (ko) | 금속터미널을구비하는전력반도체모쥴,전력반도체모쥴의금속터미널제조방법및전력반도체모쥴의제조방법 | |
CN219917157U (zh) | 半导体器件 | |
KR19980070675A (ko) | 오프셋 다이 패드를 갖는 반도체 패키지 및 그 제조 방법 | |
JPH09312372A (ja) | 半導体装置の製造方法 | |
KR100437821B1 (ko) | 반도체 패키지 및 그 제조방법 | |
CN219591387U (zh) | 半导体设备 | |
JP3938525B2 (ja) | 半導体装置の製造方法 | |
KR19990051002A (ko) | 적층형 패키지 및 그 제조방법 | |
KR100250145B1 (ko) | 비지에이반도체패키지와그제조방법 | |
JP3434633B2 (ja) | 樹脂封止型半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |