CN1157774C - 半导体器件的制造方法和半导体器件 - Google Patents
半导体器件的制造方法和半导体器件 Download PDFInfo
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- CN1157774C CN1157774C CNB011329971A CN01132997A CN1157774C CN 1157774 C CN1157774 C CN 1157774C CN B011329971 A CNB011329971 A CN B011329971A CN 01132997 A CN01132997 A CN 01132997A CN 1157774 C CN1157774 C CN 1157774C
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Abstract
提供可以使电力元件用多引脚封装的内部连接简化的构成和制造方法。通过连接剂把具有主电极和比该主电极面积小的副电极的半导体芯片装载到引线框架的管芯垫上,通过连接剂把用连杆把各自的内部引线连接起来的内部引线框架,装载到半导体芯片的主电极和副电极及引线框架的对应的外部引线之间,导电性地同时把内部引线和半导体芯片和外部引线之间固定粘接起来,然后切断连杆,把内部引线框架分离成各个内部引线。
Description
技术领域
本发明涉及具有多个引脚的半导体器件的制造方法和用该方法得到的半导体器件。
背景技术
近些年来,随着便携式电子设备的普及,人们特别要求半导体封装的小型薄型化、轻重量化和高性能化。以前,半导体芯片的上部电极用金丝键合法连接到外部引线上。此外,在二极管等的2端器件的情况下,则用焊接通过内部引线连接到外部引线上。
此外,在电力-MOSFET等的3端产品的情况下,由于要处理比较大的大电流,故虽然焊接引线是理想的,但是,由于设置在芯片上表面上的栅极电极与源极电极相比非常小,故即便是想焊接内部引线也得不到应有的位置精度。为此,为了确保电流容量,栅极电极用单线的键合金丝进行连接,源极电极用多条键合金丝进行连接。
虽然有着栅极电极用可以用细线进行连接的金丝键合,源极电极用对散热和导通电阻有利的内部引线的焊接进行连接的各不相同的进行连接的方法,但是,需要改变电极的表面处理:栅极电极要改变为金丝键合用的电极(例如Al),源极电极要改变为焊接用的电极(例如VNiAu),这将招致制造设备价格和制造价格的增加。
此外,虽然电力-MOSFET大多是把2个串联连接起来使用,但是以前用印制基板的布线进行该种串联连接。若使用该方法,将发生由布线产生的寄生电感和布线电阻,招致性能的降低。
发明内容
本发明就是考虑到上述问题而发明的,目的是提供在半导体器件的内部布线中,作业性优良、可靠性高的向外部引线进行连接的连接方法。此外,还提供用上述的制造方法得到的半导体器件,和在应用上述连接方法的半导体封装内可以把2个半导体芯片串联连接起来的构成。
为了解决上述课题,本发明的半导体器件的制造方法的第1方面的特征是具备下述工序:把在上表面上具有主电极和比该主电极面积小的副电极的半导体芯片,通过第一连接剂装载到外部引线框架的管芯垫上的工序;把用连杆连接着把上述半导体芯片的主电极和副电极连接到上述外部引线框架的对应的连接用焊盘上的各内部引线的内部引线框架,通过第二连接剂装载到上述半导体芯片和上述外部引线框架上的工序;加热上述第一连接剂和第二连接剂,在上述半导体芯片与上述管芯垫之间、上述内部引线与上述半导体芯片的电极和上述外部引线框架的连接焊盘之间,同时导电性地进行粘接固定的工序;和切断上述连杆,把上述内部引线框架分离成各内部引线的工序。
此外,本发明的半导体器件的第2方面的特征是:具备装载到引线框架的管芯垫上边,具有主电极和比该主电极面积小的副电极的半导体芯片;具有连接在上述半导体芯片的主电极和副电极及上述引线框架的对应的外部引线的连接焊盘之间,在各自的内部引线之间被切断的连杆的内部引线框架。
上述的半导体器件,理想的是如下所述地构成。
(1)连杆比内部引线框架的其它部分的厚度薄。
(2)连杆被设置在与外部引线框架相邻的外部引线的中央附近。
(3)管芯垫,在与连杆相邻的部分处,具有离开该连杆一定距离那样后退的缺口部分。
(4)内部引线框架的连杆部分形成得比半导体芯片的上表面还高。
此外,本发明的半导体器件的第7方面具备:装载到与外部引线框架相邻的第1和第2管芯垫上边,每一个都具有主电极和比该主电极面积小的副电极的第1和第2半导体芯片;具有连接在上述第1和第2半导体芯片的各自的主电极和副电极及上述外部引线框架的对应的外部引线之间的内部引线和在每一条内部引线之间被切断的连杆的内部引线框架;在上述第1和第2管芯垫的相向的边上垂直于上述第1管芯垫形成的突起引线部分;与要连接到已装载到上述第2管芯垫上的第2半导体芯片的主电极上的内部引线形成一个整体,具有与上述突起引线部分进行彼此嵌入的缺口部分,与上述突起引线部分导电性地连结的连接引线部分。
上述半导体器件,理想的是如下所述地构成。
(1)在突起引线部分的上端,具有从上端面后退支持连接引线部分的平坦部分。
(2)第1和第2半导体器件是MOSFET芯片,第1半导体器件,是内置有并联地连接到MOSFET上的肖特基二极管的芯片。
此外,本发明的半导体器件,其特征是包括:多条外部引线;与上述多条外部引线相邻的管芯垫;装载到上述管芯垫上并具有主电极和比该主电极面积小的副电极的半导体芯片;配置把上述半导体芯片的主电极和副电极连接到上述多条外部引线的对应的连接用焊盘上的两条内部引线,上述两条内部引线分别具有连杆的切断剩余部分。
此外,本发明的半导体器件,其特征是包括:多条外部引线;与上述多条外部引线并列相邻设置的第1和第2管芯垫;各自具有主电极和比该主电极面积小的副电极的第1和第2半导体芯片;把上述第1和第2半导体芯片各自的主电极和副电极连接到上述多条外部引线的对应的连接用焊盘上的两对内部引线,上述每一对内部引线具有连杆的切断剩余部分;在面向上述第2管芯垫的上述第1管芯垫的一侧垂直于上述第1管芯垫而形成的突起引线部分;与要连接到已装载到上述第2管芯垫上的第2半导体芯片的主电极上的内部引线形成一个整体,具有与上述突起引线部分进行彼此嵌入的缺口部分,与上述突起引线部分导电性地连结的连接引线部分。
附图说明
图1是用来说明本发明的实施例1的半导体器件的内部连接方法的平面图和沿A-A线的剖面图。
图2是本发明的内部引线框架的平面图。
图3是本发明的实施例2的半导体器件的平面图。
图4是本发明的实施例3的半导体器件的内部引线框架的平面图和沿B-B线的剖面图。
图5是本发明的实施例4的半导体器件的内部引线框架的平面图。
图6是本发明的实施例5的半导体器件的内部引线框架的平面图。
图7是用来说明本发明的实施例6的半导体器件的内部连接方法的平面图和沿C-C线的剖面图。
图8是沿图7的D-D线的剖面图。
图9是在实施例的应用中使用的同步整流电路的电路图。
具体实施方式
以下,参看附图说明本发明的实施例。
实施例1
图1是用来说明本发明的实施例1的半导体器件的制造方法的图,图1(a)的平面图示出了把半导体芯片装配到引线框架上边,用内部引线把半导体芯片的上表面电极和引线框架的外部引线连接起来的状态,图1(b)是沿图1(a)的A-A线的剖面图。
在图1中,1是引线框架的管芯垫,3是引线框架的外部引线,5是与外部引线3形成一个整体的内部引线连接用焊盘,7是引线框架的连杆,构成熟知的树脂密封用引线框架。为了与后述的内部引线框架进行区别,决定以后称之为外部引线框架。
半导体芯片9通过连接剂21a被装配到外部引线框架的管芯垫1上。作为连接剂21a,可以使用焊料或导电性粘接剂。半导体芯片9,例如,是MOSFET,在芯片上表面上具有电极面积大的源极电极(主电极)11和电极面积小的栅极电极(副电极)13,芯片下表面的漏极电极,如上所述,通过连接剂连接到管芯垫1上。
实施例1的特征是:连接往源极电极11和栅极电极13的外部引线框架的取出引线(内部引线)用由板状金属构成的内部引线框架进行连接。内部引线框架由源极电极引线15和栅极电极引线17构成,此外,还具有把两者连接起来的连杆19。连杆19在内部引线框架安装好以后,用剪线机等切断。连杆被设计为位于相邻的外部引线之间的大体上中央。
此外,内部引线框架用冲压加工等由例如铜或铜合金的板形成,如图1(a)所示,被加工为使芯片上表面与外部引线上表面的高度相一致。这时,含有连杆19的部分被成型为比芯片上表面高,借助于此,使连杆的切断变得容易起来。
内部引线框架,如图2所示,以用框架23把多个内部引线组(源极电极15和栅极电极17的组)连接起来的形态供给,在连接到芯片和外部引线框架上之前,要在悬挂引脚25的引线一侧的根部切断。每一个内部引线框架(内部引线组)都具有要连接到芯片上的上表面电极(源极电极11和栅极电极13)上的芯片焊盘部分15a、17a和要连接到外部引线上的引线焊盘部分15b、17b。芯片焊盘部分15a、17a和引线焊盘部分15b、17b,分别用连接剂21b、21c连接到芯片电极11、13和外部引线连接焊盘5上。连接剂21b、21c可以使用焊料或导电性粘接剂,理想的是作成为与在管芯装配时使用的连接剂21a相同的材料,但是也可以根据要求使用不同的材料。
其次,说明图1的带引线构成的制造工序。首先,用分配器向引线框架的管芯垫1和连接内部引线的外部引线的连接焊盘5适量供给例如乳剂状的焊料(焊料膏)。也可以不使用分配器而代之以使用印刷法。
其次,使用管芯装配器等,向引线框架的管芯垫11上边,装配半导体芯片9。然后,使用分配器等向芯片的源极电极11、栅极电极13的上边适量供给焊料膏。在管芯装配中使用的焊料膏和在引线安装中使用的焊料膏,可以使用同样的焊料膏。
其次,把内部引线框架从连接到框架上的状态切断成源极电极引线15和栅极电极引线17构成的一个组的量,位置对准到半导体芯片和外部引线框架上边后进行装配。
内部引线用的焊料膏的供给,除去上述方法之外,也可以预先在内部引线框架的芯片焊盘部分15a、17a和引线焊盘部分15b、17b上印刷上焊料膏(图2的虚线部分),位置对准到半导体芯片和外部引线框架上边的规定的位置后进行装配。
其次,使装配完毕的引线框架通入焊料回流炉实施焊料的软化。回流炉既可以是皮带传送式的连续炉,也可以是静止型的回流炉。借助于此,可以使管芯装配用的焊料21a、内部引线用的焊料21b、21c同时软化。
上边所说的虽然是焊料回流的情况,但是,即便是在使用导电性粘接剂的情况下,也可以用分配器或印刷法供给该粘接剂,可以借助于与回流同样的加热工序(热处理)进行固定粘接。
其次,用剪线机切断内部引线框架的连杆19,使源极电极15和栅极电极17分离。由于内部引线框架的连杆19比半导体芯片19的上表面还高,故使剪线机不接触芯片地触碰到连杆19上是容易的。
然后,采用向熟知的树脂模铸工序供给引线框架,模铸后,切断外部引线3的连杆7的办法,完成封装完毕的半导体器件。
本发明的内部引线框架,由于有4个支持点,故在装配时稳定且可以提高位置精度。在现有方法的情况下,在芯片的管芯装配后,还需要进行金丝键合,但在本发明的情况下,由于在芯片的装配后,才进行内部引线框架的装配,芯片和内部引线框架的焊料回流可以同时进行,故可以缩短工序。此外,由于不使用昂贵的金丝,故可以降低造价。
实施例2
实施例2虽然基本上与实施例1是相同的,但管芯垫的形状与实施例1是不一样的。
图3的平面图示出了本发明的实施例2的半导体器件的内部连接状态。对于那些与实施例1相同的部分赋予同一标号而省略重复的说明。在以后的实施例中也同样地处理。
如图3所示,实施例2的特征是:接近管芯垫1a的连杆19的部分从缺口26后退,使得易于进行管芯连杆的切断。
实施例3
图4是本发明的实施例3的内部引线的平面图和连杆19a的一部分(B部分)的沿B-B线的扩大剖面图。在实施例3中,如图4(b)所示,作成为使得连杆19a的切断部分27的厚度比内部引线的厚度(例如0.3mm)还薄(例如0.15mm),以便易于进行切断。
实施例4
实施例4是使内部引线框架进一步变形的实施例。图5是本发明的实施例4的内部引线的平面图,连杆部分由2条连杆19b、19b’构成。借助于此,可以提高连杆部分的刚性,防止源极电极引线15和栅极电极引线17的扭歪等的相对变形。
另外,也可以对于连杆19b、19b’,如图4(b)所示,部分性地设置薄的场所,使切断容易进行。
实施例5
实施例5是使内部引线框架进一步变形的实施例。图6是本发明的实施例5的内部引线的平面图,连杆部分由2条连杆19c、19c’构成。与实施例4的不同之处是:1条连杆19c被设置在外部引线框架的内部引线连接用焊盘5附近。与实施例4同样,可以提高内部引线框架的刚性。此外,对于连杆19c、19c’,也可以如图4(b)所示,部分性地设置薄的场所,使得易于进行切断。
实施例6
图7(a)的平面图示出了本发明的实施例6的半导体器件的引线连接方法,图7(b)示出了其沿C-C线的剖面图。在本实施例中,2个半导体芯片相邻地被装配到引线框架上,在进行了内部引线连接后,作为1个封装进行模铸。另外,沿A-A线的剖面图,与图1(b)的剖面图同样。此外,图8示出了沿图1(b)的D-D线的剖面图。
示于图7的2个半导体芯片111、112,虽然在管芯装配后,用使用在实施例1到实施例5中说明的内部引线框架的连接方法,分别连接到外部引线框架上,但是,图的右侧所示的第1内部引线框架的形状与图的左侧所示的第2内部引线框架的形状不同。第1内部引线框架例示的是实施例1的内部引线框架,但是,也可以使用实施例3或实施例4的内部引线框架。
此外,图的左侧所示的第2管芯垫12,与图的右侧所示的第1管芯垫11的形状也不同。第2管芯垫12,虽然例示的是实施例1的管芯垫,但也可以使用实施例2的管芯垫。
第1管芯垫11,被加工为使得与第2管芯垫12相邻部分的一部分,一直到管芯垫的大体上的中央位置为止被切一个缺口,变成为垂直。该垂直部分将成为突起引线部分33。
另一方面,左侧的第2内部引线框架的源极电极(主电极)引线的一部分,具有在第1芯片方向上延伸的连接引线部分29,使装载第1芯片的管芯垫的突起引线部分33嵌入到在其顶端设置的缺口部分31内。这时,要预先把支持第2芯片的内部引线的连接引线部分29的台阶(平坦部分)35设置在从突起引线部分33的上端面后退的位置上。借助于此,就可以稳定地保持第2内部引线框架。第2内部引线框架的连接引线部分29和第1芯片焊盘的突起引线部分33之间的互相嵌入部分,可以用焊料21d进行接合。
其次,说明实施例6的半导体器件的制造工序。首先,用分配器,向引线框架的管芯垫11、12,连接内部引线的外部引线的焊盘5上适量供给例如焊料膏。也可以不使用焊料膏而代之以使用印刷法。
其次,使用管芯装配机等向引线框架的管芯垫11、12上分别装配半导体芯片91、92。然后使用分配器等向芯片的源极电极111、112,栅极电极131、132的上边适量供给焊料膏。在管芯装配中使用的焊料膏与在安装引线中使用的焊料膏可以使用相同的焊料膏。
其次,从把内部引线框架连接到框架上的状态,切断第1芯片用的源极电极引线151和栅极电极引线171的一组的量,位置对准到半导体芯片的电极和外部引线框架的连接焊盘上边后进行装配。接着,切断第2芯片用的源极电极引线152和栅极电极引线172的一组的量,在位置对准到半导体芯片和外部引线框架上边后进行装配。这时,要作成为使得第2内部引线框架的连接引线部分37的缺口部分31与第1内部引线框架的突起引线部分33进行彼此嵌入,并载置到设置在突起引线部分33上的台阶35上。然后,用分配器向连接引线部分29和突起引线部分33的嵌入部分供给焊料膏21d。
其次,把已装配上芯片和内部引线框架的外部引线框架通入焊料回流炉内实施焊料的软化。回流炉既可以是皮带传送式的连续炉,也可以是静止型的回流炉。借助于此,可以使管芯装配用的焊料21a,内部引线用的焊料21a、21c,连接部分用的焊料21d同时软化。
然后,采用经由与实施例1同样的工序,完成密封完毕的半导体器件。在上边所说的实施例中虽然把焊料膏用做连接剂,但是,当然也可以使用导电性粘接剂。
作为向连接引线部分29的第1管芯11的焊盘进行连接的连接方法,虽然也可以考虑先在下方成型连接引线部分29的顶端,再直接焊接到第1管芯垫11上的方法,但是,这种方法存在着连接所用的焊料与芯片的装配用的焊料进行融合,对装配焊料厚度、芯片的平行度产生不良影响的可能性。对此,在本发明中,由于使用突起引线部分33使焊料部分远离芯片,故不用担心上述那样的不良影响。
实施例6的封装,若应用到图9所示的那种同步整流电路的一部分中去则是有效的。在图9中,Q1是电力-MOSFET,与晶体管符号并列地画出来的二极管是寄生二极管。串联连接到Q1上的Q2是除去寄生二极管以外并联连接上肖特基势垒二极管SBD的电力-MOSFET。在Q1的源极电极S1和Q2的漏极电极D2的连接节点上,作为负载,连接有电感L和电容C的串联电路。肖特基二极管SBD被设置为用做Q1的晶体管截止时的电流通道。
如果把上述的电路的Q2作为第1半导体芯片,把Q2作为第2半导体芯片,并应用实施例6的封装,就可以实现使同步整流电路的一部分单个封装化的半导体器件。如果像这样地使半导体器件电路单个封装化,则与用布线基板进行布线的情况比,可以减少寄生电感和布线电阻,可以提高元器件性能和装配效率。
以上根据实施例对本发明进行了说明,但是本发明并不受限于上述实施例,可以有种种的变形。例如,在实施例6中,虽然说明的是2个芯片的情况,但是,对于3个芯片以上的多芯片也可以使用。
如上所述,倘采用本发明,采用使用内部引线框架的办法,与进行芯片装配的焊接工序同时,对于栅极电极这样的小电极也可以进行内部引线的焊接,可以使工序简化。不再用使用昂贵的金丝的金丝键合工序,设备也得以简化。
此外,如果把本发明应用于模铸2个芯片以上的多芯片封装,则可以减少由布线基板产生的寄生电感和布线电阻,提高元器件性能,可以减少印制基板的装配面积。
Claims (20)
1.一种半导体器件的制造方法,其特征是包括下述工序:
把在上表面上具有主电极和比该主电极面积小的副电极的半导体芯片,通过第一连接剂装载到外部引线框架的管芯垫上的工序;
把用连杆连接着把上述半导体芯片的主电极和副电极连接到上述外部引线框架的对应的连接用焊盘上的各内部引线的内部引线框架,通过第二连接剂装载到上述半导体芯片和上述外部引线框架上的工序;
加热上述第一连接剂和第二连接剂,在上述半导体芯片与上述管芯垫之间、上述内部引线与上述半导体芯片的电极和上述外部引线框架的连接焊盘之间,同时导电性地进行粘接固定的工序;和
切断上述连杆,把上述内部引线框架分离成各内部引线的工序。
2.权利要求1所述的半导体器件的制造方法,其特征是还包括下述工序:
在装载上述内部引线框架的工序之后,通过第三连接剂连接上述内部引线框架的一部分与上述外部引线框架的另外的管芯垫的工序。
3.权利要求1所述的半导体器件的制造方法,其特征是:上述第一连接剂包含焊料或导电性粘接剂。
4.权利要求1所述的半导体器件的制造方法,其特征是:上述第二连接剂包含焊料或导电性粘接剂。
5.权利要求1所述的半导体器件的制造方法,其特征是:上述第三连接剂包含焊料或导电性粘接剂。
6.权利要求1所述的半导体器件的制造方法,其特征是:上述第一连接剂和第二连接剂包含相同的材料。
7.权利要求1所述的半导体器件的制造方法,其特征是:上述第一连接剂和第三连接剂包含相同的材料。
8.一种半导体器件,其特征是包括:
多条外部引线;
与上述多条外部引线相邻的管芯垫;
装载到上述管芯垫上并具有主电极和比该主电极面积小的副电极的半导体芯片;
配置把上述半导体芯片的主电极和副电极连接到上述多条外部引线的对应的连接用焊盘上的两条内部引线,上述两条内部引线分别具有连杆的切断剩余部分。
9.权利要求8述的半导体器件,其特征是:上述连杆比上述内部引线框架的其它部分的厚度薄。
10.权利要求8所述的半导体器件,其特征是:上述连杆被设置在与上述两条内部引线连接的上述外部引线之间的中央。
11.权利要求8所述的半导体器件,其特征是:上述连杆包括连接在两条内部引线之间并被分开设置的多个分连杆。
12.权利要求8所述的半导体器件,其特征是:上述管芯垫在面向上述连杆的纵向面的部分上具有缺口。
13.权利要求8所述的半导体器件,其特征是:上述两条内部引线具有形成得比上述半导体芯片的顶部还高的连杆部分。
14.权利要求8所述的半导体器件,其特征是:上述半导体芯片包含MOS型场效应晶体管。
15.一种半导体器件,其特征是包括:
多条外部引线;
与上述多条外部引线并列相邻设置的第1和第2管芯垫;
各自具有主电极和比该主电极面积小的副电极的第1和第2半导体芯片;
把上述第1和第2半导体芯片各自的主电极和副电极连接到上述多条外部引线的对应的连接用焊盘上的两对内部引线,上述每一对内部引线具有连杆的切断剩余部分;
在面向上述第2管芯垫的上述第1管芯垫的一侧垂直于上述第1管芯垫而形成的突起引线部分;
与要连接到已装载到上述第2管芯垫上的第2半导体芯片的主电极上的内部引线形成一个整体,具有与上述突起引线部分进行彼此嵌入的缺口部分,与上述突起引线部分导电性连接的连接引线部分。
16.权利要求15所述的半导体器件,其特征是:在上述突起引线部分的上端具有支持上述连接引线部分的平坦部分。
17.权利要求15所述的半导体器件,其特征是:上述第1和第2半导体芯片各自包含MOS型场效应晶体管,上述第1半导体芯片还包含与MOS型场效应晶体管并联连接的肖特基二极管。
18.权利要求15所述的半导体器件,其特征是:上述连杆比上述内部引线框架的其它部分的厚度薄。
19.权利要求15所述的半导体器件,其特征是:上述连杆被设置在与上述两条内部引线连接的上述外部引线之间的中央。
20.权利要求15所述的半导体器件,其特征是:上述管芯垫在面向上述连杆的纵向面的部分上具有缺口。
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KR970002140B1 (ko) | 1993-12-27 | 1997-02-24 | 엘지반도체 주식회사 | 반도체 소자, 패키지 방법, 및 리드테이프 |
JPH08116013A (ja) * | 1994-10-18 | 1996-05-07 | Dainippon Printing Co Ltd | リードフレームとこれを用いて組み立てられた半導体装置 |
US5925926A (en) * | 1997-03-19 | 1999-07-20 | Nec Corporation | Semiconductor device including an inner lead reinforcing pattern |
JP2891233B2 (ja) * | 1997-04-11 | 1999-05-17 | 日本電気株式会社 | 半導体装置 |
KR100235308B1 (ko) * | 1997-06-30 | 1999-12-15 | 윤종용 | 2중 굴곡된 타이바와 소형 다이패드를 갖는 반도체 칩 패키지 |
JPH11121676A (ja) * | 1997-10-21 | 1999-04-30 | Hitachi Cable Ltd | リードフレーム |
JPH11297916A (ja) | 1998-04-07 | 1999-10-29 | Matsushita Electron Corp | 半導体装置 |
US6144093A (en) * | 1998-04-27 | 2000-11-07 | International Rectifier Corp. | Commonly housed diverse semiconductor die with reduced inductance |
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
JP3741550B2 (ja) | 1998-10-09 | 2006-02-01 | シャープ株式会社 | 半導体装置およびその製造方法 |
KR100359361B1 (ko) * | 1998-12-17 | 2002-10-31 | 닛뽕덴끼 가부시끼가이샤 | 리드 프레임 및 이를 포함한 반도체 장치의 제조방법 |
-
2000
- 2000-09-21 JP JP2000287385A patent/JP4102012B2/ja not_active Expired - Fee Related
-
2001
- 2001-06-27 US US09/891,316 patent/US6919644B2/en not_active Expired - Fee Related
- 2001-07-12 TW TW090117123A patent/TW558816B/zh not_active IP Right Cessation
- 2001-08-16 KR KR10-2001-0049306A patent/KR100483142B1/ko not_active IP Right Cessation
- 2001-09-13 CN CNB011329971A patent/CN1157774C/zh not_active Expired - Fee Related
-
2005
- 2005-01-10 US US11/030,981 patent/US20050121799A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103367178A (zh) * | 2012-03-27 | 2013-10-23 | 德州仪器公司 | 堆叠半导体封装 |
CN112992818A (zh) * | 2021-04-26 | 2021-06-18 | 佛山市国星光电股份有限公司 | 一种功率器件及其制作方法 |
CN112992818B (zh) * | 2021-04-26 | 2022-03-18 | 佛山市国星光电股份有限公司 | 一种功率器件及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1345083A (zh) | 2002-04-17 |
KR20020023108A (ko) | 2002-03-28 |
US20050121799A1 (en) | 2005-06-09 |
TW558816B (en) | 2003-10-21 |
KR100483142B1 (ko) | 2005-04-14 |
US20020033541A1 (en) | 2002-03-21 |
JP4102012B2 (ja) | 2008-06-18 |
JP2002100716A (ja) | 2002-04-05 |
US6919644B2 (en) | 2005-07-19 |
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