TWI726063B - 具有夾具對準刻痕的半導體封裝和相關方法 - Google Patents

具有夾具對準刻痕的半導體封裝和相關方法 Download PDF

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TWI726063B
TWI726063B TW106107376A TW106107376A TWI726063B TW I726063 B TWI726063 B TW I726063B TW 106107376 A TW106107376 A TW 106107376A TW 106107376 A TW106107376 A TW 106107376A TW I726063 B TWI726063 B TW I726063B
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lead frame
die
score
clamp
notch
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TW106107376A
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TW201803047A (zh
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馬可 艾倫 馬翰倫
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美商艾馬克科技公司
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Abstract

在一個實施例中，一種電子組件可包括引線框架及第一半導體晶粒。引線框架可包括引線框架頂部側、與引線框架頂部側相對的引線框架底部側，及在引線框架頂部側處的頂部刻痕。頂部刻痕可包括頂部刻痕基底，頂部刻痕基底位於引線框架頂部側與引線框架底部側之間，且界定頂部刻痕的刻痕長度；且頂部刻痕還可包括頂部刻痕第一側壁，頂部刻痕第一側壁沿著刻痕長度從引線框架頂部側延伸到頂部刻痕基底。第一半導體晶粒可包括晶粒頂部側、與晶粒頂部側相對且安裝到引線框架頂部側上的晶粒底部側，及晶粒周邊。頂部刻痕可位於晶粒周邊的外側。本文中還揭示其它實例及相關方法。

Description

具有夾具對準刻痕的半導體封裝和相關方法
本發明大體來說涉及電子裝置，且更特定來說，涉及具有夾具對準刻痕的半導體封裝和相關方法。
相關申請案交叉參考
本申請案主張於2016年7月11日申請的美國專利申請案第15/207,462號的優先權，所述美國專利申請案的內容特此以全文引用的方式併入本文中。
現有半導體封裝及用於生產此些封裝的方法可遭受不一致，例如，歸因於在形成或耦合此些封裝的封裝組件時的變化性。例如，在將導電夾具附接到引線框架時，可由於此夾具的夾具尾長度及/或夾具彎曲角度的製造或工具磨損變化而影響所述導電夾具與半導體晶粒之間的平面對準及/或耦合。因此，期望具有解決之前所述問題以及其它問題同時成本有效且容易併入製造流程中的半導體封裝結構及方法。
本發明的一態樣提供一種電子組件，其包括：引線框架頂部平面；引線框架底部平面，其與所述引線框架頂部平面平行；引線框架， 其包括：引線框架頂部側，其包括：引線框架頂端，所述引線框架頂部平面沿著所述引線框架頂端延伸；引線框架底部側，其包括：引線框架底端，所述引線框架底部平面沿著所述引線框架底端延伸；及頂部刻痕，其包括：頂部刻痕基底，其位於所述引線框架頂部平面與所述引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；及第一半導體晶粒，其包括：晶粒頂部側；晶粒底部側，其安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間，且界定晶粒周邊；其中所述頂部刻痕位於所述晶粒周邊外部。
本發明還提供一種電子組件，其包括：引線框架，其包括：引線框架頂部側；引線框架底部側，其與所述引線框架頂部側相對；及頂部刻痕，其位於所述引線框架頂部側且包括：頂部刻痕基底，其位於所述引線框架頂部側與所述引線框架底部側之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；及第一半導體晶粒，其包括：晶粒頂部側；晶粒底部側，其與所述晶粒頂部側相對且安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間，且界定晶粒周邊；其中所述頂部刻痕位於所述晶粒周邊外部。
本發明還提供一種方法，其包括：將第一半導體晶粒安裝在引線框架的具有頂部刻痕的第一側上；及將夾具從所述頂部刻痕耦合到所述第一半導體晶粒的晶粒頂部側；其中：所述引線框架包括：引線框架頂部側，其包括：引線框架頂端，引線框架頂部平面沿著其延伸；引線框架 底部側，其包括：引線框架底端，所述引線框架底部平面沿著其延伸；及頂部刻痕，其包括：頂部刻痕基底，其位於所述引線框架頂部平面與所述引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；所述第一半導體晶粒包括：晶粒頂部側；晶粒底部側，其安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間，且界定晶粒周邊；所述夾具包括插入到所述頂部刻痕中的夾具邊緣；且所述夾具從所述頂部刻痕突出越過所述引線框架頂部側到所述晶粒頂部側。
100‧‧‧電子組件
101‧‧‧囊封劑
105‧‧‧中心區
106‧‧‧周邊
110‧‧‧引線框架
111‧‧‧引線框架頂部側
112‧‧‧引線框架底部側
115‧‧‧焊盤
116‧‧‧引線
117‧‧‧引線
120‧‧‧頂部刻痕
121‧‧‧頂部刻痕側壁
122‧‧‧頂部刻痕側壁
125‧‧‧頂部刻痕基底
130‧‧‧頂部刻痕
131‧‧‧頂部刻痕側壁
135‧‧‧頂部刻痕基底
140‧‧‧夾具
141‧‧‧夾具尾
142‧‧‧夾具邊緣
145‧‧‧夾具頂
150‧‧‧夾具
151‧‧‧夾具尾
152‧‧‧夾具邊緣
155‧‧‧夾具頂
156‧‧‧夾具頂底部
161‧‧‧引線
171‧‧‧引線
172‧‧‧底部刻痕
181-184‧‧‧熔接結構
190‧‧‧半導體晶粒
191‧‧‧晶粒側
192‧‧‧晶粒側
193‧‧‧晶粒側壁
196‧‧‧晶粒端子
197‧‧‧晶粒端子
198‧‧‧晶粒端子
217‧‧‧刻痕長度
500‧‧‧電子組件
540‧‧‧夾具
541‧‧‧夾具尾
545‧‧‧夾具頂
582‧‧‧熔接結構
590‧‧‧晶粒
600‧‧‧電子組件
610‧‧‧引線框架
615‧‧‧晶粒焊盤
616‧‧‧引線
700‧‧‧方法流程圖
710-740‧‧‧步驟框
1111‧‧‧引線框架頂部平面
1122‧‧‧引線框架底部平面
1161‧‧‧引線支腳
1171‧‧‧引線支腳
2172‧‧‧引線支腳
2211‧‧‧側壁區段
2212‧‧‧側壁區段
2213‧‧‧側壁區段
3172‧‧‧引線支腳
3311‧‧‧側壁區段
3312‧‧‧側壁區段
3351‧‧‧基底區段
3352‧‧‧基底區段
圖1呈現根據本發明的實施例的電子組件的剖面側視圖。
圖2呈現電子組件的引線框架的引線的部分的透視圖，展示該處的頂部刻痕的部分。
圖3呈現電子組件的引線框架的另一引線的部分的透視圖，展示該處的頂部刻痕的部分。
圖4說明圖2的透視圖，具有耦合到頂部刻痕的夾具。
圖5說明根據本發明的實施例的電子組件的剖面側視圖。
圖6說明根據本發明的實施例的電子組件的剖面側視圖。
圖7呈現用於提供電子組件的方法的流程圖。
以下論述通過提供其實例來呈現本發明的各種方面。此些實例並非限制性，且因此本發明的各種方面的範圍應未必受所提供實例的任 何特定特性限制。在以下論述中，短語“舉例來說”、“例如”及“示範性”並非限制性且通常與“通過實例且非限制的方式”、“例如且非限制性”及其類似者同義。
為說明的簡潔及清楚起見，繪圖說明構造的一般方式，且眾所周知的特徵及技術的描述及細節可被忽略以避免不必要模糊本發明。另外，繪圖中的元件未必按比例繪製。例如，圖中的元件中的一些元件的尺寸可相對於其它元件經放大以說明提高對本發明的實施例的理解。不同圖中的相同參考編號表示相同元件。
如本文中所使用，術語“及/或”和“或”包含相關聯所列物項中的一或多者的任何及全部組合。如本文中所使用，除非上下文另有明確指示，否則單數形式意欲包含複數形式。另外，術語“在…時”意指某動作至少在起始動作的持續時間的某一部分內。
將進一步理解，術語“包括”及/或“包含”在本說明書中使用時規定所述特徵、數值、步驟、操作、元件及/或組件的存在，但不排除存在或添加一或多個其它特徵、數值、步驟、操作、元件、元件及/或其群組。
應理解，術語“第一”、“第二”等可在本文中用於描述各種元件，且這些組件應不受這些術語限制。這些術語僅用於將一個元件與另一元件區分開。因此，例如，下文所論述第一部件、第一元件、第一區、第一層及/或第一區段可被稱作第二部件、第二元件、第二區、第二層及/或第二區段，而不脫離本發明的教示內容。
類似地，各種空間術語(例如，“上部”、“下部”、“側”、 “頂部”、“底部”、“在…上方”、“在…下方”及其類似者)可用於以相對方式將一個元件與另一元件區分開。然而，應理解，元件可以不同方式定向，例如，裝置可轉向側面使得其“頂”表面水準定向且其“側”表面垂直定向，而不脫離本發明的教示內容。
術語“耦合”及其類似者應廣泛地理解且指以電方式、機械方式或其它方式連接兩個或多於兩個元件或信號。耦合(無論機械、電或其它方式)可達任何時間長度，例如，永久或半永久或僅達片刻。此外，應理解，當組件A被稱作為“連接到”或“耦合到”組件B，組件A可直接連接到元件B或間接地連接到元件B(例如，中間元件C(及/或其它元件)可定位在元件A與組件B之間)。類似地，除非另有規定，如本文中所使用，詞語“在…上方”或“在…上”包含定向、佈置或關係，其中規定元件可直接或間接物理接觸。
對“一個實施例”或“實施例”的提及意指結合所述實施例描述的特定特徵、結構或特性包含於本發明的至少一個實施例中。因此，在本說明書通篇中的各處出現的短語“在一個實施例中”或“在實施例中”未必全部指代同一實施例，但在一些狀況下可能。
詞語“約”、“大約”或“基本上”的使用意指預期組件的值接近於所述值或位置。然而，如此項技術中眾所周知，始終存在阻止值或位置如確切規定的較小偏差。
此外，在一或多個實施例中，特定特徵、結構或特性可以任何適合方式組合，如所屬領域的技術人員將明瞭。
進一步理解，下文中適當地說明及描述的實施例可具有實施 例及/或可在不存在本文中未明確揭示的任何元件的情況下實踐。
在一個實施例中，一種電子組件可包括引線框架及第一半導體晶粒。所述引線框架可包括引線框架頂部側、與所述引線框架頂部側相對的引線框架底部側，及在所述引線框架頂部側處的頂部刻痕。所述頂部刻痕可包括頂部刻痕基底，其位於所述引線框架頂部側與所述引線框架底部側之間，且界定所述頂部刻痕的刻痕長度；且還可包括頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底。所述第一半導體晶粒可包括晶粒頂部側、與所述晶粒頂部側相對且安裝到所述引線框架頂部側上的晶粒底部側，及位於所述晶粒頂部側與所述晶粒底部側之間且界定晶粒周邊的晶粒側壁。所述頂部刻痕可位於所述晶粒周邊的外側。
在一個實施例中，電子組件可包括引線框架、引線框架頂部平面、與引線框架頂部平面平行的引線框架底部平面。引線框架可包括引線框架頂部側，其包括所述引線框架頂部平面沿著其延伸的引線框架頂端；引線框架底部側，其包括所述引線框架底部平面沿著其延伸的引線框架底端。所述引線框架還可包括頂部刻痕，所述頂部刻痕包括：頂部刻痕基底，其位於所述引線框架頂部平面與引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度的；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底。所述第一半導體晶粒可包括晶粒頂部側、安裝到所述引線框架頂部側上的晶粒底部側，及晶粒側壁，所述晶粒側壁位於所述晶粒頂部側與所述晶粒底部側之間且界定晶粒周邊。所述頂部刻痕可位於所述晶粒周邊的外側。
在一個實施方案中，用於提供電子組件的方法可包括：將第一半導體晶粒安裝在引線框架的具有頂部刻痕的第一側上；將夾具從頂部刻痕耦合到所述第一半導體晶粒的晶粒頂部側。引線框架可包括引線框架頂部側，其包括引線框架頂部平面沿著其延伸的引線框架頂端；及引線框架底部側，其包括所述引線框架底部平面沿著其延伸的引線框架底端。所述引線框架還可包括頂部刻痕，所述頂部刻痕包括：頂部刻痕基底，其位於所述引線框架頂部平面與引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底。所述第一半導體晶粒可包括晶粒頂部側、安裝到所述引線框架頂部側上的晶粒底部側，及晶粒側壁，所述晶粒側壁位於所述晶粒頂部側與所述晶粒底部側之間且界定晶粒周邊。所述夾具可包括插入到所述頂部刻痕中的夾具邊緣。所述夾具可從所述頂部刻痕突出越過所述引線框架頂部側到所述晶粒頂部側。
本文中進一步解釋其它實例及實施例。此些實例及實施例可在圖中、申請專利範圍第書中及/或本文發明中找到。
轉向圖式，圖1表示根據本發明的一個實施例的電子組件100的剖面側視圖。圖2表示電子組件100的引線框架110的引線117的部分的透視圖，展示該處的頂部刻痕120的部分。圖3呈現電子組件100的引線框架110的引線116的部分的透視圖，展示該處的頂部刻痕130的部分。圖4說明具有耦合到頂部刻痕120的夾具150的圖2的透視圖。在一些實施方案中，電子組件100可包括半導體基於引線框架的封裝，其在一些實施方案中經配置(例如)用於高功率及/或高電流要求。
如在圖1到2中可見，引線框架110包括引線框架頂部側111及與引線框架頂部側111相對的引線框架底部側112。引線框架頂部側111包含引線框架110的頂端，其中此頂端可包括引線框架110的最頂點或頂表面。引線框架底部側112包含引線框架110的底端，其中此底端可包括引線框架110的最低點或最低表面。引線框架110界定引線框架頂部平面1111，其沿著引線框架110的頂端延伸；且引線框架底部平面1122，其可平行於引線框架頂部平面1111且沿著引線框架110的底端延伸。
在本實施例中，引線框架110還可包括焊盤115，及引線116到117。引線116到117從中心區105延伸到電子組件100的周邊106。焊盤115在本說明中展示為位於中心區105處，但在相同或其它實例中，所述焊盤可為或可包括引線，所述引線(例如)沿與圖1中所呈現的橫截面平面非平面及/或正交的方向延伸到周邊106。如在圖2到4中可見，引線116到117可各自包括多個引線支腳，所述引線支腳通過其間的橋接件耦合在一起。引線框架110進一步包括頂部刻痕120，所述頂部刻痕從引線框架頂部側111延伸到引線117中。
半導體晶粒190位於引線框架110上方，其中晶粒側191使用熔接結構183安裝到引線框架頂部側111上且在焊盤115上方。因此，晶粒190及頂部刻痕120兩者位於同一引線框架頂部側111上。晶粒側192背對引線框架110，且晶粒側壁193在晶粒側192與晶粒側191之間延伸，從而界定半導體晶粒190的晶粒周邊。引線框架110可用於將晶粒190介接到電子組件100的外側，且可包括導電材料，例如銅及/或其合金。
頂部刻痕120位於半導體晶粒190的晶粒周邊的外側，因此 可用於接納導電夾具150。在本實施例中，頂部刻痕120可在引線框架頂部側111處接達且包括頂部刻痕基底125、頂部刻痕側壁121及頂部刻痕側壁122。頂部刻痕基底125位於引線框架頂部側111與引線框架底部側112之間，因此相對於引線框架頂部側111凹陷。頂部刻痕基底125還位於引線框架頂部平面1111與引線框架底部平面1122之間。
頂部刻痕側壁121沿著刻痕長度217從引線框架頂部側111延伸到頂部刻痕基底125。頂部刻痕側壁122類似於頂部刻痕側壁121，但跨越頂部刻痕基底125與其相對，使得頂部刻痕側壁122比頂部刻痕側壁121更接近於晶粒190。然而，在一些實例中，頂部刻痕側壁122可為任選的，使得頂部刻痕基底125可朝向晶粒190從頂部刻痕側壁121延伸到引線117的邊緣，類似於引線116的頂部刻痕130的配置。
在一些實施方案中，頂部刻痕120可通過蝕刻引線框架110來形成，其中此蝕刻可(例如)經由化學蝕刻或經由鐳射蝕刻來實施以界定頂部刻痕側壁121、頂部刻痕側壁122及/或頂部刻痕基底125的蝕刻表面。在一些實施方案中，此化學蝕刻可包括蝕刻劑，例如，氯化鐵、磷酸銨及/或CuCiAHAS(氯化銅-鹽酸水溶液)。在一些實施方案中，此鐳射蝕刻可包括鐳射蝕刻，例如，運用LDI(鐳射定義成像)的LEEP過程(改進型鐳射蝕刻過程)。頂部刻痕120還可(例如)通過衝壓或壓模、燒蝕、鋸切、水沖，及/或研磨引線框架110來機械形成。在一些實施例中，類似於頂部刻痕120的頂部刻痕也可通過彎曲引線框架110來形成。儘管圖往往將頂部刻痕側壁121、頂部刻痕側壁122及頂部刻痕基底125的表面及結展示為基本上平面且正交，但此些表面及結可包括非平面度及/或可視為弧形，例如， U形狀或V形狀，此取決於縮放水準及/或所使用的化學或機械形成過程。
如圖1及2所見，引線117包括引線支腳1171，其中其內端界定頂部刻痕側壁121的側壁區段2211。引線117還包括引線支腳2172，其中其內端界定頂部刻痕側壁121的側壁區段2212。在本實例中，頂部刻痕側壁121貫穿刻痕長度217為連續的，包括在引線邊緣1171及2172的內端之間延伸(從側壁區段2211到側壁區段2212)的側壁區段2213。在本實例中，頂部刻痕基底125貫穿刻痕長度217也為連續的。然而，可存在其中頂部刻痕側壁121可為不連續(沿著刻痕長度217包括間斷段，例如通過省略側壁區段2213)的實施例。也可存在其中頂部刻痕基底125可為不連續(沿著刻痕長度217包括間斷端)的實施例。
如圖1及3中所見，在本實施例中，引線116可類似於引線117，且包括頂部刻痕130。頂部刻痕130經配置以如本文中針對夾具150描述為經接納在頂部刻痕120(圖1、2、4)中一樣接納夾具140(圖1)的夾具尾141的夾具邊緣142。頂部刻痕130包括頂部刻痕基底135及頂部刻痕側壁131，其可分別類似於頂部刻痕120的頂部刻痕基底125及頂部刻痕側壁121(圖1到2)。引線116包括引線支腳1161，其中其內端界定頂部刻痕側壁131的側壁區段3311。引線116還包括引線支腳3172，其中其內端界定頂部刻痕側壁131的側壁區段3312。在本實例中，頂部刻痕側壁131在引線支腳1161及3172的內端之間為不連續的，其中側壁區段3311及3312可為共面的但彼此通過間隙間隔或分離開。在本實例中，頂部刻痕基底135在引線支腳1161及3172的內端之間也為不連續的，其中基底區段3351及3352可為共面但彼此通過間隙間隔或分離開。然而，可存在其中頂部刻痕 側壁131可為連續，及/或其中頂部刻痕基底135可為連續的實施例。
圖1到4展示引線116及117，其包括在引線框架底部側112處的相應底部刻痕，例如，引線117的底部刻痕171及172，及引線116的底部刻痕161。例如，底部刻痕171包括底部刻痕基底，其位於引線框架頂部側111與引線框架底部側112之間，且借此相對於引線框架底部側112凹陷。底部刻痕171還包括底部刻痕側壁，其從引線框架底部側112延伸到其底部刻痕基底，且鄰近其底部刻痕基底。底部刻痕172及161還包括類似相應底部刻痕基底及底部刻痕側壁。在一些實例中，底部刻痕171、172及/或161的底部刻痕基底及/或底部刻痕側壁可除其在引線框架底部側112處的位置外可與本文中所描述的頂部刻痕側壁及頂部刻痕基底(例如，頂部刻痕120及130的那些)類似的。底部刻痕171、172及161可包括或用作用於加強囊封劑101與引線框架110之間的粘合或卡扣的鎖定特徵。在一些實施方案中，底部刻痕171、172、及/或161的深度可比頂部刻痕120或130中的任一者的深度大。
如圖1及4中所見，夾具150包括夾具尾151，所述夾具尾具有插入到頂部刻痕120中的夾具邊緣152，其中夾具尾151的其餘部分從頂部刻痕120突出越過引線框架頂部側111。夾具邊緣152通過頂部刻痕120中的熔接結構181熔接到引線框架110，其中此熔接結構181可在夾具邊緣152的底部與頂部刻痕基底125之間延伸。在一些實例中，熔接結構181可完全填充頂部刻痕120。在同一或其它實例中，熔接結構181可能過充滿頂部刻痕120且可在引線框架頂部側111的至少一部分上延伸。在一些實例中，熔接結構181可為焊膏、環氧材料或導電燒結材料。在相同或其它實 例中，熔接結構181可經由鐳射或超聲波附接來形成。
夾具150還包括夾具頂155，所述夾具頂以其間的角度或彎曲耦合到夾具尾150，其中夾具150可彎曲、衝壓或以其它方式由導電材料形成，所述導電材料在一些實施方案中可與關於引線框架110的材料所描述的材料中的一或多者相似或相同。在本實施例中，夾具頂155的夾具頂底部156經由熔接結構182耦合到晶粒190的晶粒側192，所述熔接結構位於所述夾具頂底部與所述晶粒側之間。可存在其中熔接結構182及/或183可包括類似於上文關於熔接結構181所描述的材料中的一或多者的材料的實例。
頂部刻痕120可考慮到夾具尾151的長度的變化以防止此些變化影響夾具150在晶粒190及/或在引線框架110上方對準或耦合。例如，在一些實施方案中，當熔接結構181及182經回焊時，如果夾具尾151由於(例如)製造變化而比需要的長，那麼夾具邊緣152的底部可視需要凹陷低於引線框架頂部側111的高度且凹陷到頂部刻痕120中，借此防止夾具邊緣152到達夾具150的底部且使所述夾具傾斜。因此，頂部刻痕基底125相對於引線框架頂部側111的深度可防止夾具邊緣152的底部直接接觸頂部刻痕基底125，借此緩和夾具在夾具邊緣152周圍傾斜，其原本可能造成非平面對準及/或夾具頂底部156與晶粒側192之間的減少耦合，及/或熔接結構182的不一致的厚度。頂部刻痕基底125的深度及/或頂部刻痕側壁121的高度的範圍可介於從大約至少10微米到引線框架110的厚度的一半，借此適應夾具尾長度的製造或容限變化。例如，如果引線框架110為大約200微米厚，那麼頂部刻痕120可高達100微米深度。
在一些實施例中，晶粒190可包括電力裝置，例如，場效電晶體(FET)晶粒，其可具有源極端子、閘極端子及汲極端子。晶粒190包括在晶粒側192處的晶粒端子196，其可通過熔接結構182耦合到夾具頂底部156。晶粒190還包括在晶粒側191的晶粒端子197，其可通過熔接結構183耦合到引線框架110。晶粒190進一步包括在晶粒側192處的晶粒端子198，其經展示通過連接器耦合到引線框架110的引線116，所述連接器在本實施例中包括耦合到頂部刻痕130的夾具140，但在其它實施例中可包括其它連接器類型，例如線接合線或線帶。在一些實施方案中，晶粒端子196可包括晶粒190的源極端子，而晶粒端子197可包括晶粒190的汲極端子。然而，可存在其中端子196可包括晶粒190的汲極端子而晶粒端子197可包括晶粒190的源極端子的實施方案。晶粒端子198可包括晶粒190的閘極端子。
如圖1及4的實施例中所見，夾具150的夾具邊緣152可在插入到頂部刻痕120中時直接接觸頂部刻痕側壁121。例如，夾具邊緣152可沿著及/或貫穿夾具邊緣152的基本上整個長度而抵靠頂部刻痕側壁121。夾具邊緣152的此定位准許頂部刻痕側壁121充當用於輔助使夾具150相對於引線框架110及/或晶粒190對齊的支架。另外，夾具邊緣152在頂部刻痕120內及/或抵靠頂部刻痕側壁121的此定位可限制夾具150在(例如)熔接結構181的回焊期間側傾或拔除。
圖5說明根據本發明的一個實施例的電子組件500的剖面側視圖。電子組件500類似於上文所描述的電子組件100，使得對電子組件100的相應描述適用於電子組件500，且還包括堆疊於晶粒190上方的晶粒590。 電子組件500包含具有刻痕120及130的引線框架110，及上文關於電子組件100所描述的夾具150，而且還包括安裝在夾具150的夾具頂155上方的晶粒590的底部側，及在晶粒590上方的夾具540。夾具540類似於夾具140，但其夾具尾541較長以適應晶粒190上方的晶粒590的堆疊高度，且其夾具頂545的底部改為通過熔接結構582耦合到晶粒590的頂部側。
圖6表示根據本發明的一個實施例的電子組件600的剖面側視圖。電子組件600類似於上文所論述的電子組件100，使得對電子組件100的對應描述適用於電子組件600。引線框架610類似於引線框架110(圖1到5)，但經配置以支援晶粒190以覆晶或翻轉晶粒形式安裝在其上，其中晶粒側192及對應的晶粒端子196及198耦合到引線框架610的頂部側。晶粒端子198在本實例中耦合到引線616，其中引線616可類似於引線116或117(圖1到5)，例如，通過延伸到電子組件600的周邊，但不需要包括頂部刻痕，如頂部刻痕120或130(圖1到5)。晶粒端子196在本實例中耦合到晶粒焊盤615，所述晶粒焊盤可類似於晶粒焊盤115(圖1到5)，及/或可為類似於延伸到電子組件600的周邊的引線616的引線。電子組件600可因此包括引線上晶片配置。本實例還展示將晶粒190耦合到引線117的夾具150，其中經由頂部刻痕120將夾具尾151錨定於該處。由於晶粒190在圖6中相對於圖1到5的實施例翻轉，因此夾具頂155改為耦合到晶粒側191及其端子197。
在圖6的本實例中，晶粒端子196及198分別經由熔接結構184及182耦合到晶粒焊盤615及引線616。在一些實例中，熔接結構184及182可包括焊料，及/或可經由焊料板模圖案化定義。可存在其中熔接結 構184及/或182可包括耦合到晶粒焊盤615或引線616的相應覆晶凸塊的實例，其中此些覆晶凸塊可包括焊料凸塊及/或金屬柱。
儘管電子組件600在圖6中經展示成非堆疊配置，但可存在其中電子組件600可包括類似於圖5的配置的堆疊晶粒配置，其中晶粒590將安裝在夾具頂155上方，其中引線616將包括頂部刻痕(如同頂部刻痕120或130(圖1到5))及/或其中夾具540將把晶粒590耦合到引線616的此頂部刻痕的實施例。
圖7呈現用於提供電子組件的方法700的流程圖。在一些實施例中，方法700的電子組件可類似於如本文中圖1到6所展示的電子組件100、500及/或600中的一或多者，或類似於其變化或組合。
方法700的框710包括將第一半導體晶粒安裝在包括第一頂部刻痕的引線框架的第一側上。例如，第一半導體晶粒可類似於如安裝在引線框架110(圖1、5)上的晶粒190。作為另一實例，第一半導體晶粒可類似於如安裝在引線框架610(圖6)上的晶粒190，或另外以(例如)引線上晶片配置安裝的覆晶，使得其多個端子接觸引線框架的第一側。
方框710的引線框架可類似於引線框架110(圖1到5)、引線框架510(圖5)、引線框架610(圖6)，或其變化形式。引線框架可包括具有引線框架頂部平面沿著其延伸的頂端的引線框架頂部側，例如上文關於引線框架頂部側111(圖1到5)或引線框架610的頂部側(圖6)及對應引線框架頂端1111(圖1到6)描述為實例。類似地，引線框架可包括具有引線框架底部平面沿著其延伸的底端的引線框架底部側，例如上文關於引線框架底部側112(圖1到5)或引線框架610(圖6)的底部頂部側及對 應的引線框架底端1122(圖1到6)描述為實例。
方框710的引線框架還可在其頂部側具有第一頂部刻痕，其中此第一頂部刻痕可包括頂部刻痕基底及頂部刻痕第一側壁。頂部刻痕基底可位於引線框架頂部平面與引線框架底部平面之間，且可界定第一頂部刻痕的刻痕長度。頂部刻痕第一側壁可沿著頂部刻痕長度從引線框架頂部側及/或引線框架頂部平面延伸到頂部刻痕基底。第一頂部刻痕還可任選地包括頂部刻痕第二側壁，所述頂部刻痕第二側壁還可沿著頂部刻痕長度從引線框架頂部側及/或引線框架頂部平面延伸到頂部刻痕基底，其中此頂部刻痕第二側壁跨越頂部刻痕基底面向頂部刻痕第一側壁。取決於實施例，頂部刻痕基底、頂部刻痕第一側壁及/或頂部刻痕第二側壁可為連續或不連續的。在一些實施方案中，第一頂部刻痕可類似於頂部刻痕120或130，及其相應頂部刻痕基底125或135，及/或其相應側壁121、122或131(圖1到6)。
方法700的方框720包括：將第一夾具從第一頂部刻痕耦合第一半導體晶粒的晶粒頂部側。第一夾具可包括夾具尾，其具有耦合到晶粒頂部側的夾具頂，及夾具邊緣，其耦合到引線框架的第一頂部刻痕，其中第一夾具的夾具尾可從第一頂部刻痕突出且耦合到夾具頂。在一些實例中，第一夾具可類似於本文中所描述的夾具140(圖1)、夾具150(圖1、4到6)，及/或夾具540(圖5)。例如，第一夾具可類似於夾具150(圖1、4到6)，具有耦合到頂部刻痕120的夾具尾151的夾具邊緣152，且具有耦合到晶粒190的晶粒側192的夾具頂155。在相同或其它實例中，第一夾具可類似於夾具140(圖1)，具有耦合到頂部刻痕130的夾具尾141的夾具邊緣 142，且具有耦合到晶粒190的晶粒側192的夾具頂145。
方法700的方塊730包括：將第二半導體晶粒安裝在第一半導體晶粒上面的第一夾具上方。在一些實例中，第二半導體晶粒可類似於安裝在夾具150的夾具頂155上方且在晶粒190上面的晶粒590(圖5)。
方法700的方框740包括：將第二夾具從引線框架的第二頂部刻痕耦合到第二半導體晶粒的頂部側。在一些實例中，第二夾具可類似於夾具540，所述夾具具有耦合到晶粒590的頂部側的夾具頂545及耦合到頂部刻痕130的夾具邊緣142(圖5)。此第二夾具可具有夾具尾，所述夾具尾比第一夾具的夾具尾長以適應第一及第二半導體晶粒的堆疊配置的高度。
如本文中所述，本發明的範圍並不限於所論述的特定實例方法方框(或相關聯結構)。例如，在一些實施方案中，可將各種方框(或其部分)從實例方法700移除或添加到所述實例方法，可重新排序各種方框(或其部分)，可修改各種方框(或其部分)等，例如，方框730及/或740可為任選的。
雖然關於特定優選實施例及實例實施例描述本發明的標的物，但前述圖式及其描述僅描繪標的物的說明性實施例，且因此並不應認為對其範圍的限制。顯而易見，所屬領域的技術人員將明瞭許多替代方案及變化，例如，本文中所描述的頂部刻痕的特定實施方案可變化，其中(例如)頂部刻痕120到130可彼此互換。作為另一實例，本文中所描述的結構及元件可與其它襯底類型一起使用，包含在其頂部側處具有一或多個頂部刻痕及耦合在此(些)頂部刻痕與相應半導體晶粒之間耦合的對應夾具的 層壓板或其它襯底。儘管本說明主要將QFN/MLF或QFP引線框架襯底用於說明目的，但應理解，在提供相同或類似益處的同時將這些概念應用於其它引線框架襯底(例如，可佈線-MLF(RtMLF)或模制互連系統(MIS))以及層壓襯底設計是可能的。在層壓設計的狀況下，仍可利用引線框架來實現導電引線接頭形成且互連到安裝在層壓襯底上的裝置。
如在下文中之申請專利範圍所反映，進步性方面可在於少於前所揭示之單個實施例的所有特徵。因此，下文中所表達的申請專利範圍特此明確併入圖式的此詳細說明中，其中每一申請專利範圍獨自作為本發明的單獨實施例。此外，如所屬領域的技術人員將理解，雖然本文中所描述的一些實施例包含一些但非包含在其它實施例中的其它特徵，但不同實施例的特徵的組合意欲在本發明的範圍內且意欲形成不同實施例。
100‧‧‧電子組件
101‧‧‧囊封劑
105‧‧‧中心區
106‧‧‧周邊
110‧‧‧引線框架
111‧‧‧引線框架頂部側
112‧‧‧引線框架底部側
115‧‧‧焊盤
116‧‧‧引線
117‧‧‧引線
120‧‧‧頂部刻痕
121‧‧‧頂部刻痕側壁
122‧‧‧頂部刻痕側壁
125‧‧‧頂部刻痕基底
130‧‧‧頂部刻痕
131‧‧‧頂部刻痕側壁
135‧‧‧頂部刻痕基底
140‧‧‧夾具
141‧‧‧夾具尾
142‧‧‧夾具邊緣
145‧‧‧夾具頂
150‧‧‧夾具
151‧‧‧夾具尾
152‧‧‧夾具邊緣
155‧‧‧夾具頂
156‧‧‧夾具頂底部
161‧‧‧引線
171‧‧‧引線
172‧‧‧底部刻痕
181-184‧‧‧熔接結構
190‧‧‧半導體晶粒
191‧‧‧晶粒側
192‧‧‧晶粒側
193‧‧‧晶粒側壁
196‧‧‧晶粒端子
197‧‧‧晶粒端子
198‧‧‧晶粒端子
1111‧‧‧引線框架頂部平面
1122‧‧‧引線框架底部平面
1161‧‧‧引線支腳
1171‧‧‧引線支腳

Claims (22)

  1. 一種電子組件，其包括：引線框架頂部平面；引線框架底部平面，其與所述引線框架頂部平面平行；引線框架，其包括：引線框架頂部側，其包括：引線框架頂端，所述引線框架頂部平面沿著所述引線框架頂端延伸；引線框架底部側，其包括：引線框架底端，所述引線框架底部平面沿著所述引線框架底端延伸；及頂部刻痕，其包括：頂部刻痕基底，其位於所述引線框架頂部平面與所述引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；第一半導體晶粒，其包括：晶粒頂部側；晶粒底部側，其安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間並且界定晶粒周邊；其中所述頂部刻痕位於所述晶粒周邊外部； 夾具，其包括：夾具尾，其具有插入到所述頂部刻痕中的夾具邊緣，使得所述夾具邊緣的底部在所述引線框架頂部側下方；及夾具頂，其耦合到所述夾具尾；其中：所述夾具頂附接到所述第一半導體晶粒；所述夾具尾從所述頂部刻痕突出越過所述引線框架頂部側；所述夾具邊緣的所述底部以一角度鄰接所述頂部刻痕第一側壁；且所述頂部刻痕基底相對於所述引線框架頂部側的深度防止所述夾具邊緣的所述底部直接接觸所述頂部刻痕基底。
  2. 根據申請專利範圍第1項所述的電子組件，其進一步包括：熔接結構，其延伸於所述夾具邊緣的所述底部和所述頂部刻痕基底之間，其中所述熔接結構將所述夾具邊緣熔接於所述頂部刻痕中。
  3. 根據申請專利範圍第1項所述的電子組件，其中：所述頂部刻痕基底與所述頂部刻痕第一側壁包括所述引線框架頂部側的相應部分；並且所述夾具邊緣的所述底部完全地在所述引線框架頂部側下方。
  4. 根據申請專利範圍第2項所述的電子組件，其中：所述頂部刻痕包括：刻痕第二側壁，其跨越所述頂部刻痕基底與所述刻痕第一側壁相對；所述刻痕第二側壁比所述頂部刻痕第一側壁更接近所述第一半導 體晶粒；並且所述熔接結構延伸以物理性接觸所述刻痕第二側壁。
  5. 一種電子組件，其包括：引線框架，其包括：引線框架頂部側；引線框架底部側，其與所述引線框架頂部側相對；及頂部刻痕，其位於所述引線框架頂部側且包括：頂部刻痕基底，其位於所述引線框架頂部側與所述引線框架底部側之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；第一半導體晶粒，其包括：晶粒頂部側；晶粒底部側，其與所述晶粒頂部側相對且安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間，且界定晶粒周邊；其中所述頂部刻痕位於所述晶粒周邊外部；及夾具，其包括：夾具尾，其具有插入到所述頂部刻痕中的夾具邊緣，使得所述夾具邊緣的底部在所述引線框架頂部側下方；其中： 所述夾具尾從所述頂部刻痕突出越過所述引線框架頂部側；所述夾具邊緣的所述底部以一角度鄰接所述頂部刻痕第一側壁；且所述頂部刻痕基底相對於所述引線框架頂部側的深度防止所述夾具邊緣的所述底部直接接觸所述頂部刻痕基底。
  6. 根據申請專利範圍第5項所述的電子組件，其中所述頂部刻痕基底是不連續的。
  7. 根據申請專利範圍第5項所述的電子組件，其中：所述夾具邊緣具有在所述半導體晶粒遠端的第一角以及在所述半導體晶粒近端的第二角；以及所述夾具邊緣沿著所述夾具邊緣的所述第一角直接接觸所述頂部刻痕第一側壁。
  8. 根據申請專利範圍第5項所述的電子組件，其中：所述夾具邊緣通過焊接材料熔接到所述刻痕，所述焊接材料在所述夾具邊緣的所述底部與所述頂部刻痕基底之間延伸。
  9. 根據申請專利範圍第5項所述的電子組件，其中：所述夾具包括耦合到所述夾具尾的夾具頂；且所述夾具頂的夾具頂底部耦合到所述晶粒頂部側。
  10. 根據申請專利範圍第9項所述的電子組件，其中：所述晶粒頂部側包括：閘極端子，其耦合到所述引線框架頂部側在所述引線框架的引線處；及 源極端子或汲極端子中的一者，其通過熔接結構耦合到所述夾具頂底部。
  11. 根據申請專利範圍第5項所述的電子組件，其進一步包括：第二半導體晶粒，其位於所述第一半導體晶粒上方；其中：所述夾具包括耦合到所述夾具尾的夾具頂；且所述夾具頂的夾具頂底部耦合到所述第二半導體晶粒的頂部側。
  12. 根據申請專利範圍第5項所述的電子組件，其中：所述頂部刻痕基底與所述頂部刻痕第一側壁由相應蝕刻表面界定。
  13. 根據申請專利範圍第5項所述的電子組件，其中：所述頂部刻痕基底及所述頂部刻痕第一側壁貫穿所述刻痕長度為連續的。
  14. 根據申請專利範圍第5項所述的電子組件，其中：所述晶粒底部側包括：閘極端子，其在所述引線框架的第一引線處耦合到所述引線框架頂部側；及源極端子或汲極端子中的一者，其通過熔接結構耦合到所述引線框架的第二引線或焊盤中的至少一者。
  15. 根據申請專利範圍第5項所述的電子組件，其中：所述頂部刻痕包括：刻痕第二側壁，其沿著所述刻痕長度從所述引線框架頂部側延 伸到所述頂部刻痕基底；其中所述刻痕第二側壁比所述頂部刻痕第一側壁更接近所述第一半導體晶粒。
  16. 根據申請專利範圍第5項所述的電子組件，其中：所述引線框架包括在所述引線框架底部側處具有底部刻痕的引線，所述底部刻痕包括：底部刻痕基底，其位於所述引線框架頂部側與所述引線框架底部側之間；及底部刻痕側壁，其鄰近所述底部刻痕基底從所述引線框架底部側延伸到所述底部刻痕基底；其中底部刻痕的深度比所述頂部刻痕的深度大。
  17. 一種電子組件，其包括：引線框架，其包括：引線框架頂部側；引線框架底部側，其與所述引線框架頂部側相對；及頂部刻痕，其位於所述引線框架頂部側且包括：頂部刻痕基底，其位於所述引線框架頂部側與所述引線框架底部側之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；及第一半導體晶粒，其包括：晶粒頂部側； 晶粒底部側，其與所述晶粒頂部側相對且安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間，且界定晶粒周邊，其中：所述引線框架包括引線，所述引線具有：第一引線支腳，其具有界定所述頂部刻痕第一側壁的第一區段的第一支腳內端；及第二引線支腳，其具有界定所述頂部刻痕第一側壁的第二區段的第二支腳內端；及所述頂部刻痕第一側壁在所述第一支腳內端與所述第二支腳內端之間為不連續的。
  18. 根據申請專利範圍第17項所述的電子組件，其中：所述頂部刻痕基底在所述第一支腳內端與所述第二支腳內端之間為不連續的。
  19. 根據申請專利範圍第17項所述的電子組件，其進一步包括：夾具，其包括夾具尾，其具有插入到所述頂部刻痕中的夾具邊緣，使得所述夾具邊緣的底部在所述引線框架頂部側下方，其中：所述夾具尾從所述頂部刻痕突出越過所述引線框架頂部側；所述夾具邊緣的所述底部以一角度鄰接所述頂部刻痕第一側壁；且所述頂部刻痕基底相對於所述引線框架頂部側的深度防止所述夾具邊緣的所述底部直接接觸所述頂部刻痕基底。
  20. 一種製造電子組件的方法，其包括：將第一半導體晶粒安裝在引線框架的具有頂部刻痕的第一側上；及將夾具從所述頂部刻痕耦合到所述第一半導體晶粒的晶粒頂部側；其中：所述引線框架包括：引線框架頂部側，其包括：引線框架頂端，引線框架頂部平面沿著所述引線框架頂端延伸；引線框架底部側，其包括：引線框架底端，所述引線框架底部平面沿著所述引線框架底端延伸；及頂部刻痕，其包括：頂部刻痕基底，其位於所述引線框架頂部平面與所述引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；及頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂部側延伸到所述頂部刻痕基底；所述第一半導體晶粒包括：晶粒頂部側；晶粒底部側，其安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間 並且界定晶粒周邊；所述夾具包括插入到所述頂部刻痕中的夾具邊緣，使得所述夾具邊緣的底部在所述引線框架頂部側下方；所述夾具邊緣的所述底部以一角度鄰接所述頂部刻痕第一側壁；且所述頂部刻痕基底相對於所述引線框架頂部側的深度防止所述夾具邊緣的所述底部直接接觸所述頂部刻痕基底；且所述夾具從所述頂部刻痕突出越過所述引線框架頂部側到所述晶粒頂部側。
  21. 一種電子組件，其包括：引線框架，其包括：引線框架頂部側，其包括：引線框架頂端，引線框架頂部平面沿著所述引線框架頂端延伸；引線框架底部側，其包括：引線框架底端，所述引線框架底部平面沿著所述引線框架底端延伸；及頂部刻痕，其包括：頂部刻痕基底，其位於所述引線框架頂部平面與所述引線框架底部平面之間，且界定所述頂部刻痕的刻痕長度；頂部刻痕第一側壁，其沿著所述刻痕長度從所述引線框架頂 部側延伸到所述頂部刻痕基底；頂部刻痕第二側壁，其跨越所述頂部刻痕基底與所述頂部刻痕第一側壁相對；及半導體晶粒，其安裝在所述引線框架頂部側上，其中所述半導體晶粒包括：晶粒頂部側；晶粒底部側，其安裝在所述引線框架頂部側上；及晶粒側壁，其位於所述晶粒頂部側與所述晶粒底部側之間並且界定晶粒周邊；夾具，其從所述頂部刻痕耦接到所述半導體晶粒的所述晶粒頂部側，其中：所述頂部刻痕被橫向地設置在所述晶粒周邊的外側；所述夾具包括插入到所述頂部刻痕中的夾具邊緣，所述夾具邊緣包括一表面；所述夾具從所述頂部刻痕突出越過所述引線框架頂部側到所述晶粒頂部側；及所述夾具邊緣插入到所述頂部刻痕中，使得所述夾具邊緣的整個表面在所述引線框架頂部側下方；熔接結構，其延伸於所述夾具邊緣的所述表面和所述頂部刻痕基底之間，其中：所述熔接結構將所述夾具邊緣熔接於所述頂部刻痕中；及所述熔接結構延伸以物理性接觸所述刻痕第二側壁；及 囊封劑，其設置以囊封所述半導體晶粒的至少部分、所述夾具的至少部份以及所述引線框架頂部側的至少部分。
  22. 根據申請專利範圍第21項所述的電子組件，其中：所述夾具邊緣的所述表面以一角度鄰接所述頂部刻痕第一側壁；且所述頂部刻痕基底相對於所述引線框架頂部側的深度防止所述夾具邊緣的所述表面直接接觸所述頂部刻痕基底。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102222146B1 (ko) * 2018-04-10 2021-03-05 제엠제코(주) 저비용 전도성 금속 구조체를 이용한 반도체 패키지
US11189550B2 (en) 2018-04-10 2021-11-30 Jmj Korea Co., Ltd. Low-cost semiconductor package using conductive metal structure
US10593640B2 (en) * 2018-04-18 2020-03-17 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
JP6437701B1 (ja) * 2018-05-29 2018-12-12 新電元工業株式会社 半導体モジュール
CN111261596A (zh) * 2018-12-03 2020-06-09 杰米捷韩国株式会社 利用多个夹件结构的半导体封装及其制造方法
DE102019112979A1 (de) * 2019-05-16 2020-11-19 Infineon Technologies Ag Clip mit Verriegelungsausnehmung
US11069600B2 (en) * 2019-05-24 2021-07-20 Infineon Technologies Ag Semiconductor package with space efficient lead and die pad design
EP3905324A1 (en) * 2020-05-01 2021-11-03 Nexperia B.V. A semiconductor device and a method of manufacture
US11482504B2 (en) * 2020-09-16 2022-10-25 Micron Technology, Inc. Edge-notched substrate packaging and associated systems and methods
JP2022146340A (ja) * 2021-03-22 2022-10-05 株式会社東芝 半導体装置
US20230170322A1 (en) * 2021-11-29 2023-06-01 Texas Instruments Incorporated Gang clip with mount compound arrester

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201212193A (en) * 2010-09-07 2012-03-16 Alpha & Omega Semiconductor A method of package with clip bonding
US20120104580A1 (en) * 2010-10-29 2012-05-03 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
TW201403762A (zh) * 2012-07-09 2014-01-16 Alpha & Omega Semiconductor 底部源極的功率裝置及製備方法
WO2014039658A1 (en) * 2012-09-05 2014-03-13 Texas Instruments Incorporated Vertically stacked power fets and synchronous buck converter having low on-resistance
TW201603201A (zh) * 2014-07-07 2016-01-16 萬國半導體股份有限公司 嵌入式封裝及封裝方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994412A (en) * 1990-02-09 1991-02-19 Motorola Inc. Self-centering electrode for power devices
US5277356A (en) * 1992-06-17 1994-01-11 Rohm Co., Ltd. Wire bonding method
TW374952B (en) * 1997-03-24 1999-11-21 Seiko Epson Corp Semiconductor device substrate, lead frame, semiconductor device and the manufacturing method, circuit substrate and the electronic machine
JPH113953A (ja) * 1997-06-10 1999-01-06 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP3285815B2 (ja) * 1998-03-12 2002-05-27 松下電器産業株式会社 リードフレーム，樹脂封止型半導体装置及びその製造方法
TW459357B (en) * 1999-08-20 2001-10-11 Rohm Co Ltd Electronic part and method of fabricating thereof
JP3429246B2 (ja) * 2000-03-21 2003-07-22 株式会社三井ハイテック リードフレームパターン及びこれを用いた半導体装置の製造方法
US6353257B1 (en) * 2000-05-19 2002-03-05 Siliconware Precision Industries Co., Ltd. Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention
US8236612B2 (en) * 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP4149439B2 (ja) * 2002-07-01 2008-09-10 株式会社ルネサステクノロジ 半導体装置
US7187063B2 (en) * 2002-07-29 2007-03-06 Yamaha Corporation Manufacturing method for magnetic sensor and lead frame therefor
JP2007509485A (ja) * 2003-08-14 2007-04-12 アドバンスド インターコネクト テクノロジーズ リミテッド 半導体デバイス・パッケージおよびその製造方法
US7005325B2 (en) * 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration
US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
US7394150B2 (en) * 2004-11-23 2008-07-01 Siliconix Incorporated Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
US7443015B2 (en) * 2005-05-05 2008-10-28 Stats Chippac Ltd. Integrated circuit package system with downset lead
TWI285415B (en) * 2005-08-01 2007-08-11 Advanced Semiconductor Eng Package structure having recession portion on the surface thereof and method of making the same
US7537965B2 (en) * 2006-06-21 2009-05-26 Delphi Technologies, Inc. Manufacturing method for a leadless multi-chip electronic module
JP2008071927A (ja) * 2006-09-14 2008-03-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7972906B2 (en) * 2008-03-07 2011-07-05 Fairchild Semiconductor Corporation Semiconductor die package including exposed connections
KR101014915B1 (ko) * 2009-02-23 2011-02-15 주식회사 케이이씨 반도체 패키지 및 그 제조 방법
US8586419B2 (en) * 2010-01-19 2013-11-19 Vishay-Siliconix Semiconductor packages including die and L-shaped lead and method of manufacture
US9184117B2 (en) * 2010-06-18 2015-11-10 Alpha And Omega Semiconductor Incorporated Stacked dual-chip packaging structure and preparation method thereof
US8519525B2 (en) * 2010-07-29 2013-08-27 Alpha & Omega Semiconductor, Inc. Semiconductor encapsulation and method thereof
US8513693B2 (en) * 2011-08-08 2013-08-20 Intellectual Discovery Co., Ltd. Miniature leadless surface mount lamp with dome and reflector cup
JP2013041950A (ja) * 2011-08-12 2013-02-28 Sharp Corp 発光装置
KR101905535B1 (ko) * 2011-11-16 2018-10-10 엘지이노텍 주식회사 발광 소자 패키지 및 이를 구비한 조명 장치
US8951847B2 (en) * 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
JP6078948B2 (ja) * 2012-01-20 2017-02-15 日亜化学工業株式会社 発光装置用パッケージ成形体及びそれを用いた発光装置
US8883567B2 (en) * 2012-03-27 2014-11-11 Texas Instruments Incorporated Process of making a stacked semiconductor package having a clip
JP5947107B2 (ja) * 2012-05-23 2016-07-06 ルネサスエレクトロニクス株式会社 半導体装置
US9013028B2 (en) * 2013-01-04 2015-04-21 Texas Instruments Incorporated Integrated circuit package and method of making
US8884415B2 (en) * 2013-02-28 2014-11-11 Nxp B.V. IC package with stainless steel leadframe
JP6484396B2 (ja) * 2013-06-28 2019-03-13 日亜化学工業株式会社 発光装置用パッケージ及びそれを用いた発光装置
DE102013224581A1 (de) * 2013-11-29 2015-06-03 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zu seiner Herstellung
JP6413412B2 (ja) * 2014-07-11 2018-10-31 日亜化学工業株式会社 半導体発光装置及びその製造方法
KR101631232B1 (ko) * 2014-12-15 2016-06-27 제엠제코(주) 클립을 이용한 적층 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201212193A (en) * 2010-09-07 2012-03-16 Alpha & Omega Semiconductor A method of package with clip bonding
US20120104580A1 (en) * 2010-10-29 2012-05-03 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
TW201403762A (zh) * 2012-07-09 2014-01-16 Alpha & Omega Semiconductor 底部源極的功率裝置及製備方法
WO2014039658A1 (en) * 2012-09-05 2014-03-13 Texas Instruments Incorporated Vertically stacked power fets and synchronous buck converter having low on-resistance
TW201603201A (zh) * 2014-07-07 2016-01-16 萬國半導體股份有限公司 嵌入式封裝及封裝方法

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US20180012829A1 (en) 2018-01-11
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