CN113192920A - 一种qfn封装的引脚结构 - Google Patents
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- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000005022 packaging material Substances 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 6
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- 229940125773 compound 10 Drugs 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- ZLVXBBHTMQJRSX-VMGNSXQWSA-N jdtic Chemical compound C1([C@]2(C)CCN(C[C@@H]2C)C[C@H](C(C)C)NC(=O)[C@@H]2NCC3=CC(O)=CC=C3C2)=CC=CC(O)=C1 ZLVXBBHTMQJRSX-VMGNSXQWSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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Abstract
本发明公开了一种QFN封装的引脚结构,包括框架基体和塑封料,框架基体上设有基岛固定区和蚀刻区,蚀刻区位于基岛固定区的外周;基岛固定区包括芯片和用于固定芯片的基岛,芯片连接在基岛的顶面;蚀刻区和基岛之间设有半蚀刻的基岛支架,蚀刻区包括多个引脚,每个引脚的边缘设有半蚀刻的边缘区域,边缘区域内设有半蚀刻的凹槽;芯片通过焊线和引脚相连接,蚀刻区、基岛固定区和焊线均塑封在塑封料内,且边缘区域及边缘区域内的凹槽内填充塑封料;本申请在边缘区域和边缘区域内的凹槽形成的阶梯槽,能够增加塑封料和引脚的附着面积及附着强度,提高了QFN封装的可靠性及芯片的稳定性。
Description
技术领域
本发明涉及芯片封装技术领域,具体涉及一种QFN封装的引脚结构。
背景技术
随着QFN应用的快速增长,高性能的QFN产品,必将会在国内外IC封装测试市场中赢得良好的收益,而QFN引线框架塑封体与引线框架之间的附着强度决定了QFN封装的可靠性,从而影响着芯片的稳定性。现有技术的QFN引线框架,在塑封时易出现引线框架和塑封料之间的剥离,降低了QFN封装的可靠性及芯片的稳定性。
发明内容
本发明的目的在于提供一种QFN封装的引脚结构,以解决现有技术中导致的塑封料和引线框架之间稳定性和可靠性差的问题。
为达到上述目的,本发明是采用下述技术方案实现的:
一种QFN封装的引脚结构,包括框架基体和塑封料,所述框架基体上设有基岛固定区和蚀刻区,所述蚀刻区位于所述基岛固定区的外周;
所述基岛固定区包括芯片和用于固定所述芯片的基岛,所述芯片连接在所述基岛的顶面;
所述蚀刻区和所述基岛之间设有半蚀刻的基岛支架,所述蚀刻区包括多个引脚,每个所述引脚的边缘设有半蚀刻的边缘区域,所述边缘区域内设有半蚀刻的凹槽;
所述芯片通过焊线和所述引脚相连接,所述蚀刻区、基岛固定区和焊线均塑封在所述塑封料内,且所述边缘区域及边缘区域内的凹槽内填充所述塑封料。
进一步地,所述基岛支架上内设有半蚀刻的凹槽,且所述述基岛支架及基岛支架内的凹槽内填充所述塑封料。
进一步地,所述基岛支架内的凹槽的形状和所述基岛支架的形状相适配,呈回字形。
进一步地,所述引脚的边缘区域位于所述引脚底面的两侧;所述边缘区域内的凹槽为矩形状。
进一步地,所述边缘区域的深度为所述引脚厚度的1/2-2/3;所述边缘区域内的凹槽的深度为所述引脚厚度的1/4。
进一步地,所述基岛支架的深度为所述框架基体厚度的1/2-2/3,所述基岛支架内的凹槽的深度为所述框架基体厚度的1/4。
进一步地,所述边缘区域内的凹槽的宽度为边缘区域宽度的1/3~2/3;
所述基岛支架内的凹槽的宽度为所述基岛支架宽度的1/3~2/3。
进一步地,所述塑封料是由粉状颗粒堆砌制成塑封料。
进一步地,所述框架基体的材质为铜。
进一步地,所述蚀刻区有四个,四个所述蚀刻区均布在所述基岛的四周。
根据上述技术方案,本发明的实施例至少具有以下效果:
1、本申请在每个引脚的边缘设计半蚀刻的边缘区域,并在边缘区域内设计了半蚀刻的凹槽,边缘区域和边缘区域内的凹槽形成的阶梯槽,能够增加塑封料和引脚的附着面积及附着强度,提高了QFN封装的可靠性及芯片的稳定性;
2、本申请在基岛和蚀刻区之间设置半蚀刻的基岛支架,并在基岛支架上设置半蚀刻的凹槽,基岛支架和基岛支架内的凹槽形成的阶梯槽增加了塑封料和引脚的附着面积及附着强度,配合边缘区域处形成的阶梯槽,共同提高了QFN封装的可靠性及芯片的稳定性。
附图说明
图1为本发明具体实施方式整体结构的俯视图;
图2为图1的局部主视剖视图。
其中:1、框架基体;2、基岛;3、基岛支架;4、引脚;5、芯片;6、边缘区域;7、蚀刻区;8、凹槽;9、焊线;10、塑封料。
具体实施方式
为使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解,下面结合具体实施方式,进一步阐述本发明。
需要说明的是,在本发明的描述中,术语“前”、“后”、“左”、“右”、“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图中所示的方位或位置关系,仅是为了便于描述本发明而不是要求本发明必须以特定的方位构造和操作,因此不能理解为对本发明的限制。本发明描述中使用的术语“前”、“后”、“左”、“右”、“上”、“下”指的是附图中的方向,术语“内”、“外”分别指的是朝向或远离特定部件几何中心的方向。
如图1和图2所示,一种QFN封装的引脚结构,包括框架基体1和塑封料10,框架基体1上设有基岛固定区和蚀刻区7,蚀刻区7位于基岛固定区的外周;基岛固定区包括芯片5和用于固定芯片5的基岛2,芯片5连接在基岛2的顶面;蚀刻区7和基岛2之间设有半蚀刻的基岛支架3,蚀刻区7包括多个引脚4,每个引脚4的边缘设有半蚀刻的边缘区域6,边缘区域6内设有半蚀刻的凹槽8;芯片5通过焊线9和引脚4相连接,蚀刻区7、基岛固定区和焊线9均塑封在塑封料10内,且边缘区域6及边缘区域6内的凹槽8内填充塑封料10。
本申请在每个引脚的边缘设计半蚀刻的边缘区域,并在边缘区域内设计了半蚀刻的凹槽,边缘区域和边缘区域内的凹槽形成的阶梯槽,能够增加塑封料和引脚的附着面积及附着强度,提高了QFN封装的可靠性及芯片的稳定性。
如图1所示,本申请的框架基体1采用铜材料制成。框架基体1上设置基岛固定区,基岛固定区包括基岛2,基岛2用于固定芯片5,进行QFN封装时,将芯片5放置到基岛2的顶面。基岛2位于框架基体1的中央处,蚀刻区7位于基岛2的四周。如框架基体1的形状为正方形状,基岛2和芯片5位于中心位置,蚀刻区7位于四边,四个边上的蚀刻区7之间不接触,蚀刻区7和基岛2之间也不接触,两者之间设置半蚀刻工艺进行蚀刻的基岛支架3,基岛支架3将蚀刻区7与蚀刻区之间隔开,并将蚀刻区与基岛2之间隔开。
每个蚀刻区7内设置多个位于同一列的引脚4,引脚4的边缘区域采用半蚀刻工艺进行蚀刻,即在引脚的边缘形成凹槽状的边缘区域6。在一些进一步地实施例中,边缘区域存在于引脚的两侧,此种设计便于边缘区域6的蚀刻。
在本申请中,在半蚀刻的边缘区域6内设有半蚀刻的凹槽8,半蚀刻的凹槽8和半蚀刻的边缘区域6形成阶梯槽。进行QFN封装时,形成的阶梯槽增加了和塑封料之间附着面积及附着强度,提高了QFN封装的可靠性及芯片的稳定性。
在本申请中,在半蚀刻的基岛支架3内也设置了半蚀刻的凹槽,半蚀刻的凹槽8和半蚀刻的基岛支架3形成阶梯槽。进行QFN封装时,形成的阶梯槽增加了和塑封料之间附着面积及附着强度,提高了QFN封装的可靠性及芯片的稳定性。
在一些实施例中,引脚4两侧的边缘区域6呈矩形状,其内形成的凹槽8的形状也为矩形状。
在一些实施例中,半蚀刻的基岛支架3的形状类似为回字形,其内形成的凹槽的形状也为回字形。
在一些实施例中,框架原有的半蚀刻深度介于框架总厚度的1/2~2/3之间,其增加的凹槽半蚀刻深度介于框架总厚度的1/4。便于半蚀刻区域内再次进行半蚀刻,确保阶梯槽的成型效果。
在一些实施例中,增加的凹槽宽度介于其框架原有的蚀刻宽度的1/3~2/3之间。便于半蚀刻区域内再次进行半蚀刻,确保阶梯槽的成型效果。
如图2所示:还包括塑封料10,所述塑封料10通过塑封固化的方式将蚀刻区7、基岛2、芯片5、焊线9均塑封于塑封料10内。塑封料10为长方体(通常为小圆柱成型,塑封时变成液体包裹芯片和框架,最终再固化成型),且由塑封料粉状颗粒料堆砌而成。通过基岛外围及引线管脚边缘蚀刻的阶梯槽,使封装时塑封料填充在阶梯槽内,有效增加了塑封料与引线框架的附着强度,提高了QFN封装的可靠性及芯片的稳定性。
由技术常识可知,本发明可以通过其它的不脱离其精神实质或必要特征的实施方案来实现。因此,上述公开的实施方案,就各方面而言,都只是举例说明,并不是仅有的。所有在本发明范围内或在等同于本发明的范围内的改变均被本发明包含。
Claims (10)
1.一种QFN封装的引脚结构,其特征在于,包括框架基体(1)和塑封料(10),所述框架基体(1)上设有基岛固定区和蚀刻区(7),所述蚀刻区(7)位于所述基岛固定区的外周;
所述基岛固定区包括芯片(5)和用于固定所述芯片(5)的基岛(2),所述芯片(5)连接在所述基岛(2)的顶面;
所述蚀刻区(7)和所述基岛(2)之间设有半蚀刻的基岛支架(3),所述蚀刻区(7)包括多个引脚(4),每个所述引脚(4)的边缘设有半蚀刻的边缘区域(6),所述边缘区域(6)内设有半蚀刻的凹槽(8);
所述芯片(5)通过焊线(9)和所述引脚(4)相连接,所述蚀刻区(7)、基岛固定区和焊线(9)均塑封在所述塑封料(10)内,且所述边缘区域(6)及边缘区域(6)内的凹槽(8)内填充所述塑封料(10)。
2.根据权利要求1所述的QFN封装的引脚结构,其特征在于,所述基岛支架(3)上内设有半蚀刻的凹槽(8),且所述述基岛支架(3)及基岛支架(3)内的凹槽(8)内填充所述塑封料(10)。
3.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述基岛支架(3)内的凹槽(8)的形状和所述基岛支架(3)的形状相适配,呈回字形。
4.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述引脚(4)的边缘区域(6)位于所述引脚(4)底面的两侧;所述边缘区域(6)内的凹槽(8)为矩形状。
5.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述边缘区域(6)的深度为所述引脚(4)厚度的1/2-2/3;所述边缘区域(6)内的凹槽(8)的深度为所述引脚(4)厚度的1/4。
6.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述基岛支架(3)的深度为所述框架基体(1)厚度的1/2-2/3,所述基岛支架(3)内的凹槽(8)的深度为所述框架基体(1)厚度的1/4。
7.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述边缘区域(6)内的凹槽(8)的宽度为边缘区域宽度的1/3~2/3;
所述基岛支架(3)内的凹槽(8)的宽度为所述基岛支架(3)宽度的1/3~2/3。
8.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述塑封料(10)是由粉状颗粒堆砌制成塑封料(10)。
9.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述框架基体(1)的材质为铜。
10.根据权利要求2所述的QFN封装的引脚结构,其特征在于,所述蚀刻区(7)有四个,四个所述蚀刻区(7)均布在所述基岛(2)的四周。
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