US20010045628A1 - Frame for semiconductor package - Google Patents

Frame for semiconductor package Download PDF

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Publication number
US20010045628A1
US20010045628A1 US09/850,211 US85021101A US2001045628A1 US 20010045628 A1 US20010045628 A1 US 20010045628A1 US 85021101 A US85021101 A US 85021101A US 2001045628 A1 US2001045628 A1 US 2001045628A1
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Prior art keywords
frame
semiconductor
lead
leads
semiconductor package
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Abandoned
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US09/850,211
Inventor
Chikao Ikenaga
Kouji Tomita
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Assigned to DAINIPPON PRINTING CO., LTD reassignment DAINIPPON PRINTING CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IKENAGA, CHIKAO, TOMITA, KOUJI
Publication of US20010045628A1 publication Critical patent/US20010045628A1/en
Priority to US10/340,943 priority Critical patent/US6897549B2/en
Priority to US11/017,896 priority patent/US7247515B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a frame for semiconductor package in which a semiconductor device is mounted on a lead frame and the outside thereof, particularly the upper surface of semiconductor device is encapsulated with molding compound.
  • FIG. 1 is a sectional view of one example of semiconductor package.
  • FIG. 2 is a plan view thereof.
  • the semiconductor package shown in FIGS. 1 and 2 is comprised of a lead frame 1 , a semiconductor device 4 mounted on die-pad 3 supported with suspending leads 2 of lead frame 1 , metallic thin wires 6 electrically connecting electrodes provided on the top face of the semiconductor device 4 with terminals 5 of lead frame 1 , respectively and molding compound 7 for encapsulating the outside region of semiconductor device 4 including the upper side of semiconductor device 4 and the lower side of die-pad 3 .
  • the semiconductor package is of non-lead type in which so-called outer leads are not projected from the semiconductor package and the two of inner leads and outer leads are integrated into terminals 5 , wherein used lead flame 1 is half-cut by etching in such a manner that die-pad 3 is positioned higher than terminals 5 . Since such a step is formed between die pads 3 and terminals 5 , molding compound 7 can be inserted into the lower side of die-pad 3 so that a thin semiconductor package can be realized even though the semiconductor package has non-exposed die-pad.
  • a matrix type frame is mainly used for the above-mentioned semiconductor package of non-lead type, in which plural semiconductor devices are arranged in a direction of a width of the matrix type frame. Further, recently, from a demand for cost down, it is thought to switch over a frame of individually molding type shown in FIG. 3 to a frame of collectively molding type shown in FIG. 4.
  • FIG. 3(A) In the frame of individually molding type, as shown in FIG. 3(A), individual molding cavities C of small size are provided separately within a frame F. After molding, individual semiconductor packages are stamped out so that semiconductor packages S shown in FIG. 3(B) are obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver paste and others, and wire bonding is carried out. Thereafter, respective semiconductor devices are individually molded with molding compound and the respective molded semiconductor devices are stamped out to form individual semiconductor packages.
  • FIG. 4(A) In the frame of collectively molding type, as shown in FIG. 4(A), some molding cavities C of large size are provided within a frame F. Multiple semiconductor devices are arranged in matrix within each molding cavity C, respectively and collectively molded with molding compound. Thereafter, the collectively molded semiconductor devices are cut at grid-leads L by means of dicing saw so that a semiconductor package S shown in FIG. 4(B) is obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver pastes and others and wire bonding is carried out. Thereafter, plural semiconductor devices arranged are collectively molded with molding compound to a given cavity size, and then the collectively molded semiconductor devices are cut to form individual semiconductor packages by dicing.
  • suspending leads In the above-mentioned semiconductor package of collectively molding type, heat generated in semiconductor device is transmitted through a die-pad to suspending leads, in which there is a case where suspending leads come off from molded resin due to a difference in thermal expansion coefficient between metal and resin. Therefore, in order to prevent the coming-off of suspending leads suspending leads are formed with projection portions, or as shown in FIG. 2, the tips of suspending leads are formed into a forked shape, so-called fish tail shape.
  • An object of the present invention is to provide a frame for semiconductor package of collectively molding type used for the production of semiconductor package, in which the frame for semiconductor package is formed in such a manner that any metal piece is not left at edges of semiconductor device in dicing.
  • a frame for semiconductor package of the present invention comprises plural lead frames arranged in matrix through grid-leads, in which the individual semiconductor devices are mounted on die-pads supported with suspending leads of the individual lead frames, respectively, the semiconductor devices are collectively molded with molding compound and the collectively molded semiconductor devices are cut at grid-leads by means of dicing saw to obtain individual semiconductor packages, wherein the suspending leads are formed into fish tails and at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads.
  • FIG. 1 is a sectional view of one example of semiconductor package.
  • FIG. 2 is a plan view of semiconductor package shown in FIG. 1.
  • FIG. 3 is an explanatory view of a frame of individually molding type.
  • FIG. 4 is an explanatory view of a frame of collectively molding type.
  • FIG. 5 is an explanatory view of R-shape generated by etching.
  • FIG. 6 is an explanatory view showing a state where metal piece is left at edges of semiconductor package.
  • FIG. 7 is a plan view of one example of the present invention.
  • FIG. 8 is a partial enlarged view of the frame shown in FIG. 7.
  • FIG. 9 is a sectional view of another example of frame shown corresponding to FIG. 8.
  • FIG. 7 is a plan view of one example of a frame of the present invention.
  • FIG. 8 is a partial enlarged plan view of the frame.
  • F designates a metal frame for lead frames, in which lead frames 10 are arranged in a matrix of 3 ⁇ 4 through grid-leads L.
  • the grid-leads L connect terminals 11 of adjacent lead frames 10 with each other.
  • die-pad 3 is supported with suspending leads 2 .
  • suspending leads 2 are formed into fish tail and both the longitudinal grid-lead L and transverse grid-lead L are eliminated within areas enclosed with fish tails of the suspending leads 2 .
  • Process for producing semiconductor packages using the frame F is as follows. First, semiconductor devices are mounted on die-pads 3 of the respective lead frames 10 of frame F through silver pastes and wire bonding is made between terminals 11 of lead frames and electrodes provided on the top face of semiconductor devices. Thereafter, twelve semiconductor devices are collectively molded with molding compound to a given cavity size and then the collectively molded semiconductor devices are cut at grid-leads L by means of dicing saw in such a manner that terminals 5 of individual lead frames are left, by which the collectively molded semiconductor devices are divided into individual semiconductor packages. In this dicing, edges of semiconductor package are formed with resin cut into an orthogonal shape, since nothing exists except molded resin at edges X of each semiconductor device.
  • FIG. 9 is a partial enlarged plan view of another example shown corresponding to FIG. 8.
  • transverse grid-lead L is eliminated within areas enclosed with fish tails of suspending leads 2 .
  • Semiconductor devices are mounted on the frame F for semiconductor packages and collectively molded with molding compound. Thereafter the collectively molded semiconductor devices are cut at dicing lines ⁇ by means dicing saw to form individual semiconductor packages. Even though longitudinal grid-lead L exists outward at each edge X of individual semiconductor package, this part is not roundish. Therefore, edges of semiconductor package are formed with mounted resin cut into orthogonal shape.
  • a frame for semiconductor package of the present invention comprises plural lead frames arranged in matrix through grid-leads, in which individual semiconductor devices are mounted on die-pads supported with suspending leads of the individual lead frames, respectively, the semiconductor devices are collectively molded with molding compound and the collectively molded semiconductor devices are cut at grid-leads by means of dicing saw to obtain individual semiconductor packages, wherein the suspending leads are formed into fish tails and at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads.

Abstract

A frame F for semiconductor package has die-pads 3 supported with suspending leads 2 of individual lead frames 10. Semiconductor devices are arranged on die-pads 3. These semiconductor devices are collectively molded with molding compounds, and then the collectively molded semiconductor packages are cut into individual packages by means of dicing saw. In the frame F, suspending leads are formed into fish tails, wherein at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads 2. Accordingly, whether R-shape generated by producing frame for semiconductor package by etching process is large or small, to exist metal piece at edges of semiconductor packages in dicing becomes almost nothing.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a frame for semiconductor package in which a semiconductor device is mounted on a lead frame and the outside thereof, particularly the upper surface of semiconductor device is encapsulated with molding compound. [0002]
  • 2. Description o the Prior Art [0003]
  • In recent years, it has been required to miniaturize and shape semiconductor product mounted on a substrate thinner, as packaging of semiconductor is made denser. It has been severely required for LSI to reduce the number of chips by improving integration level and to miniaturize and make a package lighter. The popularization of so-called CSP (Chip Size Package) is rapidly advancing. Particularly, in the development of thin semiconductor product with lead frame, the semiconductor package of single side encapsulation type has been developed in which a semiconductor device is mounted on a lead frame and the surface of semiconductor device mounted on a lead frame is encapsulated with molding compound. [0004]
  • FIG. 1 is a sectional view of one example of semiconductor package. FIG. 2 is a plan view thereof. The semiconductor package shown in FIGS. 1 and 2 is comprised of a [0005] lead frame 1, a semiconductor device 4 mounted on die-pad 3 supported with suspending leads 2 of lead frame 1, metallic thin wires 6 electrically connecting electrodes provided on the top face of the semiconductor device 4 with terminals 5 of lead frame 1, respectively and molding compound 7 for encapsulating the outside region of semiconductor device 4 including the upper side of semiconductor device 4 and the lower side of die-pad 3. The semiconductor package is of non-lead type in which so-called outer leads are not projected from the semiconductor package and the two of inner leads and outer leads are integrated into terminals 5, wherein used lead flame 1 is half-cut by etching in such a manner that die-pad 3 is positioned higher than terminals 5. Since such a step is formed between die pads 3 and terminals 5, molding compound 7 can be inserted into the lower side of die-pad 3 so that a thin semiconductor package can be realized even though the semiconductor package has non-exposed die-pad.
  • Since semiconductor device is miniature, a matrix type frame is mainly used for the above-mentioned semiconductor package of non-lead type, in which plural semiconductor devices are arranged in a direction of a width of the matrix type frame. Further, recently, from a demand for cost down, it is thought to switch over a frame of individually molding type shown in FIG. 3 to a frame of collectively molding type shown in FIG. 4. [0006]
  • In the frame of individually molding type, as shown in FIG. 3(A), individual molding cavities C of small size are provided separately within a frame F. After molding, individual semiconductor packages are stamped out so that semiconductor packages S shown in FIG. 3(B) are obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver paste and others, and wire bonding is carried out. Thereafter, respective semiconductor devices are individually molded with molding compound and the respective molded semiconductor devices are stamped out to form individual semiconductor packages. [0007]
  • In the frame of collectively molding type, as shown in FIG. 4(A), some molding cavities C of large size are provided within a frame F. Multiple semiconductor devices are arranged in matrix within each molding cavity C, respectively and collectively molded with molding compound. Thereafter, the collectively molded semiconductor devices are cut at grid-leads L by means of dicing saw so that a semiconductor package S shown in FIG. 4(B) is obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver pastes and others and wire bonding is carried out. Thereafter, plural semiconductor devices arranged are collectively molded with molding compound to a given cavity size, and then the collectively molded semiconductor devices are cut to form individual semiconductor packages by dicing. [0008]
  • In the above-mentioned semiconductor package of collectively molding type, heat generated in semiconductor device is transmitted through a die-pad to suspending leads, in which there is a case where suspending leads come off from molded resin due to a difference in thermal expansion coefficient between metal and resin. Therefore, in order to prevent the coming-off of suspending leads suspending leads are formed with projection portions, or as shown in FIG. 2, the tips of suspending leads are formed into a forked shape, so-called fish tail shape. [0009]
  • Generally, in case of producing products by etching, parts designed to be form a right angle are finished to have roundish shape (R-shape), no matter how etching process is carried out. In a frame for semiconductor package of collectively molding type having suspending leads formed into fish tail shape. R-shape formed by etching is also seen. For example, even if suspending [0010] leads 2 having fish tail shape are designed as shown in FIG. 5, etched products have R-shape as shown by the dotted line.
  • Semiconductors are mounted on the frame F for semiconductor package of collectively molding type, collectively molded, thereafter divided into individual semiconductor packages by dicing. At this time, if roundish part of R-shape does not come to dicing line α there is no problem. However, if roundish part of R-shape comes to dicing line α because of large R-shape, as shown in FIG. 6, a [0011] metal piece 8 of grid-lead L is left at an edge of individual semiconductor package. Further, in a few cases, when mounting semiconductor product on a substrate, the metal piece 8 comes off from molded resin and drops down on the substrate, so that a state where accident such as shot circuit is likely to occur is generated.
    • BRIEF SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a frame for semiconductor package of collectively molding type used for the production of semiconductor package, in which the frame for semiconductor package is formed in such a manner that any metal piece is not left at edges of semiconductor device in dicing. [0012]
  • In order to achieve the above-mentioned object, a frame for semiconductor package of the present invention comprises plural lead frames arranged in matrix through grid-leads, in which the individual semiconductor devices are mounted on die-pads supported with suspending leads of the individual lead frames, respectively, the semiconductor devices are collectively molded with molding compound and the collectively molded semiconductor devices are cut at grid-leads by means of dicing saw to obtain individual semiconductor packages, wherein the suspending leads are formed into fish tails and at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads.[0013]
    • BREIF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view of one example of semiconductor package. [0014]
  • FIG. 2 is a plan view of semiconductor package shown in FIG. 1. [0015]
  • FIG. 3 is an explanatory view of a frame of individually molding type. [0016]
  • FIG. 4 is an explanatory view of a frame of collectively molding type. [0017]
  • FIG. 5 is an explanatory view of R-shape generated by etching. [0018]
  • FIG. 6 is an explanatory view showing a state where metal piece is left at edges of semiconductor package. [0019]
  • FIG. 7 is a plan view of one example of the present invention. [0020]
  • FIG. 8 is a partial enlarged view of the frame shown in FIG. 7. [0021]
  • FIG. 9 is a sectional view of another example of frame shown corresponding to FIG. 8.[0022]
    • DETAILED DESCRIPTION
  • Then, referring to figures, embodiments of the present inventions are explained. FIG. 7 is a plan view of one example of a frame of the present invention. FIG. 8 is a partial enlarged plan view of the frame. [0023]
  • In these figures, F designates a metal frame for lead frames, in which [0024] lead frames 10 are arranged in a matrix of 3×4 through grid-leads L. The grid-leads L connect terminals 11 of adjacent lead frames 10 with each other. In each lead frame 10, die-pad 3 is supported with suspending leads 2. Further, suspending leads 2 are formed into fish tail and both the longitudinal grid-lead L and transverse grid-lead L are eliminated within areas enclosed with fish tails of the suspending leads 2.
  • Process for producing semiconductor packages using the frame F is as follows. First, semiconductor devices are mounted on die-[0025] pads 3 of the respective lead frames 10 of frame F through silver pastes and wire bonding is made between terminals 11 of lead frames and electrodes provided on the top face of semiconductor devices. Thereafter, twelve semiconductor devices are collectively molded with molding compound to a given cavity size and then the collectively molded semiconductor devices are cut at grid-leads L by means of dicing saw in such a manner that terminals 5 of individual lead frames are left, by which the collectively molded semiconductor devices are divided into individual semiconductor packages. In this dicing, edges of semiconductor package are formed with resin cut into an orthogonal shape, since nothing exists except molded resin at edges X of each semiconductor device.
  • FIG. 9 is a partial enlarged plan view of another example shown corresponding to FIG. 8. [0026]
  • In this case, transverse grid-lead L is eliminated within areas enclosed with fish tails of suspending [0027] leads 2. Semiconductor devices are mounted on the frame F for semiconductor packages and collectively molded with molding compound. Thereafter the collectively molded semiconductor devices are cut at dicing lines α by means dicing saw to form individual semiconductor packages. Even though longitudinal grid-lead L exists outward at each edge X of individual semiconductor package, this part is not roundish. Therefore, edges of semiconductor package are formed with mounted resin cut into orthogonal shape.
  • As above-mentioned, a frame for semiconductor package of the present invention comprises plural lead frames arranged in matrix through grid-leads, in which individual semiconductor devices are mounted on die-pads supported with suspending leads of the individual lead frames, respectively, the semiconductor devices are collectively molded with molding compound and the collectively molded semiconductor devices are cut at grid-leads by means of dicing saw to obtain individual semiconductor packages, wherein the suspending leads are formed into fish tails and at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads. Accordingly, whether R-shape generated by producing frame for semiconductor package by etching process is large or small, to exist metal piece at edges of semiconductor packages in dicing becomes almost nothing. Accordingly, when mounting semiconductor products on a substrate, there is no case where metal piece drops out on the substrate, so that accident of short circuit occurs. [0028]

Claims (1)

What is claimed is:
1. A frame for semiconductor package comprising plural lead frames arranged in matrix through grid-leads, in which individual semiconductor devices are mounted on die-pads supported with suspending leads of the individual lead frames, respectively, the semiconductor devices are collectively molded with molding compound and the collectively molded semiconductor devices are cut at grid-leads by means of dicing saw to obtain individual semiconductor packages, wherein the suspending leads are formed into fish tails and at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads.
US09/850,211 2000-05-09 2001-05-07 Frame for semiconductor package Abandoned US20010045628A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/340,943 US6897549B2 (en) 2000-05-09 2003-01-13 Frame for semiconductor package
US11/017,896 US7247515B2 (en) 2000-05-09 2004-12-21 Frame for semiconductor package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-135337 2000-05-09
JP2000135337A JP4349541B2 (en) 2000-05-09 2000-05-09 Resin-encapsulated semiconductor device frame

Related Child Applications (1)

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US10/340,943 Continuation US6897549B2 (en) 2000-05-09 2003-01-13 Frame for semiconductor package

Publications (1)

Publication Number Publication Date
US20010045628A1 true US20010045628A1 (en) 2001-11-29

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US09/850,211 Abandoned US20010045628A1 (en) 2000-05-09 2001-05-07 Frame for semiconductor package
US10/340,943 Expired - Lifetime US6897549B2 (en) 2000-05-09 2003-01-13 Frame for semiconductor package
US11/017,896 Expired - Lifetime US7247515B2 (en) 2000-05-09 2004-12-21 Frame for semiconductor package

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/340,943 Expired - Lifetime US6897549B2 (en) 2000-05-09 2003-01-13 Frame for semiconductor package
US11/017,896 Expired - Lifetime US7247515B2 (en) 2000-05-09 2004-12-21 Frame for semiconductor package

Country Status (2)

Country Link
US (3) US20010045628A1 (en)
JP (1) JP4349541B2 (en)

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CN102082100B (en) * 2009-11-30 2013-05-15 万国半导体有限公司 Packaging method for semiconductor devices with bulged pins

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Also Published As

Publication number Publication date
US20030098503A1 (en) 2003-05-29
US20050106777A1 (en) 2005-05-19
JP2001320008A (en) 2001-11-16
JP4349541B2 (en) 2009-10-21
US6897549B2 (en) 2005-05-24
US7247515B2 (en) 2007-07-24

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