CN102082100B - Packaging method for semiconductor devices with bulged pins - Google Patents
Packaging method for semiconductor devices with bulged pins Download PDFInfo
- Publication number
- CN102082100B CN102082100B CN 200910253503 CN200910253503A CN102082100B CN 102082100 B CN102082100 B CN 102082100B CN 200910253503 CN200910253503 CN 200910253503 CN 200910253503 A CN200910253503 A CN 200910253503A CN 102082100 B CN102082100 B CN 102082100B
- Authority
- CN
- China
- Prior art keywords
- lead frame
- plastic packaging
- pin
- metal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 238000005520 cutting process Methods 0.000 claims abstract description 37
- 238000012858 packaging process Methods 0.000 claims abstract description 5
- 238000012856 packing Methods 0.000 claims description 24
- 210000003205 muscle Anatomy 0.000 claims description 17
- 238000009826 distribution Methods 0.000 claims description 8
- 239000002699 waste material Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000638 solvent extraction Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 8
- 238000003466 welding Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 241000500881 Lepisma Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910253503 CN102082100B (en) | 2009-11-30 | 2009-11-30 | Packaging method for semiconductor devices with bulged pins |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910253503 CN102082100B (en) | 2009-11-30 | 2009-11-30 | Packaging method for semiconductor devices with bulged pins |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102082100A CN102082100A (en) | 2011-06-01 |
CN102082100B true CN102082100B (en) | 2013-05-15 |
Family
ID=44087979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200910253503 Active CN102082100B (en) | 2009-11-30 | 2009-11-30 | Packaging method for semiconductor devices with bulged pins |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102082100B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108258912B (en) * | 2015-09-11 | 2020-04-28 | 万国半导体(开曼)股份有限公司 | Pulse transformer |
CN108109796A (en) * | 2017-12-14 | 2018-06-01 | 贵州凯里经济开发区中昊电子有限公司 | The production method of SMD plastic-packaged electronic components and the metal tape of use |
CN109317583B (en) * | 2018-09-29 | 2020-06-23 | 深圳赛意法微电子有限公司 | Semiconductor device cutting rib forming method and semiconductor device processing equipment |
CN110993786B (en) * | 2019-11-13 | 2023-05-30 | 合肥久昌半导体有限公司 | Processing technology of multi-row high-power Hall element |
CN111211097B (en) * | 2020-02-17 | 2021-11-16 | 珠海格力电器股份有限公司 | Packaging module and packaging method of power semiconductor device |
CN116230648A (en) * | 2023-01-06 | 2023-06-06 | 重庆万国半导体科技有限公司 | Semiconductor device group and preparation method and application thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1905142A (en) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | QFN chip packaging technique |
CN1956157A (en) * | 2005-10-28 | 2007-05-02 | 半导体元件工业有限责任公司 | Method of forming a leaded molded array package |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4349541B2 (en) * | 2000-05-09 | 2009-10-21 | 大日本印刷株式会社 | Resin-encapsulated semiconductor device frame |
US6686258B2 (en) * | 2000-11-02 | 2004-02-03 | St Assembly Test Services Ltd. | Method of trimming and singulating leaded semiconductor packages |
US20040058478A1 (en) * | 2002-09-25 | 2004-03-25 | Shafidul Islam | Taped lead frames and methods of making and using the same in semiconductor packaging |
-
2009
- 2009-11-30 CN CN 200910253503 patent/CN102082100B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1956157A (en) * | 2005-10-28 | 2007-05-02 | 半导体元件工业有限责任公司 | Method of forming a leaded molded array package |
CN1905142A (en) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | QFN chip packaging technique |
Also Published As
Publication number | Publication date |
---|---|
CN102082100A (en) | 2011-06-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: The United States of California Sunnyvale mercury Street No. 495 Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: The United States of California Sunnyvale mercury Street No. 495 Patentee before: Alpha and Omega Semiconductor Inc. |
|
CP02 | Change in the address of a patent holder |
Address after: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: The United States of California Sunnyvale mercury Street No. 495 Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. |
|
TR01 | Transfer of patent right |
Effective date of registration: 20160831 Address after: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407 Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Address before: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. |
|
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Packaging method for semiconductor devices with bulged pins Effective date of registration: 20191210 Granted publication date: 20130515 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
|
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20130515 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |