JP5168160B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP5168160B2 JP5168160B2 JP2009006282A JP2009006282A JP5168160B2 JP 5168160 B2 JP5168160 B2 JP 5168160B2 JP 2009006282 A JP2009006282 A JP 2009006282A JP 2009006282 A JP2009006282 A JP 2009006282A JP 5168160 B2 JP5168160 B2 JP 5168160B2
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Description
1.第1の実施の形態
2.第2の実施の形態
3.第3の実施の形態
4.第4の実施の形態
5.第5の実施の形態
6.第6の実施の形態
(半導体装置の製造方法)
本発明の第1の実施の形態に係る半導体装置の製造方法について説明する。半導体装置の製造方法は、主として、チップ製造工程と、基板製造工程と、チップ実装工程と、封止工程とを有する。チップ製造工程と基板製造工程は、どちらを先に行なってもよいし、並行して行なってもよい。
チップ製造工程では、図1に示すように、突状(凸状)の接続端子2を有する半導体チップ1を製造する。半導体チップ1は、例えば、シリコンを主材料としたチップであって、裏面研削で所定の厚さとされた半導体ウエハからダイシングによって個片のチップに切り出される。半導体チップ1は、平面視四角形(正方形又は長方形)に形成される。半導体チップ1の主面には、図示しない素子や配線などが形成される。また、半導体チップ1の主面(素子形成面)には、図示しない電極パッド(例えば、アルミニウムパッド)が形成され、当該電極パッド上に、例えば金スタッドバンプからなる接続端子2が形成される。接続端子2は、半導体チップ1の主面内に複数形成される。各々の接続端子2の高さは、レベリングによってほぼ同じ高さに揃えられることが望ましい。
基板製造工程では、図2(A)の断面図及び(B)の平面図に示すように、配線層3とハンダ層4と保護層5とを有す回路基板6を製造する。回路基板6は、例えば、ガラスエポキシなどの有機材料を主材料とした基板である。回路基板6は、チップ実装用のインターポーザーとなるもので、被実装体に相当する。配線層3は、導電性金属を用いて回路基板6の主面(図の上面)側に形成される。配線層3の一部3aは、ハンダ層4によって覆われる。ハンダ層4は、例えば印刷法等によって配線層3の一部3aにプリコートされる。ハンダ層4のプリコートは、接続端子間のショートや接続不良を防止するために、厚みが均一に塗布されることが望ましい。例えば、ハンダ層4の厚みは10μm程度とする。配線層3の一部3aは、上述した半導体チップ1の接続端子2と接続される部分となる。以降の説明では、配線層3の一部3aを「接続対象部3a」と記述する。接続対象部3aは、上述した複数の接続端子2と1:1の対応関係で設けられる。
チップ実装工程では、図3(A)に示すように、半導体チップ1の主面と回路基板6の主面を対向させた状態で、図3(B)に示すように、回路基板6上に接続端子2を介して半導体チップ1を実装する。その際、半導体チップ1と回路基板6をローカルリフロー法により接続する。ローカルリフロー法では、まず、半導体チップ1の接続端子2が形成されていないチップ裏面を図示しないセラミックツールで吸着する。次に、セラミックツールで吸着した半導体チップ1の主面に形成されているアライメントマークと回路基板6の主面に形成されているアライメントマークを、それぞれカメラで認識して、画像処理によりアライメントを行なう。その後、半導体チップ1の接続端子2を、回路基板6の接続対象部3aを被覆しているハンダ層4に接触させて熱を加える。このとき、ハンダ層4を形成しているハンダ材料が接続端子2に十分濡れ上がるのに必要な時間だけ加熱を行なう。また、接続端子2の部分に余分な応力が加わらないように、セラミックツールを上下させて、半導体チップ1と回路基板6の間の空隙寸法を調整する。
封止工程では、図5に示すように、半導体チップ1を封止樹脂12で封止する。また、回路基板6の主面と反対側の面に複数の外部接続端子13を形成する。外部接続端子13は、例えばハンダボールを用いて形成される。封止樹脂12は、アンダーフィル材として用いられる封入樹脂11と同様に、シリカを主成分とするフィラーとエポキシ系樹脂から構成される。但し、封止樹脂12に関しては、封入樹脂11のように毛細管現象を利用して充填する必要がないため、封入樹脂11と比較してフィラーの混合量を増やして、熱膨張係数を半導体チップ1の材料(シリコン)に近づけることが可能である。このため、封止樹脂12の熱膨張係数は、封入樹脂11よりも半導体チップ1のチップ材料(本例ではシリコン)に近いレベル(好ましくは、同等のレベル)となっている。ここで、各部の材料の熱膨張係数を例示すると、半導体チップ1の熱膨張係数は2.6(ppm/k)、アンダーフィル材となる封入樹脂11の熱膨張係数は44(ppm/k)となっている。また、モールド材となる封止樹脂12の熱膨張係数は半導体チップ1と同じ2.6(ppm/k)、回路基板6の熱膨張係数は40(ppm/k)となっている。封止樹脂12は、半導体チップ1の内側で封入樹脂11により覆われない部分を含めて、半導体チップ1全体を覆うようにモールドされる。このとき、例えば真空モールド法のような充填性の高い方法で樹脂封止することにより、半導体チップ1の内側の空隙内に確実に封止樹脂12を充填することが可能となる。
以上の製造方法によって得られる半導体装置は、次のような構成を有するものとなる。即ち、半導体チップ1は、回路基板6上に突状の接続端子2を介して実装された状態となる。また、回路基板6と半導体チップ1との間には、複数の接続端子2を封止する状態で封入樹脂11が封入された状態となる。また、回路基板6上のチップ実装領域8の内側に接続端子2の配置領域を囲む状態で樹脂止め部7が環状に形成され、この樹脂止め部7によって封入樹脂11がせき止められた状態となる。このため、封入樹脂11は、半導体チップ1の外周部を規定する4つの辺部のうち、樹脂注入部9が設けられた1つの辺部を除く3つの辺部からはみ出さないように半導体チップ1の内側に収められた状態となる。
(半導体装置の製造方法)
本発明の第2の実施の形態に係る半導体装置の製造方法について説明する。半導体装置の製造方法は、主として、チップ製造工程と、基板製造工程と、チップ実装工程と、封止工程とを有する。チップ製造工程と基板製造工程は、どちらを先に行なってもよいし、並行して行なってもよい。本発明の第2の実施の形態においては、上記第1の実施の形態と同様の部分に同じ符号を付して説明する。
チップ製造工程では、図6に示すように、突状(凸状)の接続端子2を有する半導体チップ1を製造する。半導体チップ1は、例えば、シリコンを主材料としたチップであって、裏面研削で所定の厚さとされた半導体ウエハからダイシングによって個片のチップに切り出される。半導体チップ1は、平面視四角形(正方形又は長方形)に形成される。半導体チップ1の主面には、図示しない素子や配線などが形成される。また、半導体チップ1の主面(素子形成面)には、図示しない電極パッド(例えば、アルミニウムパッド)が形成され、当該電極パッド上に、相互拡散を防止するためのバリア膜を介して接続端子2が形成される。バリア膜の組成としては、例えばチタンなどが考えられる。接続端子2は、例えば、金や銅で形成されたポスト状の突起電極であり、表面が平滑に処理されることが望ましい。
基板製造工程では、図7(A)の断面図及び(B)の平面図に示すように、配線層3と保護層5とを有す回路基板6を製造する。回路基板6は、例えば、ガラスエポキシなどの有機材料を主材料とした基板である。回路基板6は、チップ実装用のインターポーザーとなるもので、被実装体に相当する。配線層3は、導電性金属を用いて回路基板6の主面(図の上面)側に形成される。配線層3の接続対象部3aは、上述した半導体チップ1の接続端子2と接続される部分となる。接続対象部3aは、上述した複数の接続端子2と1:1の対応関係で設けられる。
チップ実装工程では、図8に示すように、半導体チップ1の主面と回路基板6の主面を対向させるとともに、回路基板6の主面側に保護層5の開口位置に合わせてフィルム状の異方性導電樹脂14を配置する。そして、この状態から図9(A),(B)に示すように、回路基板6上に接続端子2を介して半導体チップ1を実装する。異方性導電樹脂14は、絶縁性の樹脂フィルム内に微小な導電性粒子を含有させた材料で、金属端子間で圧着することにより、導電性粒子が金属端子間に介在し、金属端子同士の導電が得られる材料である。チップ実装工程では、半導体チップ1と回路基板6をローカルリフロー法により接続する。ローカルリフロー法では、まず、半導体チップ1の接続端子2が形成されていないチップ裏面を図示しないセラミックツールで吸着する。次に、セラミックツールで吸着した半導体チップ1の主面に形成されているアライメントマークと回路基板6の主面に形成されているアライメントマークを、それぞれカメラで認識して、画像処理によりアライメントを行なう。その後、半導体チップ1と回路基板6との間に異方性導電樹脂14を介在させた状態で、回路基板6と半導体チップ1とを圧着する。このとき、異方性導電樹脂14を挟み込むようにして、半導体チップ1の接続端子2を回路基板6の接続対象部3aに接触させて熱と荷重を加える。そうすると、接続端子2と接続対象部3aは、異方性導電樹脂14に含まれる粒子状の導電材料により電気的に接続される。また、接続端子2は、加熱によって軟化した異方性導電樹脂14によって封止された状態となり、異方性導電樹脂14は、回路基板6と半導体チップ1との間に封入された状態となる。このため、異方性導電樹脂14は封入樹脂(アンダーフィル材)を構成するものとなる。また、熱と荷重を加えたときに、軟化した異方性導電樹脂14が回路基板6の主面内で濡れ広がる領域は樹脂止め部7によって制限される。したがって、半導体チップ1の周辺に樹脂がはみ出すことはない。その結果、異方性導電樹脂14は、半導体チップ1の内側に収められた状態となる。この状態で異方性導電樹脂14を熱処理によって硬化させる。
封止工程では、図10に示すように、半導体チップ1を封止樹脂12で封止する。また、回路基板6の主面と反対側の面に例えばハンダボールを用いて複数の外部接続端子13を形成する。封止樹脂12は、上記第1の実施の形態と同様に、シリカを主成分とするフィラーとエポキシ系樹脂から構成される。また、封止樹脂12に関しては、異方性導電樹脂14と比較してフィラーの混合量を増やして、熱膨張係数を半導体チップ1の材料(シリコン)に近づけることが可能である。このため、封止樹脂12の熱膨張係数は、異方性導電樹脂14よりも半導体チップ1のチップ材料(本例ではシリコン)に近いレベル(好ましくは、同等のレベル)となっている。封止樹脂12は、半導体チップ1の内側で異方性導電樹脂14により覆われない部分を含めて、半導体チップ1全体を覆うようにモールドされる。このとき、例えば真空モールド法のような充填性の高い方法で樹脂封止することにより、半導体チップ1の内側の空隙内に確実に封止樹脂12を充填することが可能となる。
以上の製造方法によって得られる半導体装置は、次のような構成を有するものとなる。即ち、半導体チップ1は、回路基板6上に突状の接続端子2を介して実装された状態となる。また、回路基板6と半導体チップ1との間には、各々の接続端子2を封止する状態で異方性導電樹脂14が封入された状態となる。また、回路基板6上のチップ実装領域8の内側に接続端子2の配置領域を囲む状態で樹脂止め部7が環状に形成され、この樹脂止め部7によって異方性導電樹脂14がせき止められた状態となる。このため、異方性導電樹脂14は、半導体チップ1の外周部を規定する4つの辺部からはみ出さないように半導体チップ1の内側に収められた状態となる。
図11は本発明の第3の実施の形態に係る半導体装置の構成を示す図であり、(A)は断面図、(B)は平面図である。本発明の第3の実施の形態においては、上述した第2の実施の形態と比較して、環状の樹脂止め部7が回路基板6の主面上に二重に設けられている点が異なる。樹脂止め部7は、回路基板6上で半導体チップ1が実装されるチップ実装領域8の内側に二重に設けられている。また、二重の樹脂止め部7は、複数の接続端子2が配置されている領域を囲むように同心状に配置されている。樹脂止め部7は、上記基板製造工程で保護層5をパターニングすることにより二重に形成される。
本発明の第4の実施の形態においては、被実装体が半導体チップとなるCOC(Chip on Chip)構造の半導体装置とその製造方法について説明する。COC構造の利点は、異なる2種類の半導体チップを多数の微小な接続端子で電気的に接続することによって、単独の半導体チップよりも高い機能を低コストで実現可能な点にある。例えば、従来のeDRAM(embedded DRAM)では容量の大きいDRAMを混載するとチップサイズが大きくなるために、コスト的、技術的にも困難である。これに対して、COC構造であれば、それぞれ異なるLogicチップとDRAMチップを組み合わせることで、容易に大容量化が可能である。さらにお互いのチップを非常に多くの端子で電気的に接続することによって、Wide Band化が可能であり、eDRAM同様に高速でアクセス可能である。また従来のスタック型パッケージや、SiPと比較すると、入出力バッファを小さくできるため低消費電力化も実現することができる。
本発明の第4の実施の形態に係る半導体装置の製造方法について説明する。半導体装置の製造方法は、主として、第1のチップ製造工程と、第2のチップ製造工程と、第1の実装工程と、第2の実装工程と、封止工程とを有する。第1のチップ製造工程と第2のチップ製造工程は、どちらを先に行なってもよいし、並行して行なってもよい。
第1のチップ製造工程では、図12に示すように、突状(凸状)の接続端子22を有する第1の半導体チップ21を製造する。第1の半導体チップ21は、例えば、シリコンを主材料としたチップである。第1の半導体チップ21は、半導体ウエハの状態で接続端子22を形成した後、裏面研削で所定の厚さとされた半導体ウエハからダイシングによって個片のチップに切り出される。第1の半導体チップ21は、平面視四角形(正方形又は長方形)に形成される。第1の半導体チップ21の主面には、図示しない素子や配線などが形成される。また、第1の半導体チップ21の主面(素子形成面)には、図示しない電極パッド(例えば、アルミニウムパッド)が形成され、当該電極パッド上に接続端子22が突状に形成される。接続端子22は、バリアメタル層23と低融点金属層24とによって構成される。バリアメタル層23は、相互拡散を防止するために形成される。低融点金属層24を構成する材料としては、例えばSn−Ag合金が挙げられる。また、バリアメタル層23としては、例えば、チタンとニッケルの積層構造が望ましい。接続端子22の直径は、例えば30μm程度である。バリアメタル層23の構成材料の1つであるニッケルの層と、低融点金属層24のSn−Ag合金の層は、それぞれ半導体ウエハの状態で電解めっき法を用いて形成することにより、低コストで均一性に優れた接続端子22を形成することが可能である。
第2のチップ製造工程では、図13に示すように、突状(凸状)の接続端子32を有する第2の半導体チップ31を製造する。接続端子32は、バリアメタル層33と低融点金属層34とによって構成される。第2の半導体チップ31は、基本的には、上述した第1の半導体チップ21と同様の方法で製造される。但し、第2の半導体チップ31は、第1の半導体チップ21よりも大きいサイズで半導体ウエハから個片に分割される。また、第2の半導体チップ31の主面上には接続端子32と同時に樹脂止め部35が形成される。樹脂止め部35は、接続端子32と同一の材料(バリアメタル、低融点金属)を用いて形成される。樹脂止め部35は、接続端子32の高さ寸法と同等の突出寸法をもって第2の半導体チップ31の主面に突状に形成される。樹脂止め部35は、複数の接続端子32が配置されている領域を囲む状態で環状に形成される。また、第2の半導体チップ31の主面内には、第1の半導体チップ21が実装されるチップ実装領域36が設定される。チップ実装領域36は、第1の半導体チップ21の外形に合わせて平面視四角形に区画される。樹脂止め部35は、チップ実装領域36の内側に平面視四角形に形成される。さらに、第2の半導体チップ31の主面内には樹脂注入部37が設けられる。樹脂注入部37は、チップ実装領域36の外側に形成される。樹脂注入部37は、樹脂止め部35に通じるように形成されている。また、第2の半導体チップ31の主面内には、チップ実装領域36よりも外側に図示しない電極パッド(例えば、アルミニウムパッド)が形成される。
第1の実装工程では、図14(A)に示すように、第1の半導体チップ21の主面と第2の半導体チップ31の主面を対向させた状態で、図14(B)に示すように、第2の半導体チップ31上に互いの接続端子22,32を介して第1の半導体チップ21を実装する。その際、第1の半導体チップ21と第2の半導体チップ31をローカルリフロー法により接続する。ローカルリフロー法では、まず、第1の半導体チップ21の接続端子22が形成されていないチップ裏面を図示しないセラミックツールで吸着する。次に、セラミックツールで吸着した第1の半導体チップ21の主面に形成されているアライメントマークと第2の半導体チップ31の主面に形成されているアライメントマークを、それぞれカメラで認識して、画像処理によりアライメントを行なう。その後、第1の半導体チップ21の接続端子22を、第2の半導体チップ31の接続端子32に接触させて熱を加える。その際、荷重を加えて低融点金属層24,34表面の自然酸化膜を破壊するとともに、加熱を行なって相互に拡散させる。また、半導体チップ間のギャップが適切になるように、セラミックツールを上下させながら冷却して接続を完了させる。
第2の実装工程では、図15に示すように、第1の半導体チップ21を実装済みの第2の半導体チップ31を、それよりもサイズが大きい配線基板41上に実装するとともに、第2の半導体チップ31と配線基板41とを金属製のワイヤ42で電気的に接続する。配線基板41上にはダイボンド材を用いて第2の半導体チップ31を接合固定する。ワイヤ42は、第2の半導体チップ31の主面上に形成された電極パッドと、配線基板41の主面上に形成された電極パッド(例えば、金パッド)との間に、ワイヤボンディングによってループ状に架け渡される。
封止工程では、図16に示すように、第1の半導体チップ21と第2の半導体チップ31を共通の封止樹脂43で一括して封止する。また、配線基板41の下面(封止樹脂43と反対側の面)には、例えばハンダボールからなる外部接続端子44を形成する。封止樹脂43は、シリカを主成分とするフィラーとエポキシ系樹脂から構成される。封止樹脂43に関しては、アンダーフィル材のように毛細管現象を利用して充填する必要がないため、アンダーフィル材と比較してフィラーの混合量を増やして、熱膨張係数を半導体チップの材料(シリコン)に近づけることが可能である。このため、封止樹脂43の熱膨張係数は、封入樹脂38よりも半導体チップ21,31のチップ材料(本例ではシリコン)に近いレベル(好ましくは、同等のレベル)となっている。封止樹脂43は、第1の半導体チップ21の内側で封入樹脂38により覆われない部分を含めて、半導体チップ21,31全体を覆うようにモールドされる。このとき、例えば真空モールド法のような充填性の高い方法で樹脂封止することにより、第1の半導体チップ21の内側の空隙内に確実に封止樹脂43を充填することが可能となる。
以上の製造方法によって得られる半導体装置は、次のような構成を有するものとなる。即ち、第1の半導体チップ21は、第2の半導体チップ31上に突状の接続端子接続端子22,32を介して実装された状態となる。また、第1の半導体チップ21と第2の半導体チップ31との間には、複数の接続端子22,32を封止する状態で封入樹脂11が封入された状態となる。また、第2の半導体チップ31上のチップ実装領域36の内側に接続端子22,32の配置領域を囲む状態で樹脂止め部35が環状に形成され、この樹脂止め部35によって封入樹脂38がせき止められた状態となる。このため、封入樹脂38は、第1の半導体チップ21の外周部を規定する4つの辺部のうち、樹脂注入部37が設けられた1つの辺部を除く3つの辺部からはみ出さないように第1の半導体チップ21の内側に収められた状態となる。
図17は本発明の第4の実施の形態に係る半導体装置の応用例を示す図である。図示した半導体装置においては、上述した第1の半導体チップ21と第2の半導体チップ31とを用いた実装構造に加えて、第1の半導体チップ21の裏面上に接合材45を用いて半導体パッケージ46が実装(接合)されている。接合材45としては、例えば、DAF(Die Attach Film)材が用いられている。半導体パッケージ46は、ワイヤ47を介して配線基板41と電気的に接続されている。第1の半導体チップ21と第2の半導体チップ31は、共通の封止樹脂43によって半導体パッケージ46と一体に封止されている。
図18は本発明の第5の実施の形態に係る半導体装置の構成を示す図であり、(A)は断面図、(B)は平面図である。本発明の第5の実施の形態においては、上述した第4の実施の形態と比較して、第2の半導体チップ31上のチップ実装領域36の内側に接続端子22,32の配置領域を囲む状態で環状の樹脂止め部35が二重に設けられている点が異なる。樹脂止め部35は、相対的に内側に形成された第1の樹脂止め部35aと相対的に外側に形成された第2の樹脂止め部35bとによって構成されている。第1の樹脂止め部35aは、上記第1のチップ製造工程で、第1の半導体チップ21の主面上に複数の接続端子22と同時に形成されるものである。また、第1の樹脂止め部35aは、接続端子22と同じ材料でかつ同じ高さ寸法で形成されるものである。第2の樹脂止め部35bは、上記第2のチップ製造工程で、第2の半導体チップ31の主面上に複数の接続端子32と同時に形成されるものである。また、第2の樹脂止め部35bは、接続端子32と同じ材料でかつ同じ高さ寸法で形成されるものである。
図20は本発明の第6の実施の形態に係る半導体装置の構成を示す図であり、(A)は断面図、(B)は平面図である。本発明の第6の実施の形態においては、上記第4の実施の形態と比較して、特に、下記の構成が異なっている。即ち、第1の半導体チップ21の主面と第2の半導体チップ31の主面に、それぞれ所定個数(図例では12個ずつ)の単位で接続端子22,32が2つの端子領域39a,39bに分けて設けられている。端子領域の分割数は3つ以上であってもよいが、ここでは2つに分けて設けられているものとする。これに対して、第2の半導体チップ31の主面上でかつチップ実装領域36の内側には、第1の樹脂止め部35aと第2の樹脂止め部35bが横に並べて設けられている。第1の樹脂止め部35aは、端子領域39aに設けられている所定個数の接続端子22,32を囲む状態で平面視四角形の環状に形成されている。第2の樹脂止め部35bは、端子領域39bに設けられている所定個数の接続端子22,32を囲む状態で平面視四角形の環状に形成されている。また、第2の半導体チップ31の主面上には、第1の樹脂止め部35aにつながる樹脂注入部37aと、第2の樹脂止め部35bにつながる樹脂注入部37bが設けられている。樹脂注入部37a,37bは、いずれもチップ実装領域36の外側に形成されている。
Claims (5)
- 被実装体と、
前記被実装体上に突状の接続端子を介して実装された半導体チップと、
前記接続端子を封止する状態で前記被実装体と前記半導体チップとの間に封入された封入樹脂とを備え、
前記封入樹脂は、前記半導体チップの外周部を規定する4つの辺部のうち、少なくとも1つの辺部からはみ出さないように前記半導体チップの内側に収められており、
前記被実装体上で前記半導体チップが実装されるチップ実装領域の内側に樹脂止め部が設けられており、
前記被実装体は、前記チップ実装領域の外側に、前記樹脂止め部に通じる樹脂注入部を有しており、
前記半導体チップの内側で前記封入樹脂により覆われない部分を含めて、前記半導体チップを封止するとともに、熱膨張係数が前記封入樹脂よりも前記半導体チップのチップ材料に近い封止樹脂を備えており、
前記樹脂止め部は、前記接続端子が配置されている領域を囲む状態で環状に形成されており、
前記環状の樹脂止め部は、少なくとも、環状の第1の樹脂止め部と、前記第1の樹脂止め部を囲む環状の第2の樹脂止め部を含んでおり、
前記第1の樹脂止め部は前記半導体チップ側に設けられており、
前記第2の樹脂止め部は前記被実装体側に設けられている、
半導体装置。 - 前記第1の樹脂止め部および前記第2の樹脂止め部は、前記接続端子と同一の材料を用いて設けられている請求項1に記載の半導体装置。
- 突状の接続端子と、前記突状の接続端子が配置されている領域を囲む状態で環状に形成されている第1の樹脂止め部とを有する半導体チップを製造する工程と、
前記半導体チップが実装されるチップ実装領域の内側に配置され前記第1の樹脂止め部を囲むように形成される環状の第2の樹脂止め部を有する被実装体を製造する工程と、
前記被実装体上に前記接続端子を介して前記半導体チップを実装するとともに、前記被実装体と前記半導体チップとの間に封入樹脂を封入する工程と、
を有する半導体装置の製造方法。 - 前記封入樹脂の封入は、前記被実装体上に前記半導体チップを実装した後、前記被実装体と前記半導体チップとの間に液状の樹脂を注入することにより行なう請求項3に記載の半導体装置の製造方法。
- 前記封入樹脂の封入は、前記被実装体と前記半導体チップとの間に異方性導電樹脂を介在させた状態で、前記被実装体と前記半導体チップとを圧着することにより行なう請求項3に記載の半導体装置の製造方法。
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