CN102779795A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN102779795A
CN102779795A CN201210148566XA CN201210148566A CN102779795A CN 102779795 A CN102779795 A CN 102779795A CN 201210148566X A CN201210148566X A CN 201210148566XA CN 201210148566 A CN201210148566 A CN 201210148566A CN 102779795 A CN102779795 A CN 102779795A
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diaphragm
semiconductor device
semiconductor element
sealing resin
resin
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丰田庆
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Panasonic Intellectual Property Management Co Ltd
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明的半导体装置具备基板、安装于所述基板上的半导体元件、被覆所述半导体元件的至少一部分的保护膜、将所述半导体元件及所述保护膜密封的密封树脂,在所述保护膜与所述密封树脂之间至少存在1处所述保护膜和所述密封树脂未密合的空隙,藉此,能够提供应力缓和优良的半导体装置。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
随着近年来的电子设备的轻薄短小化,对于内部的半导体装置也要求其高密度化和高性能化。通过半导体装置的高密度化,微细的结合处增大,装置本身也薄型化。这样的高密度化半导体装置与现有的半导体装置相比对热应力等的耐受性降低,需要想办法保持可靠性。
作为满足这样的要求的结构,提出图10所示的结构(例如,参见专利文献1)。在图10所示的结构中,半导体元件101通过安装材料106被配置在电路基板102上。半导体元件101通过金属引线103与基板电极105键合。该半导体元件101的一部分被硅橡胶107被覆,受到保护。在硅橡胶107及半导体元件101的上侧形成有由密封树脂108所形成的密封用树脂层104。
即,在基板102上安装了半导体元件101后,设置硅橡胶107的单体材料以被覆半导体元件101的一部分,通过使其加热固化形成保护膜,再用树脂密封,使密封树脂108与保护膜密合,构成半导体装置。
在这样的半导体装置中,由构成该装置的各材料的热膨胀系数差引发的应力因弹性率低于周围材料的硅橡胶107变形而缓和,由此能够抑制剥离等的发生。
专利文献
专利文献1:日本专利特开平9-321182号公报
发明的内容
但是,在上述专利文献1中,作为保护膜的硅橡胶107使用环氧·聚硅氧烷弹性体树脂组合物,在该硅橡胶的表面存在的反应性官能团包含环氧基、烷氧基、硅烷醇基、羟基、氨基的至少一种,因此该保护膜与由环氧树脂组合物形成的密封用树脂108的密合性变高。
由此,被覆半导体元件的一部分的硅橡胶107的保护膜与密封用树脂密合,应力缓和存在极限。
本发明考虑上述现有的半导体装置的课题,目的是提供应力缓和优良的半导体装置及其制造方法。
为了达到上述目的,第1项本发明是半导体装置,它具备基板、安装于上述基板上的半导体元件、被覆上述半导体元件的至少一部分的保护膜、将上述半导体元件及上述保护膜密封的密封树脂;
在上述保护膜与上述密封树脂之间至少存在1处上述保护膜和上述密封树脂未密合的空隙。
第2项本发明如上述第1项本发明的半导体装置,上述保护膜具有斥水性。
第3项本发明如上述第1或第2项本发明的半导体装置,上述保护膜由界面张力能为15mN/m以上30mN/m以下的硅橡胶材料形成;上述密封树脂的界面张力能为40mN/m以上60mN/m以下。
第4项本发明如上述第1~第3项中任一项的本发明的半导体装置,上述保护膜的厚度为10μm以上2000μm以下;上述保护膜在摄氏25度至摄氏260度的弹性率在0.5MPa以上10MPa以下的范围内。
第5项本发明如上述第1项本发明的半导体装置,上述保护膜由硅橡胶材料形成;上述硅橡胶材料的前体具有有机聚硅氧烷骨架;上述前体通过氢化硅烷化反应引起的热固化反应,固化为具有硅氧烷骨架的硅橡胶。
第6项本发明如上述第1~第5项本发明的半导体装置,上述空隙的厚度为0.1μm以上100μm以下。
第7项本发明如上述第1项本发明的半导体装置,上述基板为引线框,上述半导体元件与上述引线框的外部端子通过金属引线连接,上述保护膜被覆上述金属引线的与上述半导体元件的连接部分。
第8项本发明如上述第1项本发明的半导体装置,上述基板为电路基板,通过金属引线,上述半导体元件与上述电路基板的电极部连接,上述保护膜被覆上述金属引线的与上述半导体元件的连接部分。
第9项本发明如上述第1项本发明的半导体装置,上述基板为电路基板,上述半导体元件的电极焊盘和上述电路基板的电极焊盘由焊锡连接部连接,配置了该焊锡连接部的区域用底部填充树脂(アンダ一フイル樹脂)填充,上述保护膜被覆上述半导体元件和上述底部填充树脂的圆角部(フィレツト部),上述密封树脂密封上述半导体元件和上述底部填充树脂的圆角部以及上述保护膜,在上述保护膜和上述底部填充树脂的圆角部之间形成有另外的空隙。
第10项本发明如上述第1项本发明的半导体装置,上述密封树脂为环氧树脂;上述保护膜由硅橡胶材料形成;上述硅橡胶材料的前体具有有机聚硅氧烷骨架;上述前体通过氢化硅烷化反应引起的热固化反应,固化为具有硅氧烷骨架的硅橡胶。
第11项本发明是半导体装置的制造方法,具有
装载保护膜的前体以被覆安装于基板的半导体元件的至少一部分的装载工序;
通过上述前体聚合形成上述保护膜的聚合工序;
用密封树脂将上述半导体元件及上述保护膜密封,在上述保护膜与上述密封树脂之间至少形成1处上述保护膜和上述密封树脂未密合的空隙的密封工序。
第12项本发明如上述第11项本发明的半导体装置的制造方法,在上述装载工序中,装载作为上述保护膜的前体的硅橡胶单体;
在上述聚合工序中,通过利用上述硅橡胶单体的聚合的橡胶化,形成上述保护膜。
第13项本发明如上述第11项本发明的半导体装置的制造方法,在上述密封工序中,使用与上述保护膜的润湿性差的材料,形成上述密封树脂。
通过本发明,能够提供应力缓和优良的半导体装置及其制造方法。
附图的简单说明
图1本发明的实施方式1的半导体装置的截面结构图。
图2(a)~(e)用于说明本发明的实施方式1的半导体装置的制造方法的截面结构图。
图3本发明的实施方式2的半导体装置的截面结构图。
图4(a)~(e)用于说明本发明的实施方式2的半导体装置的制造方法的截面结构图。
图5本发明的实施方式3的半导体装置的截面结构图。
图6(a)~(e)用于说明本发明的实施方式3的半导体装置的制造方法的截面结构图。
图7本发明的实施方式1的变形例的半导体装置的截面结构图。
图8本发明的实施方式2的变形例的半导体装置的截面结构图。
图9本发明的实施方式1的变形例的半导体装置的截面结构图。
图10具有现有的半导体元件保护膜的树脂密封型半导体装置的截面图。
发明的具体实施方式
以下,根据附图对本发明的实施方式进行详细的说明。
实施方式1
图1为本发明的实施方式1的半导体装置的结构截面示意图。如图1所示,本实施方式1的半导体装置包含具有芯片焊盘部(ダイパツド部)1B和外部端子1A的引线框1、介以糊料2搭载于芯片焊盘部1B的半导体元件3、连接半导体元件3与外部端子1A的金属引线4。还有,在本实施方式1的半导体装置中,半导体元件3被斥水性硅橡胶的保护膜5被覆。以引线框1的外部端子1A的前端露出的状态,密封树脂6被覆引线框1的外部端子1A、芯片焊盘部1B、半导体元件3、保护膜5及金属引线4而实现密封。此外,金属引线4的与半导体元件3的连接部分4a也被斥水性硅橡胶的保护膜5被覆。在保护膜5和密封树脂6之间形成有作为本发明的空隙的一例的空隙层7。还有,本实施方式的引线框1是本发明的基板的一例。再有,图1的空隙层7为将其厚度放大的图示,在以下的图中也同样。
引线框1由铜等热传导性及电导性优良的材料形成。密封树脂6无特别的限定,例如可以采用公知的热固性环氧树脂,该树脂是将作为主剂的邻甲酚醛型环氧树脂(オルトクレゾ一ルノボラツク型のエポキシ)、作为固化剂的能够使主剂固化的酚醛树脂配合,再配合了70重量份-90重量份左右的无机填充剂的树脂。
上述斥水性硅橡胶的保护膜5及由其构成的空隙层7是本发明的重要部分,以下对其作详细的说明。
虽然对形成保护膜5的材料没有限定,但较好是使具有疏水性官能团的硅橡胶前体固化而形成的、固化后的界面张力能为15mN/m以上30mN/m以下的硅橡胶。保护膜5可以含有无机填充材料。这时,其体积电阻率上升,藉此能够更可靠地防止金属引线4间的短路及迁移等不良情况。
作为液状硅橡胶的前体,例如可以使用文献(原产地技术杂志67卷(2004)III-7(Origin Technical Journal No.67(2004)III-7))中记载的含乙烯基的有机聚硅氧烷和、氢化有机聚硅氧烷和、铂等的固化催化剂的混合物等公知的材料,对是1液型还是2液型没有限定。即,作为液状硅橡胶的前体的基本的化学结构是主链结构为硅氧烷骨架结构,烷基或氟烷基或两者与硅原子结合的结构。还有,在硅氧烷骨架的末端结合有乙烯基等硅氧烷骨架彼此间结合所必需的反应部位。
采用公知的方法使上述混合物进行利用热的加成固化时,发生氢化硅烷化反应,前体形成作为本发明的重要的部位的、化学稳定、且低弹性率、且具有无缺陷的致密的结构的保护膜。与硅原子结合的官能团根据达到斥水性的需要,特别优选烃类官能团。
作为这样的硅橡胶的前体的有机聚硅氧烷例如可以通过在强酸的存在下使有机硅氧烷聚合后,添加水和特定的有机硅化合物等的公知的方法来制造。
这样形成的保护膜5固化后的界面张力能在15mN/m以上30mN/m以下的范围内,显示斥水性。由环氧类热固化性树脂形成的密封树脂6的界面张力能为40mN/m以上60mN/m以下,保护膜5在密封和随后的固化的工序中不与密封树脂6密合,在其界面形成空隙层7。
另外,如果保护膜5的界面张力能小于15mN/m,则难以维持保护膜自身的形状,在树脂的密封工序中,形状崩毁,不理想。而如果界面张力能大于30mN/m,则无法获得足够的斥水性,显示出与密封树脂6的密合性,无法获得本实施例的结构。
但是,密封树脂6在固化时与金属表面的官能团反应,藉此往金属的密合性优良,因此与保护膜5以外的引线框1,具体来说,与芯片焊盘部1B的未与保护膜5接触的部分及引线框1的外部端子1A密合。因而,保护膜5及由其被覆的半导体元件3在封装内被固定,作为封装整体能够维持足够的强度。
还有,保护膜5的固化后的弹性率在摄氏25℃(室温)~260℃(再流温度)为0.5MPa以上10MPa以下的范围。
还有,上述空隙层7的厚度为0.1μm以上100μm以下。
接着,说明本发明的实施方式1的半导体装置的制造方法。
图2(a)~(e)为用于说明本实施方式1的半导体装置的制造方法的截面结构图。
如图2(a)所示,在引线框1的芯片焊盘部1B上适量涂布糊料2。再如图2(b)所示,在糊料2上搭载半导体元件3。糊料2的涂布可以使用公知的涂布器,半导体元件3的搭载可以使用公知的贴片机(ダイボンダ一)。
其后,如图2(c)所示,半导体元件3和引线框1的外部端子1A用金丝引线4进行电气地且机械地接合。金丝引线4的连接可以使用公知的线焊机(ワイヤボンダ)。
其后,如图2(d)所示,将作为保护膜5的前体的硅橡胶单体5a适量地滴加在半导体元件3和糊料2的与空气接触的部分上。此时,在金丝引线4的与半导体元件3的连接部分4a上也滴下硅橡胶单体5a。该滴加量最好是以后述的方法固化为硅橡胶时的厚度达到10μm以上、2000μm以下。厚度如果小于10μm则再流工序等加热时所产生的热应力无望得到充分的缓和,而如果大于2000μm则后述的密封树脂6的厚度变小,密封树脂6的厚度变小的部分的强度不足。还有,本实施方式1的半导体装置整体的厚度为5mm。
还有,硅橡胶单体5a可以采用硅原子上结合了烷基的有机聚硅氧烷和铂等的固化催化剂的混合物。滴下硅橡胶单体5a后,在150℃加热4小时左右,能够形成保护膜5。此外,如上所述滴下硅橡胶单体5a的工序为本发明的“装载保护膜的前体以被覆安装于基板的半导体元件的至少一部分”工序(装载工序)的一例。再有,如上所述加热的工序为本发明的“通过上述前体的聚合形成上述保护膜”工序(聚合工序)的一例。
这样在半导体元件3上形成保护膜5后,将其设置在加热至适当的温度的密封模具内,如图2(e)所示,将作为环氧类热固化树脂的密封树脂6利用公知的传递模塑法(トランスフア-モ-ルド法)挤压填充,进行固化。这样,挤压填充密封树脂,使其固化的工序为本发明的“用密封树脂将上述半导体元件及上述保护膜密封,在上述保护膜与上述密封树脂之间至少形成1处上述保护膜和上述密封树脂未密合的空隙”工序(密封工序)的一例。使环氧类热固性树脂(密封树脂6)固化时,环氧类热固性树脂的界面张力能为40mN/m以上60mN/m以下,藉此其表面与形成保护膜5的硅橡胶固化体不完全密合。这样,通过使用对密封树脂6的润湿性差的材料作为这样的保护膜5的材料,密封树脂6与保护膜5不完全密合,形成空隙层7,制造图1所示的本发明的实施方式1的半导体装置。
本实施方式1的半导体装置中,如上所述,在保护膜5和密封树脂6之间形成空隙层7,藉此能够极其有效地缓和由密封树脂和其他构件的线膨胀系数差引起的内部应力。
但是,现有的专利文献1所示的硅橡胶使用环氧·硅氧烷弹性体树脂组合物,存在于表面的反应性官能团包含环氧基、烷氧基、硅烷醇基、羟基、氨基的至少一种,但是以上的官能团都是亲水性的,即使是与环氧树脂组合物之间的及其轻微的剥离,由于其亲水性,也会使水滞留在环氧树脂(密封用树脂层104)与硅橡胶107之间,存在导致再流工序时等的可靠性的降低的问题。
但是,在本实施方式1中,通过使用斥水性硅橡胶的保护膜5,能够实现减少因水从外部侵入而引起的再流时的不良情况的发生。
即,由硅橡胶固化体形成的保护膜5的界面张力能为15mN/m以上30mN/m以下,对此,水的界面张力能约为72mN/m,因此由硅橡胶固化体形成的保护膜5具有斥水性。因此,作为环氧类热固性树脂的密封树脂6与由硅橡胶固化体形成的保护膜5之间的空隙层7中不会滞留水。或者即使在该空隙层7中有水滞留,水也无法浸入界面张力低的硅橡胶固化体中。
这样,就抑制了由水从外部侵入引起的可靠性的降低,能够利用空隙层7更有效地缓和因半导体装置的各构件的热变形所引起的应力的产生。即,本发明的半导体装置通过同时抑制由水的侵入及热应力引起的可靠性的降低,能够具有更长的寿命。
还有,本实施方式中,使用依靠热而固化的硅橡胶单体作为形成保护膜5的材料,但也可以使用可利用光或热和光两者而固化的硅橡胶单体。
实施方式2
接着,说明本发明的实施方式2。本发明的实施方式2的半导体装置中,与实施方式1不同,半导体元件3被配置在电路基板上。还有,对与实施方式1对应的结构赋予相同的符号。
图3为本发明的实施方式2的半导体装置的截面构成图。
本实施方式2的半导体装置包含电路基板8、介以糊料2搭载于电路基板8的半导体元件3、连接半导体元件3与电路基板8上的电极部8a的金属引线4。还有,本实施方式2的半导体装置中,半导体元件3被斥水性硅橡胶的保护膜5被覆。这时,金属引线4的与半导体元件3的连接部分4a也被斥水性硅橡胶的保护膜5被覆,与斥水性硅橡胶密合。还有,半导体元件3、金属引线4、斥水性硅橡胶的保护膜5整体被密封树脂6密封。本实施方式2的电路基板8是本发明的基板的一例。在图3中,图示了多层基板,但可不限于多层。
在本实施例2的半导体装置中,与实施方式1同样,在保护膜5和密封树脂6之间形成有空隙层7。这样,通过形成空隙层7,可以缓和因各材料的热变形所引起的应力的产生。还有,通过使用斥水性硅橡胶的保护膜5,可以抑制由水从外部的侵入引起的可靠性的降低。由此,能够成为长寿命的半导体装置。
接着,对本发明的实施方式2的半导体的制造方法进行说明。
图4(a)~(e)为用于说明本实施方式2的半导体装置的制造方法的截面结构图。
如图4(a)所示,在电路基板8上适量涂布导电性的糊料2。再如图4(b)所示,在糊料2上搭载半导体元件3。糊料2的涂布可以使用公知的涂布器,半导体元件3的搭载可以使用公知的贴片机。
其后,如图4(c)所示,将半导体元件3和电路基板的电极部8a用金丝引线4进行电气地且机械地接合。金丝引线4的连接可以使用公知的线焊机。
其后,如图4(d)所示,将作为保护膜5的前体的硅橡胶单体5a适量地滴加在半导体元件3和糊料2的与空气接触的部分上。这时,在金丝引线4的与半导体元件3的连接部分4a上也滴下硅橡胶单体5a。该滴加量最好是以后述的方法固化为硅橡胶时的厚度达到10μm以上、2000μm以下。厚度如果小于10μm则再流工序等加热时所产生的热应力无望得到充分的缓和,而如果大于2000μm则后述的密封树脂6的厚度变小,密封树脂6的厚度变小的部分的强度不足。
还有,硅橡胶单体5a可以与上述实施方式1的半导体制造方法的说明中所述的同样。滴下硅橡胶单体5a后,在150℃加热4小时左右,能够形成保护膜5。此外,如上所述滴下硅橡胶单体5a的工序为本发明的“装载保护膜的前体以被覆安装于基板的半导体元件的至少一部分”工序(装载工序)的一例。再有,如上所述加热的工序为本发明的“通过上述前体聚合形成上述保护膜”工序(聚合工序)的一例。
这样形成保护膜5后,将其设置在加热至适当的温度的密封模具内,如图4(e)所示,仅对搭载了电路基板8的半导体元件的面利用公知的传递模塑法挤压填充作为环氧类热固化树脂的密封树脂6,将其固化。这样,挤压填充密封树脂,使其固化的工序为本发明的“用密封树脂将上述半导体元件及上述保护膜密封,在上述保护膜与上述密封树脂之间至少形成1处上述保护膜和上述密封树脂未密合的空隙”工序(密封工序)的一例。使环氧类热固性树脂固化时,环氧类热固性树脂的界面张力能为40mN/m以上60mN/m以下,藉此其表面与形成保护膜5的硅橡胶固化体不完全密合。这样,通过使用对密封树脂6的润湿性差的材料作为保护膜5的材料,藉此不完全密合,形成空隙层7,制造图3所示的本发明的实施方式2的半导体装置。
这样的实施方式2,如以下说明,能够减少因水从外部侵入而引起的再流时的不良情况的发生,能够极其有效地缓和由密封树脂6和其他构件的线膨胀系数差引发的内部应力,因此能够获得高可靠性。
即,作为硅橡胶固化体的保护膜5的界面张力能为15mN/m以上30mN/m以下,对此,水的界面张力能约为72mN/m,因此作为硅橡胶固化体的保护膜5具有斥水性。因此,作为环氧类热固性树脂的密封树脂6与作为硅橡胶固化体的保护膜5之间的空隙层7中不会滞留水。或者即使在该空隙层7中有水滞留,水也无法浸入界面张力低的硅橡胶固化体中。
而且,由于空隙层7的存在,由各构件的线膨胀系数差引起的内部应力得到极其有效地缓和,该实施方式能够提供长寿命的可靠性高的半导体装置。
实施方式3
接着,说明本发明的实施方式3。本发明的实施方式3的半导体装置中,与实施方式2不同,不同点是:半导体元件3通过焊锡与电路基板电气地且机械地连接。还有,对与实施方式2对应的结构赋予相同的符号。
图5为本发明的实施方式3的半导体装置的截面构成图。
本实施方式3的半导体装置包含电路基板80和半导体元件3。该电路基板80的电极焊盘(電極パツド)9和半导体元件3的电极焊盘10通过焊锡连接部11电气地且机械地连接。配置有该焊锡连接部11的区域用底部填充(アンダ一フイル)树脂12填充。而且,半导体元件3及底部填充树脂12的圆角部(フイレツト部)12a被斥水性硅橡胶的保护膜5被覆。还有,半导体元件3、底部填充树脂12的圆角部12a、斥水性硅橡胶的保护膜5整体被密封树脂6密封。此外,本实施方式3的电路基板80是本发明的基板的一例。
在保护膜5和密封树脂6之间形成有空隙层7,在底部填充树脂12的圆角部12a和保护膜5之间形成第2空隙层71。
这样,通过形成空隙层7,由各材料的热变形引起的应力的产生得到缓和,在本实施方式3中,通过还形成第2空隙层71,应力的产生进一步得到缓和。而且,由水从外部侵入引起的可靠性的降低也被抑制,能够得到更长寿命的半导体装置。
接着,对本发明的实施方式3的半导体的制造方法进行说明。
图6(a)~(e)为用于说明本实施方式3的半导体装置的制造方法的截面结构图。
如图6(a)所示,在电路基板80上设有电极焊盘9,在半导体元件3上设有电极焊盘10。再在电极焊盘9及电极焊盘10上分别配置焊锡球11a。
接着,如图6(b)所示,用焊锡球11a连接电极焊盘9和电极焊盘10,作为连接方法进行如下连接。以公知的倒装贴片机(フリツプチツプボンダ一),将连接前的基板80及半导体元件3的设定温度设为摄氏170度。其后,转移到利用图像识别的定位和随其后的连接工序,加压时,使加压力为0.1N,在3秒的时间内将电路基板80及半导体元件3从作为装置设定温度的170℃加热升温至摄氏300度,藉此能够连接。
接着,如图6(c)所示,在倒装贴片连接的电路基板80和半导体元件3的间隙填充底部填充树脂12,将其固化。底部填充树脂12的填充可以使用公知的涂布器,用公知的方法填充。即,在电路基板80和半导体元件3的间隙的端部中的至少1处滴下适量的底部填充材料。其后,依靠毛细管现象,底部填充材料适量地充满填充焊锡连接部11和电路基板80和半导体元件3的间隙。填充后,例如在165℃加热2小时,底部填充材料热固化,藉此底部填充材料的填充工序完成。
其后,如图6(d)所示,将作为保护膜5的前体的硅橡胶单体5a适量地滴下以被覆半导体元件3及底部填充树脂12的圆角部12a。该滴加量最好是以后述的方法固化为硅橡胶时的厚度达到10μm以上、2000μm以下。厚度如果小于10μm则再流工序等加热时所产生的热应力无望得到充分的缓和,而如果大于2000μm则后述的密封树脂6的厚度变小,密封树脂6的厚度变小的部分的强度不足。
还有,硅橡胶单体5a可以与上述实施方式1的半导体制造方法的说明中所述的同样。滴下硅橡胶单体5a后,在150℃加热4小时左右,能够形成保护膜5。
该工序中,在保护膜5和底部填充树脂12的圆角部12a之间形成第2空隙层71。即,由于使用环氧类热固性树脂作为底部填充树脂12,因此在形成硅橡胶固化体的保护膜5时,利用界面张力能之差,形成第2空隙层71。
此外,如上所述滴下硅橡胶单体的工序为本发明的“装载保护膜的前体以被覆安装于基板的半导体元件的至少一部分”工序(装载工序)的一例。再有,如上所述加热的工序为本发明的“通过上述前体聚合形成上述保护膜”工序(聚合工序)的一例。
这样形成保护膜5后,将其设置在加热至适当温度的密封模具内,如图6(e)所示,仅对搭载了电路基板80的半导体元件的面利用公知的传递模塑法挤压填充作为环氧类热固化树脂的密封树脂6,将其固化。这样,挤压填充密封树脂6,使其固化的工序为本发明的“用密封树脂将上述半导体元件及上述保护膜密封,在上述保护膜与上述密封树脂之间至少形成1处上述保护膜和上述密封树脂未密合的空隙”工序(密封工序)的一例。使作为环氧类热固性树脂的密封树脂6固化时,环氧类热固性树脂的界面张力能为40mN/m以上60mN/m以下,藉此其表面与形成保护膜5的硅橡胶固化体不完全密合。这样,通过使用对密封树脂6的润湿性差的材料作为保护膜5的材料,藉此不完全密合,形成空隙层7。
如上所述,制造图5所示的本发明的实施方式3的半导体装置。
这样的实施方式3,如以下说明,能够减少因水从外部侵入而引起的再流时的不良情况的发生,能够极其有效地缓和由密封树脂6及底部填充树脂12和其他构件的线膨胀系数差引发的内部应力,因此能够获得高可靠性。
即,作为硅橡胶固化体的保护膜5的界面张力能为15mN/m以上30mN/m以下,对此,水的界面张力能约为72mN/m,因此作为硅橡胶固化体的保护膜5具有斥水性。为此,作为环氧类热固性树脂的密封树脂6与作为硅橡胶固化体的保护膜5之间的空隙层7中不会滞留水。或者即使在该空隙层7中有水滞留,水也无法浸入界面张力低的硅橡胶固化体中。
而且,由于空隙层7及第2空隙层71的存在,由各构件的线膨胀系数差引起的内部应力得到极其有效地缓和,该实施方式能够提供长寿命的可靠性高的半导体装置。
还有,上述实施方式1~3中,形成保护膜5以被覆半导体元件3的整体,但可以如表示实施方式1的变形例的半导体装置的图7的截面结构图所示那样,形成保护膜50覆盖半导体元件3的一部分。图7所示的半导体装置中,金属引线4的与半导体元件3的连接部分4a和糊料2的端部分2a(露出部分)以及半导体元件3的端部3a被保护膜50被覆。该保护膜50与实施方式1的保护膜5的材料及制造方法相同。在保护膜50和密封树脂6之间形成空隙层72。在该结构中,能够降低施加于连接部分4a附近的应力,也能够防止水的滞留。
还有,在实施方式2中,金属引线4的与半导体元件3的接触部分4a被保护膜5被覆,但可以如表示实施方式2的变形例的半导体装置的图8的截面结构图所示那样,也可以形成保护膜被覆金属引线4的与电极部8a的连接部分4b。在图8所示的半导体装置中,从半导体元件3的端部3a至电极部8a由保护膜52被覆,在保护膜52和密封树脂6之间形成空隙层73。通过该结构,至少连接部分4b受到的应力得到降低,也能够防止水的滞留。还可以如图7所示那样,也可以形成保护膜被覆连接部分4a。
还有,在上述实施方式1~3中,虽然在保护膜5和密封树脂6间的边界全部区域形成空隙层7,但也可以不在整个区域形成。此外,空隙可以不形成为层状,例如,如表示实施方式1的变形例的半导体装置的图9所示那样,只要在至少1处形成空隙层74就能够比现有的结构更有效地缓和应力。
此外,本发明中的空隙的大小形成为通过由对密封树脂6的润湿性差的材料形成保护膜5,密封树脂6和保护膜5的密合性变差,发挥应力缓和的效果的程度的大小。
本发明的存在于保护膜和密封树脂的界面的空隙在上述半导体元件为面对大电流的所谓功率元件时特别有效。由于驱动时的元件温度上升至250℃,因此在保护元件的上述保护膜热膨胀时,由于空隙的存在,能够缓和保护膜的膨胀施加于周围的密封树脂的应力。
产业上的利用可行性
本发明的半导体装置及其制造方法,具有优良的缓和应力的效果,作为高密度化半导体封装等是有用的。
符号的说明
1引线框
1A外部端子
1B芯片焊盘部
2糊料
3半导体元件
4金属引线
5、50、52保护膜
6密封树脂
7、72、73、74空隙层
8电路基板
9电极焊盘
10电极焊盘
11焊锡连接部
11a焊锡球
12底部填充树脂
12a圆角部
71第2空隙层
101半导体元件
102电路基板
103金属引线
104密封用树脂层
105基板电极
106安装材料
107硅橡胶
108密封树脂

Claims (13)

1.半导体装置,其特征在于,具备基板、安装于所述基板上的半导体元件、被覆所述半导体元件的至少一部分的保护膜、将所述半导体元件及所述保护膜密封的密封树脂;
在所述保护膜与所述密封树脂之间至少存在1处所述保护膜和所述密封树脂未密合的空隙。
2.如权利要求1所述的半导体装置,其特征在于,所述保护膜具有斥水性。
3.如权利要求1所述的半导体装置,其特征在于,所述保护膜由界面张力能为15mN/m以上30mN/m以下的硅橡胶材料形成;所述密封树脂的界面张力能为40mN/m以上60mN/m以下。
4.如权利要求1所述的半导体装置,其特征在于,所述保护膜的厚度为10μm以上2000μm以下;所述保护膜在摄氏25度至摄氏260度的弹性率在0.5MPa以上10MPa以下的范围内。
5.如权利要求1所述的半导体装置,其特征在于,所述保护膜由硅橡胶材料形成;所述硅橡胶材料的前体具有有机聚硅氧烷骨架;所述前体通过氢化硅烷化反应引起的热固化反应,固化为具有硅氧烷骨架的硅橡胶。
6.如权利要求1所述的半导体装置,其特征在于,所述空隙的厚度为0.1μm以上100μm以下。
7.如权利要求1所述的半导体装置,其特征在于,所述基板为引线框,所述半导体元件与所述引线框的外部端子通过金属引线连接,所述保护膜被覆所述金属引线的与所述半导体元件的连接部分。
8.如权利要求1所述的半导体装置,其特征在于,所述基板为电路基板,所述半导体元件与所述电路基板的电极部通过金属引线连接,所述保护膜被覆所述金属引线的与所述半导体元件的连接部分。
9.如权利要求1所述的半导体装置,其特征在于,所述基板为电路基板,所述半导体元件的电极焊盘和所述电路基板的电极焊盘由焊锡连接部连接,配置了该焊锡连接部的区域用底部填充树脂填充,所述保护膜被覆所述半导体元件和所述底部填充树脂的圆角部,所述密封树脂密封所述半导体元件和所述底部填充树脂的圆角部以及所述保护膜,在所述保护膜和所述底部填充树脂的圆角部之间形成有另外的空隙。
10.如权利要求1所述的半导体装置,其特征在于,所述密封树脂为环氧树脂;所述保护膜由硅橡胶材料形成;所述硅橡胶材料的前体具有有机聚硅氧烷骨架;所述前体通过氢化硅烷化反应引起的热固化反应,固化为具有硅氧烷骨架的硅橡胶。
11.半导体装置的制造方法,其特征在于,具有
装载保护膜的前体以被覆安装于基板的半导体元件的至少一部分的装载工序;
通过所述前体聚合形成所述保护膜的聚合工序;
用密封树脂将所述半导体元件及所述保护膜密封,在所述保护膜与所述密封树脂之间至少形成1处所述保护膜和所述密封树脂未密合的空隙的密封工序。
12.如权利要求11所述的半导体装置的制造方法,其特征在于,在所述装载工序中,装载作为所述保护膜的前体的硅橡胶单体;
在所述聚合工序中,通过利用所述硅橡胶单体的聚合的橡胶化,形成所述保护膜。
13.如权利要求11所述的半导体装置的制造方法,其特征在于,在所述密封工序中,使用与所述保护膜的润湿性差的材料,形成所述密封树脂。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475645A (zh) * 2016-01-13 2018-08-31 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN109524372A (zh) * 2018-12-29 2019-03-26 山东盛品电子技术有限公司 封装结构、解决传感器芯片封装后封装体内部应力的方法
CN109727925A (zh) * 2017-10-31 2019-05-07 华润微电子(重庆)有限公司 一种提高塑封模块可靠性的封装结构及方法
WO2020238773A1 (zh) * 2019-05-27 2020-12-03 华为技术有限公司 一种封装结构及移动终端
CN113808782A (zh) * 2020-06-16 2021-12-17 三菱电机株式会社 电气设备布线部件

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5867465B2 (ja) 2013-08-22 2016-02-24 Tdk株式会社 磁気センサ
US20150060123A1 (en) * 2013-09-04 2015-03-05 Texas Instruments Incorporated Locking dual leadframe for flip chip on leadframe packages
JP2015106649A (ja) * 2013-11-29 2015-06-08 株式会社デンソー 電子装置
US10181445B2 (en) 2014-12-29 2019-01-15 Mitsubishi Electric Corporation Power module
JP6626294B2 (ja) 2015-09-04 2019-12-25 株式会社東芝 半導体装置および光結合装置
WO2018116785A1 (ja) * 2016-12-20 2018-06-28 株式会社デンソー 半導体装置およびその製造方法
US10861741B2 (en) * 2017-11-27 2020-12-08 Texas Instruments Incorporated Electronic package for integrated circuits and related methods
US11538767B2 (en) 2017-12-29 2022-12-27 Texas Instruments Incorporated Integrated circuit package with partitioning based on environmental sensitivity
US10516381B2 (en) * 2017-12-29 2019-12-24 Texas Instruments Incorporated 3D-printed protective shell structures for stress sensitive circuits
JP6626537B2 (ja) * 2018-07-17 2019-12-25 株式会社東芝 半導体装置および光結合装置
JP7155748B2 (ja) * 2018-08-22 2022-10-19 株式会社デンソー 半導体装置
EP3633716A1 (en) * 2018-10-05 2020-04-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Package with embedded electronic component being encapsulated in a pressureless way
JP2020102517A (ja) * 2018-12-21 2020-07-02 トヨタ自動車株式会社 電子回路装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174958A (ja) * 1986-01-28 1987-07-31 Mitsubishi Electric Corp 半導体装置の製造方法
US5008733A (en) * 1982-10-11 1991-04-16 Toray Silicone Company, Limited Semiconductor device
CN101154601A (zh) * 2006-09-29 2008-04-02 冲电气工业株式会社 半导体器件以及半导体器件的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185343A (ja) * 1986-02-08 1987-08-13 Mitsubishi Electric Corp 樹脂封止形半導体装置
JP3161142B2 (ja) * 1993-03-26 2001-04-25 ソニー株式会社 半導体装置
JPH0855941A (ja) * 1994-08-15 1996-02-27 Nagase Chiba Kk 電子部品の樹脂封止物及びそれに用いるエポキシ樹脂組成物
JP3154208B2 (ja) * 1995-10-24 2001-04-09 信越化学工業株式会社 シリコーンゴム組成物

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008733A (en) * 1982-10-11 1991-04-16 Toray Silicone Company, Limited Semiconductor device
JPS62174958A (ja) * 1986-01-28 1987-07-31 Mitsubishi Electric Corp 半導体装置の製造方法
CN101154601A (zh) * 2006-09-29 2008-04-02 冲电气工业株式会社 半导体器件以及半导体器件的制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475645A (zh) * 2016-01-13 2018-08-31 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN108475645B (zh) * 2016-01-13 2023-07-18 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN109727925A (zh) * 2017-10-31 2019-05-07 华润微电子(重庆)有限公司 一种提高塑封模块可靠性的封装结构及方法
CN109524372A (zh) * 2018-12-29 2019-03-26 山东盛品电子技术有限公司 封装结构、解决传感器芯片封装后封装体内部应力的方法
WO2020238773A1 (zh) * 2019-05-27 2020-12-03 华为技术有限公司 一种封装结构及移动终端
CN113808782A (zh) * 2020-06-16 2021-12-17 三菱电机株式会社 电气设备布线部件

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