CN1531076A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1531076A
CN1531076A CNA2004100089257A CN200410008925A CN1531076A CN 1531076 A CN1531076 A CN 1531076A CN A2004100089257 A CNA2004100089257 A CN A2004100089257A CN 200410008925 A CN200410008925 A CN 200410008925A CN 1531076 A CN1531076 A CN 1531076A
Authority
CN
China
Prior art keywords
resin
semiconductor chip
circuit board
dielectric constant
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100089257A
Other languages
English (en)
Other versions
CN100539096C (zh
Inventor
本间壮一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1531076A publication Critical patent/CN1531076A/zh
Application granted granted Critical
Publication of CN100539096C publication Critical patent/CN100539096C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了一种半导体器件，该半导体器件包括：半导体芯片，该芯片形成有半导体元件或集成电路，在表面上形成低介电常数绝缘膜，并且以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；布线基板，该基板具有与所述凸点电极电连接的多个连接电极；以及树脂密封体，填充作为所述半导体芯片和所述布线基板之间的空间，并且填充排列了电连接的所述凸点电极和所述连接电极的该空间；其中，所述树脂密封体具有助熔剂功能，由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。

Description

半导体器件及其制造方法
本申请基于2003年3月13日提交的在先的日本专利申请No.2003-067607并要求其优先权，其全部内容在此供参考。
技术领域
本发明涉及将半导体芯片通过凸点电极倒装芯片连接在布线基板上的半导体器件及其制造方法。
背景技术
倒装芯片式半导体器件由配有外部连接端子的印刷电路板等的布线基板、在该布线基板上进行倒装芯片连接的半导体芯片、以及在半导体芯片/布线基板间填充的树脂密封体构成。图28是现有的倒装芯片式半导体器件的概略剖面图。形成装入了半导体元件或集成电路的半导体芯片100由切割硅等的半导体晶片来获得。在半导体元件或集成电路的层间绝缘等上使用氧化硅膜(SiO2)和氮化硅膜(SiN)等的绝缘膜。可是，随着半导体器件的微细化的发展，绝缘膜的介电常数的大小会产生信号延迟等的影响。因此，在目前的半导体器件中，通常至少部分使用称为Lowk膜的、介电常数低的低介电常数绝缘膜(介电常数大体为3.5以下的绝缘膜)104，在低介电常数绝缘膜104上形成SiO/SiN等的保护绝缘膜(钝化膜)105。在钝化膜105上，形成作为外部端子的布线基板103。未图示的连接电极(连接焊盘)形成在半导体芯片100表面上，布线基板103形成在该连接电极上并与该连接电极进行电连接，与未图示的半导体芯片100内部的半导体元件或集成电路进行电连接。
另一方面，在支撑半导体芯片100的印刷电路板等的布线基板101上，在半导体芯片100装载面上形成有布线(未图示)和与布线电连接的连接电极(连接焊盘)106，在连接焊盘(未图示)上连接有凸点电极103。此外，在布线基板101的另一面(背面)上通过未图示的连接焊盘来安装凸点电极102。凸点电极102用作半导体器件的外部连接端子。在半导体芯片100和布线基板101的间隙中排列凸点电极103，在该空间中填充热固化性环氧树脂等构成的树脂密封体110。
在形成该半导体器件的工序中，在布线基板101上涂敷树脂，接着，在连接焊盘106上配置凸点电极103并进行加压、加热，将两者连接的同时，形成树脂密封体110。在此时的加热处理上使用回流炉。此外，在将凸点电极102安装在布线基板101上时也使用回流炉。
作为倒装芯片连接的现有技术，有在通过热固化性树脂倒装芯片连接芯片的突起电极(凸点电极)和布线基板的焊料端子(连接焊盘)时将金属突起电极和焊料端子接合，然后使该接合凝固，随后进行热固化性树脂的固化来提高连接可靠性的技术(特开平11--233558号公报(图1至图3，4栏和5栏)。此外，有在芯片或布线基板上形成焊料凸点，通过热固化性树脂将芯片和布线基板两者对置配置，加热熔融凸点来进行两者的连接，然后将树脂固化，消除导通不良的技术(特开2001-351945号公报(图1至图3，第3页)。此外，有在电路基板上供给具有助熔剂功能的树脂，将芯片和电路基板进行定位，将凸点熔融并进行倒装芯片连接后，在高温下将树脂固化的技术(特开2002-261118号公报)。
如以上那样，在将安装凸点电极时或将半导体芯片安装在布线基板上时用回流炉等进行加热处理。此时，半导体芯片和布线基板因热而膨胀。但是，半导体芯片的热膨胀系数α为3～4ppm，布线基板的热膨胀系数α为10～17ppm，两者的差很大，因此，在加热时在树脂密封体上产生应力。现有的半导体器件由于使用硅氧化膜或氮化硅膜等粘结性高的膜，所以没有出现大问题，但如果使用在压力上易碎的低介电常数绝缘膜，这种应力对低介电常数绝缘膜的作用将引起大问题。低介电常数绝缘膜有时使用以低密度形成介电常数高的材料进行低介电常数化的绝缘膜。由于以低密度形成，所以低介电常数绝缘膜是易碎的膜。
即，在将半导体芯片倒装芯片(FC)封装在布线基板上的情况下，存在以下问题。
在半导体芯片内使用称为Lowk膜的介电常数低的材料构成的膜(低介电常数绝缘膜)时，Lowk膜的强度弱，在倒装芯片连接时在凸点电极下面产生Lowk膜的破损或剥离。
为了解决上述问题，有使布线基板的热膨胀系数接近半导体芯片的热膨胀系数的方法，但这种情况下，BGA(Ball Grid Array；焊球阵列)部分在可靠性试验时疲劳破损的概率高。
发明内容
本发明的一方面，提供一种半导体器件，该半导体器件包括：半导体芯片，该芯片形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜，并且以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；布线基板，该基板具有与所述凸点电极电连接的多个连接电极；以及树脂密封体，该密封体填充作为所述半导体芯片和所述布线基板之间的空间，并且填充排列了电连接的所述凸点电极和所述连接电极的该空间；其中，所述树脂密封体具有助熔剂功能，由在所述凸点电极和所述连接电极连接时所述凸点电极从熔融状态时的液体状态变为固体的树脂构成。
本发明的另一方面，提供一种半导体器件的制造方法，其中：在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；在所述半导体芯片和形成有多个连接电极的布线基板之间，介入具有助熔剂功能的树脂；在介入所述树脂的状态下，将所述凸点电极和所述连接电极合位并相互挤压所述半导体芯片和所述布线基板；加热所述半导体芯片和所述布线基板并将所述凸点电极和所述连接电极电连接，同时形成所述树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；所述树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
本发明的另一方面，提供一种半导体器件的制造方法，其中：在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；在所述半导体芯片和形成有多个连接电极的布线基板之间靠近所述半导体芯片介入具有助熔剂功能的第1树脂；在所述半导体芯片和形成有所述多个连接电极的布线基板之间，靠近所述布线基板介入具有助熔剂功能而不含有填料的第2树脂；在介入所述第1和第2树脂的状态下，将所述凸点电极和所述连接电极合位，并相互挤压所述半导体芯片和所述布线基板；加热所述半导体芯片和所述布线基板并将所述凸点电极和所述连接电极电连接，同时形成所述第1和第2树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；所述第1和第2树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
本发明的另一方面，提供一种半导体器件的制造方法，其中：在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；在所述半导体芯片和形成有多个连接电极的布线基板之间，靠近所述半导体芯片介入具有助熔剂功能的第1树脂；在所述半导体芯片和形成有所述多个连接电极的布线基板之间，靠近所述布线基板介入具有助熔剂功能的第2树脂；在所述第1和第2树脂之间，介入具有助熔剂功能而不含有填料的第3树脂；在介入所述第1、第2和第3树脂的状态下，将所述凸点电极和所述连接电极合位，并相互挤压所述半导体芯片和所述布线基板；加热所述半导体芯片和所述布线基板，并将所述凸点电极和所述连接电极电连接，同时形成所述第1、第2和第3树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；所述第1、第2及第3树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
在半导体芯片的对基板的倒装芯片连接中，在凸点电极从液体凝固为固体时，树脂从液态改变为固体状态，所以凸点电极受到保护，在凸点电极中不产生热应力，即使在半导体芯片中使用低介电常数绝缘膜(LowK膜)的情况下，凸点电极也不脱落，可提高半导体器件的可靠性。由于此时的树脂的弹性率在20Mpa或以上，所以可缓和对凸点电极施加的应力。
附图说明
图1是本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图2是接续图1的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图3是接续图2的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图4是接续图3的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图5是接续图4的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图6是接续图5的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图7是接续图6的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图8是接续图7的制造工序的本发明第1实施例的半导体器件的一制造工序的器件结构的剖面图。
图9是说明本发明第1实施例的进行倒装芯片连接时的回流条件的回流分布。
图10表示说明半导体芯片和布线基板的连接状态的SAT图像的图。
图11表示说明半导体芯片和布线基板的连接状态的SAT图像的图。
图12表示说明半导体芯片和布线基板的连接状态的IR图像的图。
图13表示说明半导体芯片和布线基板的连接状态的IR图像的图。
图14表示构成树脂密封体的树脂弹性率和回流分布之间关系的特性图。
图15表示半导体芯片上安装的凸点电极的另一安装结构的剖面图。
图16表示半导体芯片上安装的凸点电极的另一安装结构的剖面图。
图17表示半导体芯片上安装的凸点电极的另一安装结构的剖面图。
图18是本发明第2实施例的半导体器件的一制造工序的器件结构的剖面图。
图19是接续图18的制造工序的本发明第2实施例的半导体器件的一制造工序的器件结构的剖面图。
图20是本发明第3实施例的半导体器件的一制造工序的器件结构的剖面图。
图21是接续图20的制造工序的本发明第3实施例的半导体器件的一制造工序的器件结构的剖面图。
图22是接续图21的制造工序的本发明第3实施例的半导体器件的一制造工序的器件结构的剖面图。
图23是接续图22的制造工序的本发明第3实施例的半导体器件的一制造工序的器件结构的剖面图。
图24是本发明第4实施例的半导体器件的一制造工序的器件结构的剖面图。
图25是接续图24的制造工序的本发明第4实施例的半导体器件的一制造工序的器件结构的剖面图。
图26是接续图25的制造工序的本发明第4实施例的半导体器件的一制造工序的器件结构的剖面图。
图27表示本发明第1实施例的半导体芯片上安装的凸点电极的安装结构的剖面图。
图28是现有的倒装芯片式半导体器件的剖面图。
具体实施方式
以下，参照附图说明本发明的实施方式。
首先，参照图1至图17、图27来说明第1实施例。
图1至图8是说明从将凸点电极连接到半导体芯片上的工序至在布线基板上倒装芯片连接半导体芯片的工序的剖面图，图9是说明进行倒装芯片连接时的回流条件的回流分布图，图10、图11表示说明半导体芯片和布线基板的连接状态的SAT图像的图，图12、图13表示说明半导体芯片和布线基板的连接状态的IR图像的图，图14表示构成树脂密封体的树脂弹性率和回流分布之间关系的特性图，图27是表示半导体芯片上安装的凸点电极的安装结构的半导体芯片的剖面图，图15至图17是表示半导体芯片上安装的凸点电极的另一安装结构的半导体芯片的剖面图。
图1至图8表示本实施例的半导体器件的制造方法。准备硅等的半导体晶片W。该半导体晶片W为直径8英寸，其厚度为725μm，带有含铜(Cu)的布线(未图示)。该半导体晶片W划分成半导体芯片区域，在形成有半导体元件或集成电路107的各半导体芯片区域中形成被称为Lowk膜的低介电常数绝缘膜12(图1)。作为该Lowk膜的一例，使用SiOC膜。接着，在半导体芯片上的低介电常数绝缘膜(SiOC膜)12上形成Cu焊盘2。Cu焊盘通过未图示的含铜的布线与半导体元件或集成电路107电连接。半导体晶片W的表面例如被SiO2/SiN构成的钝化膜3覆盖，局部露出Cu焊盘2(图1)。接着，使用溅射装置、电子束镀敷装置等在该半导体晶片W的整个面上依次形成钛膜4、镍膜5、钯膜6，形成这些膜构成的阻挡金属层(图2)。接着，在阻挡金属层上以50μm左右的膜厚涂敷光致抗蚀剂7。然后，形成100μm角的开口部，以在该光致抗蚀剂7上重叠凸点电极形成用Cu焊盘。在该开口部上以50μm厚度电镀凸点电极用低熔点金属8等。
例如，共晶Sn/Pb焊料的情况下，将形成抗蚀剂图案的半导体晶片W浸入在含有以锡30g/l(升)、铅20g/l及烷基磺酸100g/l、表面活性剂为主要成分的添加剂的溶液中，在浸泡温度20℃下以所述阻挡金属层作为阴极，Sn/Pb作为阳极，在电流密度1A/dm2的条件下一边缓慢搅拌一边进行电镀(图3)。
然后，使用丙酮或公知的剥离液剥离光致抗蚀剂7，对阻挡金属层的Pd/Ni/Ti膜6、5、4进行腐蚀。在对钯膜6、镍膜5的腐蚀中使用王水系的腐蚀液。在钛膜4的腐蚀中可以使用乙二胺四醋酸系(图4)。最后，在该半导体晶片W上涂敷助熔剂，在氮气环境中220℃下加热30秒，在将焊料金属回流中形成焊料凸点(凸点电极)9(图5)。凸点电极9形成在Cu焊盘2上，与该Cu焊盘2电连接，并与内部的半导体元件或集成电路107电连接。然后对形成有焊料凸点9的半导体晶片W进行电气测试，切割芯片化，形成多个半导体芯片1(参照图6)。将该半导体芯片进行倒装芯片安装。半导体芯片1的表面被SiO2/SiN构成的钝化膜3覆盖保护。
接着，除去焊料凸点电极9表面的氧化膜，将具有助熔剂功能的树脂13适量涂敷在布线基板10的连接焊盘11上。进行基板等的布线基板10的连接焊盘11和焊料凸点9的合位，加压虚拟固定。然后，将半导体芯片1和布线基板10放入回流炉，使焊料凸点电极9和连接焊盘11连接(图7)。此时，设定条件，以使在焊料为熔融状态时树脂13从液状变为固体。作为树脂13的弹性率，在20Mpa或以上，期望在100Mpa或以上。具有助熔剂功能的树脂13在半导体芯片1和布线基板10之间构成树脂密封体14。图9中示出基于各条件的回流分布，图10、图11有关回流条件和Lowk膜剥离的比较结果。将回流条件改变为200℃(峰值)(条件A)、200℃、20秒(条件B)、200℃、60秒(条件C)、200℃、120秒(条件D)及240℃、120秒(条件E)，观察Lowk膜的剥离时，即使是图10、图11所示的SAT图像也可知在200℃(峰值)(条件A)、200℃、20秒(条件B)下可观察到剥离。此外，如图12、图13所示，用IR显微镜在焊盘下面观察相同的样本时，依然发生剥离。
相反，在200、60秒(条件C)、200℃、120秒(条件D)中，没有产生剥离(图12、图13)。这样，通过改变回流峰值时间，可改变树脂的状态，所以在观察上述条件下的树脂状态时，可知在上述条件下凸点电极为熔融状态时树脂从液态改变为固体。根据基板的弯曲来反算此时的树脂弹性时，弹性率在20Mpa或以上，可知如果弹性率为这样的值，则不发生剥离(图14)。即使将该回流后的芯片样本再进行作为后固化的150℃、2H(小时)固化，也不产生Lowk膜的剥离。
根据上述工序，来制造半导体器件，进行温度循环试验，并调查其可靠性。作为半导体芯片，使用形成有2500个凸点电极的15mm四方形的芯片，在作为布线基板的树脂基板上进行封装并制成样品。再有，温度循环试验以-55℃(30分)～25℃(5分)～125℃(30分)作为一个循环来进行。
其结果，可确认即使在1500个循环后连接部位都没有发生断裂。而且，也没有发生半导体元件内部形成的Lowk膜12的剥离。此外，进行吸湿回流评价，但既没有发生Lowk膜12的剥离，也没有发生凸点的剥离。
在将半导体芯片1倒装芯片连接在布线基板10上的半导体器件中，进一步将外部连接端子安装在布线基板10上(图8)。在本实施例中，作为外部连接端子，将焊料凸点等凸点电极15安装在布线基板10的背面。安装凸点电极15的方法与在半导体芯片1上安装焊料凸点9的情况相同。凸点电极15与未图示的布线基板10的布线电连接(图8)。
本实施例描述了作为Lowk膜使用SiOC膜的例子，但也可以将HSQ(氢倍半硅氧烷)、有机硅石(Organic-Sillica)、多孔HSQ、BCB(苯并环丁烯)等的其中之一作为材料或为它们的叠层膜，也可以是将这些材料多孔化后的膜。也可以使用在Lowk膜上叠层SiO2膜、SiN膜后的膜。
此外，具有助熔剂功能的树脂可以使用在树脂中混入助熔剂的树脂，也可以使用使固化剂具有助熔剂效果的树脂，作为其一例，可以使用酸酐。而且，也可以是在树脂中混入填料的树脂。作为树脂材料，可使用环氧树脂、丙烯酸树脂、硅树脂、聚酰亚胺树脂等。此外，作为上述金属凸点，在实施例中描述了Sn-Pb焊料的情况，但也可以是Au、Ag、Cu、Ni、Fe、Pd、Sn、Pb、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物。布线基板中形成的连接焊盘也可以是Sn、Pb、Au、Ag、Cu、Ni、Fe、Pd、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物、叠层膜。
图27详细地表示图6、图7所示的半导体芯片的凸点连接结构。Cu焊盘2形成在SiOC膜构成的低介电常数绝缘膜(介电常数低的层)12上，钝化膜3由多层的SiO2/SiN层3a、3b构成。
下面，参照图15至图17来说明在半导体芯片1上安装凸点电极的另一例子。在图15中，形成由在半导体芯片1上的低介电常数绝缘膜12上形成的低介电常数绝缘膜(SiO2/SiN)3受保护的Cu焊盘2。在其上形成低介电常数绝缘膜(SiO2/SiN)3’，在其开口部中使露出Cu焊盘2部分露出。在Cu焊盘2的露出部分、低介电常数绝缘膜3’的开口部和周边上通过阻挡金属层(TaN)(未图示)形成Al焊盘2’。作为提高Cu焊盘2和Al焊盘2’的粘结的阻挡金属层的例子，列举了TaN，但也可以是Ta、Ti、TiN等或它们的叠层膜、合金膜。在其上形成钝化膜(SiO2/SiN)3”，在其开口部中形成Al焊盘2’，以局部露出该焊盘。在Al焊盘2’的露出部分和钝化膜3”的开口部以及其周边上，通过阻挡金属层(Pd/Ni/Ti)51连接焊料凸点9。这样，可以并用Cu焊盘和Al焊盘。在本例中，低介电常数绝缘膜12由分别形成了Cu布线12a、12b的SiOC膜构成的2层的介电常数低的层构成。Cu焊盘2通过Cu布线12a、12b与含有形成于半导体芯片(Si芯片)1上的晶体管等的元件部107电连接。
图16、图17是作为钝化膜使用聚酰亚胺膜的例子。图16是图15的变形例，图17是图27的变形例。在图16中，形成由在半导体芯片1上的低介电常数绝缘膜12上形成的钝化膜(SiO2/SiN)3保护的Cu焊盘2。在其上形成钝化膜(SiO2/SiN)3’，在其开口部中使Cu焊盘2局部露出。在Cu焊盘2的露出部分、钝化膜3’的开口部和其周边上通过阻挡金属层(TaN)(未图示)形成Al焊盘2’。在其上形成钝化膜3”，在其开口部中形成Al焊盘2’，以使其局部露出。钝化膜3”由SiO/SiN膜和其上叠层的聚酰亚胺膜构成。在Cu焊盘2的露出部分、钝化膜3”的开口部和其周边上通过阻挡金属层(Pd/Ni/Ti)51连接焊料焊盘9。这样，可以并用Cu焊盘2和Al焊盘2’。在本例中，低介电常数绝缘膜12由分别形成了Cu布线(未图示)的SiOC膜构成的介电常数低的层构成。Cu焊盘2通过上述Cu布线与包含形成于半导体芯片(Si芯片)1上的晶体管等的元件部电连接。
在图17中，形成被在半导体芯片1上的低介电常数绝缘膜12上形成的钝化膜(SiO2/SiN)3保护的Cu焊盘2。在其上形成钝化膜3’，在其开口部中形成Cu焊盘2，以使其局部露出。在Cu焊盘2的露出部分、钝化膜3’的开口部和其周边上通过阻挡金属层(Pd/Ni/Ti)51形成焊料焊盘9。钝化膜3”由SiO/SiN膜和其上叠层的聚酰亚胺膜构成。
如以上那样，在对半导体芯片的基板的倒装芯片连接中，在凸点电极为熔融状态时树脂从液态变为固体，所以凸点电极受保护，在凸点电极上不发生热变形。即，使对凸点电极施加的压力得到缓和。因此，即使在半导体芯片上使用介电常数为3.5或以下的低介电常数绝缘膜(Lowk膜)的情况下，凸点电极也不剥离，半导体器件的可靠性提高。树脂的弹性率在20Mpa或以上。在图16、图17中，省略了Cu布线。
在本实施例中，作为用于凸点的阻挡金属，使用了Ti、Ni、Pd，但并不限于此，也可以是Ti、Cr、Cu、Ni、Au、Pd、TiW、W、Ta、TaN、TiN、Nb等的单层、叠层膜、合金膜。即使作为布线使用的金属布线、金属焊盘、阻挡金属相对于绝缘膜、金属膜和半导体芯片的粘结强度都在15J/m2或以下，也不产生这些金属布线、金属焊盘、阻挡金属膜的剥离。此外，不仅Lowk膜不剥离，而且还可以防止金属膜的剥离。而且，作为半导体芯片上形成的有机膜，可以使用聚酰亚胺膜和BCB膜(苯并环丁烯)等。
下面，参照图18和图19来说明第2实施例。
图18和图19是说明将连接了凸点电极的半导体芯片倒装芯片连接在布线基板上的工序的剖面图。首先，与第1实施例同样，形成半导体芯片21的凸点电极(焊料凸点(Sn-Pb焊料))23。在半导体芯片21上形成低介电常数绝缘膜22，半导体芯片21的表面被钝化膜27覆盖保护。首先，除去焊料的氧化膜，在布线基板20的连接焊盘24上适量涂敷具有助熔剂功能的树脂26。进行印刷电路板等的布线基板20的连接焊盘24和凸点电极23的合位，加压50kg、2秒来进行虚拟固定。然后，将倒装芯片连接器工具25侧加热，在3～10秒内温度上升到220℃，在220℃下保持1～20秒的时间，将焊料凸点23和布线基板22的连接焊盘24连接。然后将工具25冷却。可知此时到达焊料的熔点以下凝固时的树脂26的状态刚好是从液态变为固体时的状态。此时的弹性率在20Mpa或以上，优选在100Mpa或以上。即使将该半导体芯片试样进行150℃、2H固化，也不发生Lowk膜的剥离。
根据上述工序，来制造半导体器件，进行温度循环试验，调查其可靠性。作为半导体芯片，使用形成2500个凸点电极的15mm四方形的芯片，在树脂基板上进行封装并形成试样。再有，温度循环试验以-55℃(30分)～25℃(5分)～125℃(30分)作为一个循环来进行。
其结果，可确认即使在1500个循环后连接部位都没有发生断裂。而且，也没有发生半导体元件内部形成的Lowk膜22的剥离。此外，进行吸湿回流评价，但既没有发生Lowk膜22的剥离，也没有发生凸点的剥离。
在本实施例中，描述了作为Lowk膜使用SiOC膜的例子，但也可以是HSQ、有机硅石、多孔HSQ、BCB等的其中之一或它们的叠层膜，也可以使用将这些材料多孔化后的膜。也可以使用在Lowk膜上叠层SiO2膜、SiN膜后的膜。
此外，具有助熔剂功能的树脂可以使用在树脂中混入助熔剂的树脂，也可以使用使固化剂具有助熔剂效果的物质，作为其一例，可以使用酸酐。而且，也可以是在树脂中混入填料的物质。
此外，作为上述凸点电极，在实施例中描述了Sn-Pb焊料的情况，但也可以是Au、Ag、Cu、Ni、Fe、Pd、Sn、Pb、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物。布线基板的连接焊盘也可以是Sn、Pb、Au、Ag、Cu、Ni、Fe、Pd、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物、叠层膜。
在本实施例中，不使用回流炉而使用倒装芯片连接器来加热凸点电极和连接焊盘，可获得与第1实施例相同的效果。
如以上那样，用各实施例说明了本发明的实施方式，但本发明并不限定于实施例，包括可在不脱离本发明的精神的范围内的所有实施方式。
下面，参照图20至图23说明第3实施例。
图20至图23是表示半导体器件的制造方法的工序剖面图。首先，在硅等的半导体晶片W上形成图5或图15所示的凸点结构的凸点电极(焊料凸点)32(图20)。接着，在半导体晶片W整个面上，涂敷常温下的弹性率为20Mpa或以上的具有助熔剂功能的树脂35a。厚度为焊料凸点32高度的50％至90％左右。接着，将该半导体晶片W放入回流炉等中使焊料凸点32熔融，进一步使焊料凸点32从树脂35a上突出(图21)。此时，由于使用具有助熔剂功能的树脂，所以可使焊料焊盘32凸出。这是因为助熔剂效果有助于焊料的熔融，在表面张力下焊料焊盘32可凸出到树脂35a上。在使用普通的树脂时，难以使焊料从树脂上突起，所以使用这样的具有助熔剂功能的树脂很重要。此时，也可以在具有助熔剂功能的树脂中混合填料。如果添加填料，则热膨胀系数下降，树脂的可靠性提高。
接着，将形成了树脂35a的半导体晶片W进行切割，从半导体晶片30中切出多个半导体芯片。然后，除去布线基板33上形成的焊料的氧化膜，在布线基板33的连接电极(连接焊盘)34上适量涂敷具有助熔剂功能的树脂35b。由于在布线基板33的连接焊盘34和半导体芯片31的焊料凸点32的连接上使用无填料的树脂，所以连接良好(图22)。
接着，进行印刷电路板等的布线基板33的连接焊盘34和焊料凸点32的合位，并进行加压虚拟固定。然后，放入回流炉中，实现焊料凸点32和连接焊盘34的连接(图23)。进一步，为使树脂完全固化，使其在烤箱中干燥。
根据这样的工序，来制造半导体器件，进行温度循环试验，调查其可靠性。作为半导体芯片，使用形成2500个凸点电极的15mm四方形的芯片，在树脂基板上进行封装并形成试样。再有，温度循环试验以-55℃(30分)～25℃(5分)～125℃(30分)作为一个循环来进行。
其结果，可确认即使在1500个循环后连接部位都没有发生断裂。此外，在本实施例中，作为凸点电极，使用了Sn-Pb焊料凸点，但本发明并不限于此，也可以是Au、Ag、Cu、Ni、Fe、Pd、Sn、Pb、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物。另外，本发明的布线基板的连接焊盘也可以是Sn、Pb、Au、Ag、Cu、Ni、Fe、Pd、Bi、Zn、In、Sb、Ge等和它们的混合物、化合物、叠层膜。
以上，在本实施例中，在半导体芯片对基板的倒装芯片连接中，在凸点电极为熔融状态时，具有助熔剂功能的树脂从液状变为固体，所以凸点电极受到保护，在凸点电极上不发生热变形。因此，即使在半导体芯片中使用低介电常数绝缘膜(Lowk膜)的情况下，凸点电极也不剥离，可靠性提高。此外，在具有助熔剂功能的树脂上使用无填料树脂，所以凸点电极和连接焊盘的连接良好。
下面，参照图24至图26说明第4实施例。
图24至图26是表示半导体器件的制造方法的工序剖面图。在硅等的半导体晶片W上形成图5或图15所示的凸点结构的凸点电极(焊料凸点)。在布线基板43上形成有连接焊盘44，在其上形成有凸点电极47(图24)。与第3实施例同样，在半导体晶片上涂敷常温下的弹性率为20Mpa或以上的具有助熔剂功能的树脂45a(图25)。厚度为半导体晶片上形成的焊料凸点48高度的50％至90％左右。接着，将半导体晶片放入回流炉等中使焊料凸点熔融，进一步使焊料凸点从该树脂上突出。在本实施例中，在布线基板43上也涂敷固化快的具有助熔剂功能的树脂45c(图25)。形成厚度为布线基板43的连接焊盘44上形成的焊料凸点47的高度的50％至90％的树脂45c。将形成了该树脂45c的布线基板43放入回流炉中，使树脂45c虚拟固化。由于使用具有助熔剂的树脂，所以焊料凸点47从树脂45c中凸出。
在半导体晶片上、在布线基板上形成的树脂中也可以含有填料。通过在布线基板上形成固化快的树脂45c，水分难以从基板中排出，不产生空隙。
接着，将形成了树脂的半导体晶片进行切割，形成多个半导体芯片41。在半导体芯片41上，如上述那样，形成焊料凸点48，进而形成具有助熔剂功能的树脂45a。接着，除去布线基板43上的焊料凸点47上的氧化膜，在布线基板43的连接焊盘44和凸点电极47上适量涂敷具有助熔剂功能的树脂45b(图25)。此时，该树脂45b使用无填料树脂。在布线基板和半导体芯片的焊料凸点47、48的连接上使用不含有填料的树脂45b，所以连接良好。
接着，进行印刷电路板等的布线基板43的连接焊盘44上的焊料凸点47和半导体芯片41的焊料凸点的合位，加压并进行虚拟固定(图25)。然后，放入回流炉，实现焊料凸点之间的连接。而且，以烤箱进行干燥，以便将树脂45a、45b、45c完全固化，形成树脂密封体46(图26)。
根据上述工序，制造半导体器件，进行温度循环试验，调查其可靠性。作为半导体芯片，使用形成2500个凸点电极的15mm四方形的芯片，在树脂基板上进行封装并形成试样。再有，温度循环试验以--55℃(30分)～25℃(5分)～125℃(30分)作为一个循环来进行。
其结果，可确认即使在1500个循环后连接部位都没有发生断裂。此外，在本实施例中，使用了Sn-Pb焊料凸点，但也可以使用第3实施例中例示的材料。此外，布线基板的连接焊盘也可以使用第3实施例中例示的材料。
以上，在本实施例中，在半导体芯片对基板的倒装芯片连接中，在凸点电极为熔融状态时，具有助熔剂功能的树脂从液状变为固体，所以凸点电极受到保护，在凸点电极上不发生热变形。因此，即使在半导体芯片中使用低介电常数绝缘膜(Lowk膜)的情况下，凸点电极也不剥离，可靠性提高。此外，在具有助熔剂功能的树脂上使用无填料树脂，所以凸点电极和连接焊盘的连接良好。
如上所述，在各实施例中，在半导体芯片对基板的倒装芯片连接中，在凸点电极为熔融状态时树脂从液状变为固体，所以凸点电极受到保护，在凸点电极上不发生热变形。因此，即使在半导体芯片上使用低介电常数绝缘膜(Lowk膜)的情况下，也可以提高半导体器件的可靠性。
对于本领域技术人员来说，显然可以进行附加的改进和变更。因此，本发明的宽广范围不限于上述特定细节和代表性的实施例。因此，在不脱离权利要求书和其等同物定义的发明的基本原理的精神和范围情况下，可以进行各种变更。

Claims (23)

1.一种半导体器件，包括：
半导体芯片，该芯片形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜，并且以突出该低介电常数绝缘膜的形态在该表面上形成了多个凸点电极；
布线基板，该基板具有与所述凸点电极电连接的多个连接电极；以及
树脂密封体，填充作为所述半导体芯片和所述布线基板之间的空间，并且填充排列了电连接的所述凸点电极和所述连接电极的该空间；
所述树脂密封体具有助熔剂功能，由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
2.如权利要求1所述的半导体器件，其中所述的低介电常数绝缘膜的介电常数在3.5或以下。
3.如权利要求1所述的半导体器件，其中所述的低介电常数绝缘膜对所述的半导体芯片、绝缘膜、金属膜的任何一个的粘结强度均为15J/m2或以下。
4.如权利要求2所述的半导体器件，其中所述的低介电常数绝缘膜对所述的半导体芯片、绝缘膜、金属膜的任何一个的粘结强度均为15J/m2或以下。
5.如权利要求1所述的半导体器件，其中所述的树脂的弹性率在常温下为20Mpa或以上。
6.如权利要求1所述的半导体器件，其中所述的树脂密封体由靠近所述半导体芯片的第1树脂层和靠近所述布线基板的第2树脂层构成，所述第2树脂层是不包含填料的树脂层。
7.如权利要求1所述的半导体器件，其中所述的树脂密封体由靠近所述半导体芯片的第1树脂层、靠近所述布线基板的第2树脂层、以及介入在所述第1树脂层和所述第2树脂层之间的第3树脂层构成，所述第3树脂层是不含填料的树脂层。
8.如权利要求1所述的半导体器件，其中所述的半导体芯片的所述多个凸点电极与所述半导体芯片上形成的多个连接电极电连接，所述连接电极的至少一部分被至少一层由有机膜构成的钝化膜覆盖。
9.一种半导体器件的制造方法，其中：
在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；
在所述半导体芯片和形成有多个连接电极的布线基板之间，介入具有助熔剂功能的树脂；
在介入所述树脂的状态下，使所述凸点电极和所述连接电极合位，并相互挤压所述半导体芯片和所述布线基板；
加热所述半导体芯片和所述布线基板，使所述凸点电极和所述连接电极电连接的同时，形成所述树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；
所述树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
10.如权利要求9所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜的介电常数在3.5或以下。
11.如权利要求9所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜对所述半导体芯片、绝缘膜、金属膜的任何一个的粘结强度均为15J/m2或以下。
12.如权利要求9所述的半导体器件的制造方法，其中所述树脂的弹性率在常温下为20Mpa或以上。
13.如权利要求9所述的半导体器件的制造方法，其中加热所述半导体芯片和所述布线基板的处理在回流炉中进行，回流条件是200℃或以上、60秒或以上。
14.一种半导体器件的制造方法，其中：
在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；
在所述半导体芯片和形成多个连接电极的布线基板之间，靠近所述半导体芯片介入具有助熔剂功能的第1树脂；
在所述半导体芯片和形成所述多个连接电极的布线基板之间，靠近所述布线基板介入具有助熔剂功能而不含有填料的第2树脂；
在介入所述第1和第2树脂的状态下，将所述凸点电极和所述连接电极合位，并相互挤压所述半导体芯片和所述布线基板；
加热所述半导体芯片和所述布线基板，使所述凸点电极和所述连接电极电连接的同时，形成所述第1和第2树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；
所述第1和第2树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
15.如权利要求14所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜的介电常数在3.5或以下。
16.如权利要求14所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜对所述半导体芯片、绝缘膜、金属膜的任何一个的粘结强度均为15J/m2或以下。
17.如权利要求14所述的半导体器件的制造方法，其中所述的树脂的弹性率在常温下为20Mpa或以上。
18.如权利要求14所述的半导体器件的制造方法，其中加热所述半导体芯片和所述布线基板的处理在回流炉中进行，回流条件是200℃或以上、60秒或以上。
19.一种半导体器件的制造方法，其中：
在形成有半导体元件或集成电路，在表面上形成有低介电常数绝缘膜的半导体芯片中以突出该低介电常数绝缘膜的形态在该表面上形成多个凸点电极；
在所述半导体芯片和形成多个连接电极的布线基板之间，靠近所述半导体芯片介入具有助熔剂功能的第1树脂；
在所述半导体芯片和形成所述多个连接电极的布线基板之间，靠近所述布线基板介入具有助熔剂功能的第2树脂；
在所述第1和第2树脂之间，介入具有助熔剂功能而不含有填料的第3树脂；
在介入所述第1、第2和第3树脂的状态下，将所述凸点电极和所述连接电极合位并相互挤压所述半导体芯片和所述布线基板；
加热所述半导体芯片和所述布线基板，使所述凸点电极和所述连接电极电连接的同时，形成所述第1和第2树脂构成的树脂密封体，以填充所述半导体芯片和所述布线基板之间的间隙空间；
所述第1、第2及第3树脂由在所述凸点电极和所述连接电极连接时所述凸点电极为熔融状态时从液体状态变为固体的树脂构成。
20.如权利要求19所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜的介电常数在3.5或以下。
21.如权利要求19所述的半导体器件的制造方法，其中所述的低介电常数绝缘膜对所述半导体芯片、绝缘膜、金属膜的任何一个的粘结强度均为15J/m2或以下。
22.如权利要求19所述的半导体器件的制造方法，其中所述树脂的弹性率在常温下为20Mpa或以上。
23.如权利要求19所述的半导体器件的制造方法，其中加热所述半导体芯片和所述布线基板的处理在回流炉中进行，回流条件是200℃或以上、60秒或以上。
CNB2004100089257A 2003-03-13 2004-03-15 半导体器件及其制造方法 Expired - Fee Related CN100539096C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003067607A JP2004281491A (ja) 2003-03-13 2003-03-13 半導体装置及びその製造方法
JP067607/2003 2003-03-13

Publications (2)

Publication Number Publication Date
CN1531076A true CN1531076A (zh) 2004-09-22
CN100539096C CN100539096C (zh) 2009-09-09

Family

ID=33285164

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100089257A Expired - Fee Related CN100539096C (zh) 2003-03-13 2004-03-15 半导体器件及其制造方法

Country Status (4)

Country Link
US (1) US20040222522A1 (zh)
JP (1) JP2004281491A (zh)
CN (1) CN100539096C (zh)
TW (1) TWI237310B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7879713B2 (en) 2006-08-18 2011-02-01 Fujitsu Semiconductor Limited Mounting method of semiconductor element using outside connection projection electyrode and manufacturing method of semiconductor device using outside connection projection electrode
CN103548430A (zh) * 2011-06-02 2014-01-29 松下电器产业株式会社 电子部件安装方法、电子部件搭载装置以及电子部件安装系统

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100336426C (zh) * 2000-02-25 2007-09-05 揖斐电株式会社 多层印刷电路板以及多层印刷电路板的制造方法
KR100797422B1 (ko) 2000-09-25 2008-01-23 이비덴 가부시키가이샤 반도체소자, 반도체소자의 제조방법, 다층프린트배선판 및다층프린트배선판의 제조방법
TWI251890B (en) * 2004-11-05 2006-03-21 Advanced Semiconductor Eng Wafer structure, chip structure and bumping process
US7282433B2 (en) * 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
EP1840953A4 (en) * 2005-03-14 2011-09-21 Sumitomo Bakelite Co SEMICONDUCTOR COMPONENT
JP4097660B2 (ja) * 2005-04-06 2008-06-11 シャープ株式会社 半導体装置
JP4305430B2 (ja) * 2005-08-24 2009-07-29 ソニー株式会社 部品実装方法および部品実装体
KR101077671B1 (ko) 2006-04-20 2011-10-27 스미토모 베이클리트 컴퍼니 리미티드 반도체 장치
KR101037229B1 (ko) 2006-04-27 2011-05-25 스미토모 베이클리트 컴퍼니 리미티드 반도체 장치 및 반도체 장치의 제조 방법
JPWO2007135768A1 (ja) * 2006-05-19 2009-10-01 住友ベークライト株式会社 半導体装置
US20070267745A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
JP5061653B2 (ja) * 2007-03-01 2012-10-31 日本電気株式会社 半導体装置及びその製造方法
JP5627835B2 (ja) * 2007-11-16 2014-11-19 ローム株式会社 半導体装置および半導体装置の製造方法
JP2009245957A (ja) * 2008-03-28 2009-10-22 Panasonic Corp 半導体装置及びその製造方法
JP2010123817A (ja) * 2008-11-21 2010-06-03 Fujitsu Ltd ワイヤボンディング方法および電子装置とその製造方法
US8319339B2 (en) * 2009-07-10 2012-11-27 Stmicroelectronics (Tours) Sas Surface-mounted silicon chip
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
US8338287B2 (en) * 2010-03-24 2012-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US9224678B2 (en) * 2013-03-07 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for connecting packages onto printed circuit boards
JP5763116B2 (ja) * 2013-03-25 2015-08-12 株式会社東芝 半導体装置の製造方法
JPWO2015145533A1 (ja) * 2014-03-24 2017-04-13 パイオニア株式会社 発光装置及び発光装置の製造方法
TWI526129B (zh) 2014-11-05 2016-03-11 Elite Material Co Ltd Multilayer printed circuit boards with dimensional stability
JP6528793B2 (ja) * 2017-02-22 2019-06-12 サンケン電気株式会社 半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3296400B2 (ja) * 1995-02-01 2002-06-24 東芝マイクロエレクトロニクス株式会社 半導体装置、その製造方法およびＣｕ製リード
US5985043A (en) * 1997-07-21 1999-11-16 Miguel Albert Capote Polymerizable fluxing agents and fluxing adhesive compositions therefrom
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
WO1999004430A1 (en) * 1997-07-21 1999-01-28 Aguila Technologies, Inc. Semiconductor flip-chip package and method for the fabrication thereof
JP3119230B2 (ja) * 1998-03-03 2000-12-18 日本電気株式会社 樹脂フィルムおよびこれを用いた電子部品の接続方法
KR100643105B1 (ko) * 1998-05-06 2006-11-13 텍사스 인스트루먼츠 인코포레이티드 플립-칩 전자 디바이스를 언더필링하는 저응력 방법 및 장치
US6077726A (en) * 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
US6639321B1 (en) * 2000-10-06 2003-10-28 Lsi Logic Corporation Balanced coefficient of thermal expansion for flip chip ball grid array
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7879713B2 (en) 2006-08-18 2011-02-01 Fujitsu Semiconductor Limited Mounting method of semiconductor element using outside connection projection electyrode and manufacturing method of semiconductor device using outside connection projection electrode
CN101127314B (zh) * 2006-08-18 2012-08-15 富士通半导体股份有限公司 半导体元件的安装方法及半导体器件的制造方法
CN101562142B (zh) * 2006-08-18 2014-04-23 富士通半导体股份有限公司 半导体元件的安装方法及半导体器件的制造方法
CN103548430A (zh) * 2011-06-02 2014-01-29 松下电器产业株式会社 电子部件安装方法、电子部件搭载装置以及电子部件安装系统
CN103548430B (zh) * 2011-06-02 2016-12-28 松下知识产权经营株式会社 电子部件安装方法、电子部件搭载装置以及电子部件安装系统

Also Published As

Publication number Publication date
TWI237310B (en) 2005-08-01
US20040222522A1 (en) 2004-11-11
CN100539096C (zh) 2009-09-09
JP2004281491A (ja) 2004-10-07
TW200425277A (en) 2004-11-16

Similar Documents

Publication Publication Date Title
CN1531076A (zh) 半导体器件及其制造方法
TWI377630B (en) Semiconductor device and fabricating method thereof
KR100545008B1 (ko) 반도체소자와 그 제조방법 및 반도체장치와 그 제조방법
US9754904B2 (en) Electronic apparatus and method for manufacturing electronic apparatus
US20040177997A1 (en) Electronic apparatus
US20070284722A1 (en) Semiconductor device package utilizing proud interconnect material
US7713787B2 (en) Mounted body and method for manufacturing the same
JP2004072116A (ja) 信頼可能なプラスチック・パッケージ・アタッチメント用ポリマー埋め込みはんだバンプ
US6844052B2 (en) Method for underfilling semiconductor components
CN102017111B (zh) 无铅焊料连接构造体和焊料球
JP3334693B2 (ja) 半導体装置の製造方法
CN103098191B (zh) 电子元器件安装体、电子元器件及基板
JP2007511101A (ja) Ｌｏｗ−ｋ誘電体含有半導体デバイスと共に使用される電子パッケージング材料
JP4115306B2 (ja) 半導体装置の製造方法
EP1230676A1 (en) Advanced flip-chip join package
JP2009200067A (ja) 半導体チップおよび半導体装置
US20100167466A1 (en) Semiconductor package substrate with metal bumps
JP4185892B2 (ja) 半導体装置の製造方法
US20120241952A1 (en) Apparatuses and methods to enhance passivation and ild reliability
JPH10294337A (ja) 半導体装置及びその製造方法
JP4416876B2 (ja) 半導体チップ及び半導体チップの製造方法
JP2004047510A (ja) 電極構造体およびその形成方法
TW200415749A (en) Method of forming electrode-to-electrode connection structure and electrode-to-electrode connection structure formed thereby
JP3951903B2 (ja) 半導体装置及び半導体装置実装体の製造方法
JPH0992654A (ja) 半導体装置の電極構造体及びその形成方法並びに半導体装置の実装体及び半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20170802

Address after: Tokyo, Japan, Japan

Patentee after: Toshiba Storage Corporation

Address before: Tokyo, Japan, Japan

Patentee before: Toshiba Corp

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090909

Termination date: 20200315

CF01 Termination of patent right due to non-payment of annual fee