TW200415749A - Method of forming electrode-to-electrode connection structure and electrode-to-electrode connection structure formed thereby - Google Patents

Method of forming electrode-to-electrode connection structure and electrode-to-electrode connection structure formed thereby Download PDF

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Publication number
TW200415749A
TW200415749A TW092102681A TW92102681A TW200415749A TW 200415749 A TW200415749 A TW 200415749A TW 092102681 A TW092102681 A TW 092102681A TW 92102681 A TW92102681 A TW 92102681A TW 200415749 A TW200415749 A TW 200415749A
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Taiwan
Prior art keywords
electrode
connection structure
forming
electrode portion
connection
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TW092102681A
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Chinese (zh)
Inventor
Seiki Sakuyama
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Fujitsu Ltd
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Publication of TW200415749A publication Critical patent/TW200415749A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2924/0103—Zinc [Zn]
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/01049—Indium [In]
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The method of forming an electrode connection structure of the present invention comprises: the steps of forming an adherence layer (130) having opening parts (130a) on a first connected part (110) having first electrode parts (111) on the surface (110a) thereof, so that the first electrode parts (111) can be exposed to the opening parts (130a) and at least a part of the surface (110a) can be covered by the adherence layer (130); disposing a second connected part (120) having the second electrode parts (121) on the first connected part (110), so that the adherence layer (130) comes into contact with the second connected part (120) while the first electrode parts (111) and the second electrode parts (121) are opposed to each other; and performing a heat treatment to electrically connect the first electrode parts (111) with the second electrode parts (121) through conductor parts (140), so that the adherence layer (130) can be hardened.

Description

200415749 玖、發明說明 (發明說明應敛明：發明所属之技術領域、先前技術、内容、實施方式及圖式簡單說明） ， ^ -ϋ 】 技術領域 本發明係有關於一種電極間連接構造體之形成方法。 · ' 5更具體而言係有關於一種可應用於具有電性連接之半導體 * 晶片和半導體晶片之接合、半導體晶片與配線基板之封裝 及配線基板和配線基板之接合等的電極間連接構造體之 形成方法。 t先前1 10 背景技術 近年來，關於電子零件封裝於印刷配線板和陶瓷基板 ，咼密度化之要求正逐漸提高，就半導體晶片而言，可滿 足這種要求之方式中’裸晶片封裝方式頗受到注目。裸晶 片封裝中’傾向於採用藉由將焊凸塊或金凸塊插入半導體 15晶片及配線基板之平面電極間而達成之倒向封裝，即倒纟 接合，以取代藉絲焊法達成半導體晶片和基板配線之電性 · 連接之！知正向封裝。使用倒裝接合之封裝技術可例舉如 日本專利公開公報特開平10-229265號中所揭示者。 第5a〜5e圖顯示用以達成倒裝接合之習知方法之一例 · 。如第5a圖所示，習知之倒裝接合中，首先，在藉由於基 ； 板520a之表面形成絕緣層52〇b及電極521而獲得之半導 體晶片520的電極521上形成凸塊54〇。 之後’同樣如第5a圖所示，在表面設有電極511及配 線512之配線基板51〇之該表面上塗佈助炫劑娜。助熔 5 200415749 玖、發明說明 劑560之功能係除去凸塊540之表面之氧化膜，藉焊料回 流時阻隔大氣而防止凸塊540的再氧化’半導體晶片對配 線基板510之假接著等。 接著，如第5b圖所示，一邊進行對位，使配線基板 5 510之電極511和凸塊540對向，一邊將半導體晶片520 載置於配線基板510上。 接下來，如第5c圖所示，經過使凸塊540回流之加熱 處理後，電極511及電極521藉由凸塊540而連接。 然後，如第5d圖所示，洗淨除去助溶劑560。如此一 10 來，可達成半導體晶片520對配線基板510之倒裝接合。 此外，如第5e圖所示，此種倒裝接合中，配線基板 51〇和半導體晶片520之間充填有接著劑或填充劑530。填 充劑530係用以藉由保護連接電極511及電極521之導體 部或凸塊540，來確保經過長時間後之連接可靠性。 15 然而，如前述之習知連接方法中，當電極511之配設 間距在150//m以下時，若形成用以充分確保連接穩定性 之所需體積之凸塊540，相鄰之凸塊間互相接觸之可能性 就頗高。又，若為了迴避凸塊間之接觸而縮小凸塊540之 體積，連接後之配線基板510和半導體晶片520之隔離距 20 離便變小，尤其是若該隔離距離在50/zm以下，便會產生 如以下之不理想處。第1係可能關係到在洗淨除去塗佈於 配線基板510上之助熔劑560時，難以除去存在於微小間 隙中之助熔劑560，而殘留之助熔劑560會腐蝕等問題。 第2係在半導體晶片520封裝於配線基板510上之後，難 6 200415749 玖、發明說明 以將充填於配線基板510和半導體晶片520之間之接著劑 或填充劑530充填到微小間隙而沒有空隙等。200415749 发明 Description of the invention (the description of the invention should be made clear: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the simple description of the drawings), ^ -ϋ] TECHNICAL FIELD The present invention relates to a connection structure between electrodes Formation method. · '5 is more specifically related to an electrode connection structure which can be applied to semiconductors with electrical connections * wafer and semiconductor wafer bonding, packaging of semiconductor wafers and wiring substrates, and bonding of wiring substrates and wiring substrates, etc. The formation method. BACKGROUND In recent years, with regard to the packaging of electronic components on printed wiring boards and ceramic substrates, the requirement for densification has gradually increased. As far as semiconductor wafers are concerned, the bare chip packaging method is quite popular. Get noticed. In the bare chip package, the tendency is to use an inverted package which is achieved by inserting a solder bump or a gold bump between the semiconductor 15 chip and the plane electrode of the wiring substrate, that is, inverted bonding, instead of using a wire bonding method to achieve a semiconductor wafer. Electrical connection with the wiring of the substrate! Know the forward package. The packaging technique using flip-chip bonding can be exemplified as disclosed in Japanese Patent Laid-Open No. 10-229265. Figures 5a to 5e show an example of a conventional method for achieving flip-chip bonding. As shown in FIG. 5a, in conventional flip-chip bonding, first, bumps 54 are formed on the electrodes 521 of the semiconductor wafer 520 obtained by forming the insulating layer 52b and the electrodes 521 on the surface of the substrate 520a. After that, as shown in FIG. 5a, the surface of the wiring substrate 51o on which the electrodes 511 and the wirings 512 are provided is coated with a brightener Na. Flux 5 200415749 发明 The function of the agent 560 is to remove the oxide film on the surface of the bump 540, and to prevent the re-oxidation of the bump 540 by blocking the atmosphere when the solder flows back. Next, as shown in FIG. 5b, the semiconductor wafer 520 is placed on the wiring substrate 510 while the alignment is performed so that the electrodes 511 of the wiring substrate 5 510 and the bumps 540 face each other. Next, as shown in Fig. 5c, after the heat treatment for reflowing the bumps 540, the electrodes 511 and 521 are connected by the bumps 540. Then, as shown in FIG. 5d, the co-solvent 560 is removed by washing. In this way, flip-chip bonding of the semiconductor wafer 520 to the wiring substrate 510 can be achieved. In addition, as shown in FIG. 5e, in this flip-chip bonding, an adhesive or a filler 530 is filled between the wiring substrate 51 and the semiconductor wafer 520. The filler 530 is used to protect the conductive portions or the bumps 540 of the connection electrodes 511 and 521 to ensure connection reliability after a long period of time. 15 However, as in the conventional connection method described above, when the arrangement pitch of the electrodes 511 is below 150 // m, if a bump 540 of a required volume to sufficiently ensure the stability of the connection is formed, the adjacent bumps The possibility of contact between them is quite high. In addition, if the volume of the bump 540 is reduced in order to avoid contact between the bumps, the separation distance 20 between the connected wiring substrate 510 and the semiconductor wafer 520 becomes smaller, especially if the separation distance is 50 / zm or less. The following disadvantages occur. The first system may be related to problems such as that when the flux 560 coated on the wiring substrate 510 is cleaned and removed, it is difficult to remove the flux 560 existing in the minute gap, and the remaining flux 560 may corrode. The second series is difficult after the semiconductor wafer 520 is packaged on the wiring substrate 510. 200415749 玖, description of the invention is to fill the micro gap with the adhesive or filler 530 filled between the wiring substrate 510 and the semiconductor wafer 520 without voids, etc. .

因此，有一種可消除如前述之不理想處之技術，其係 將以熱硬化性環氧樹脂為主成分之接著劑預先塗佈至配線 5 基板上之必要處後，藉由Au凸塊將配線基板之電極和半 導體晶片之電極熱壓接而藉此連接，同時利用接著劑接著 接合配線基板和半導體晶片。此種技術可例舉如日本專利 公開公報特開2000-286297號中所揭示者。 然而，日本專利公開公報特開2000-286297號中所揭 10 示之技術中，接著劑介於凸塊和電極之間，恐有連接部之 電阻增大之虞。特別是因為於接著劑所添加之用以緩和半 導體晶片和配線基板之熱膨脹收縮差的Si〇2等無機填料就 介於凸塊和電極之間，故引起連接不良之可能性很高。 因此，有一種可消除如前述之不理想處之技術，其係 15 將在形成於半導體晶片之端子上之凸塊及多層配線基板上 之墊的位置具有貫通孔之填充樹脂片插入半導體晶片和多 層配線基板之間，藉此可一邊達成凸塊-墊之間之電性導通 ，一邊接合半導體晶片和多層配線基板的技術。此種技術 可例舉如曰本專利公開公報特開2001-24029號中所揭示者 20 。又，於用以覆蓋印刷配線基板上之導體電路的絕緣樹脂 形成開口部而使導體電路由該開口部露出後，一邊達成具 有凸塊之半導體晶片之該凸塊和導體電路的電性導通，一 邊接合半導體晶片和印刷配線基板的技術可例舉如日本專 利公開公報特開2001-156203號中所揭示者。 7 200415749 玖、發明說明 然而，日本專利公開公報特開2001-24029號中所揭示 之技術中，雖然可達成多層配線基板和半導體晶片之間的 密封，但是卻不能充分達成多層配線基板之凸塊露出之面 之半導體晶片搭載區域外所形成之配線和基板的保護。又 5 ’為了充分保護該配線和基板’須於半導體晶片搭載區域 外，另外形成保護層，作業效率並不理想。另，日本專利 公開公報特開2001-156203號中所揭示之技術亦可說是同 樣的情況。 I：發明内容3 10 發明揭示 因此，本發明之目的在於提供一種電極間連接構造體 之形成方法，係當電性連接具有電極部之基板時，可將該 等基板間密封，同時保護基板本身和配線者。 本發明之另一目的在於提供以此種形成方法所製成之 15 電極間連接構造體。 依據本發明之第1方面，可提供一種電極間連接構造 體之形成方法。該形成方法包含有： 對表面具有第1電極部之第1連接對象物，形成具有 開口部之接著層，使該第1電極部由該開口部露出，且大 20 致覆蓋該表面全體的步驟； 對該第1連接對象物，將具有第2電極部之第2連接 對象物配置成該第1電極部和該第2電極部對向，且該接 著層與該第2連接對象物相接的步驟；及 進行加熱處理，使該第1電極部及該第2電極部藉由 8 200415749 玖、發明說明 導體部而電性連接，同時該接著層硬化的連接步驟。Therefore, there is a technology that can eliminate the above-mentioned unsatisfactory points. After applying an adhesive with a thermosetting epoxy resin as the main component to the necessary parts of the wiring board in advance, it is applied by Au bumps. The electrodes of the wiring substrate and the electrodes of the semiconductor wafer are connected by thermocompression bonding. At the same time, the wiring substrate and the semiconductor wafer are bonded with an adhesive. Such a technique can be exemplified as disclosed in Japanese Patent Laid-Open Publication No. 2000-286297. However, in the technique disclosed in Japanese Patent Laid-Open No. 2000-286297, the adhesive is interposed between the bump and the electrode, and there is a fear that the resistance of the connection portion may increase. In particular, an inorganic filler such as SiO2, which is added to the adhesive to reduce the difference in thermal expansion and contraction between the semiconductor wafer and the wiring substrate, is located between the bump and the electrode, so the possibility of causing poor connection is high. Therefore, there is a technology that can eliminate the above-mentioned disadvantages. It inserts a semiconductor chip and a filled resin sheet having through holes at the positions of bumps formed on the terminals of the semiconductor wafer and pads on the multilayer wiring substrate. This is a technology for bonding semiconductor wafers and multilayer wiring substrates while achieving electrical conduction between bumps and pads between the multilayer wiring substrates. Such a technique can be exemplified as disclosed in Japanese Patent Laid-Open No. 2001-24029. In addition, after an opening is formed in an insulating resin for covering a conductor circuit on a printed wiring board, and the conductor circuit is exposed through the opening, electrical conduction between the bump and the conductor circuit of the semiconductor wafer having the bump is achieved, As a technique for joining the semiconductor wafer and the printed wiring board on one side, for example, as disclosed in Japanese Patent Laid-Open Publication No. 2001-156203. 7 200415749 发明 Description of the Invention However, in the technology disclosed in Japanese Patent Laid-Open Publication No. 2001-24029, although the sealing between the multilayer wiring substrate and the semiconductor wafer can be achieved, the bumps of the multilayer wiring substrate cannot be fully achieved. Protection of wiring and substrates formed outside the exposed area of the semiconductor wafer mounting area. In addition, in order to fully protect the wiring and the substrate, it is necessary to form a protective layer outside the semiconductor wafer mounting area, and the work efficiency is not satisfactory. The same can be said of the technique disclosed in Japanese Patent Laid-Open No. 2001-156203. I: Summary of the Invention 3 10 Disclosure of the Invention Therefore, the object of the present invention is to provide a method for forming an electrode connection structure. When electrically connecting substrates having electrode portions, the substrates can be sealed between the substrates while protecting the substrate itself. And wiring. Another object of the present invention is to provide a 15-electrode connection structure manufactured by such a forming method. According to the first aspect of the present invention, a method for forming a connection structure between electrodes can be provided. The forming method includes the steps of forming a first connection object having a first electrode portion on a surface, forming a bonding layer having an opening portion, exposing the first electrode portion through the opening portion, and covering the entire surface by a large amount. ; For the first connection object, a second connection object having a second electrode portion is arranged so that the first electrode portion and the second electrode portion face each other, and the bonding layer is in contact with the second connection object And a step of performing a heat treatment so that the first electrode portion and the second electrode portion are electrically connected to each other through 8 200415749 2004, the conductor portion of the invention description, and the bonding layer is hardened.

此種電極間連接構造體之形成方法中，使大致覆蓋第 1連接對象物之表面全體之接著層硬化，藉此可將第1連 接對象物和第2連接對象物之間密封，同時第2連接對象 5 物之搭載區域外之配線和第1連接對象物本身亦可獲得保 護。因此，由於不須另外形成用以保護配線和第1連接對 象物本身之保護層，故可提高作業效率。 又，在使接著層與第1及第2連接對象物接觸之狀態 中，令該接著層硬化，藉由硬化時產生之收縮而可相互地 10 壓擠第1及第2電極部。因此，第1及第2電極部之電性 連接更好，可再提高第1連接對象物和第2連接對象物之 連接可靠性。In such a method for forming an inter-electrode connection structure, a bonding layer covering substantially the entire surface of the first connection object is hardened, thereby sealing the first connection object and the second connection object, and simultaneously the second The wiring outside the mounting area of the connected object 5 and the first connected object itself can also be protected. Therefore, it is not necessary to separately form a protective layer for protecting the wiring and the first connection object itself, so that work efficiency can be improved. Further, in a state where the adhesive layer is in contact with the first and second connection objects, the adhesive layer is hardened, and the first and second electrode portions can be pressed against each other by shrinkage generated during curing. Therefore, the electrical connection between the first and second electrode portions is better, and the connection reliability between the first connection object and the second connection object can be further improved.

更進一步，於接著層設置開口部，且防止一部份之接 著層介於第1電極部和第2電極部之間，藉此亦可抑制導 15 體電阻增大。 再者，前述接著層宜係使用具有感光性之材料而形成 者。此時，可採用微影成像法形成開口部。 又，前述接著層宜含有無機填料。藉由含有無機填料 ，可適當地降低接著層之熱膨脹率。 20 本發明之實施形態中，前述導體部係預先形成於前述 第1電極部或前述第2電極部其中一方之金屬凸塊，而前 述第1電極部和前述第2電極部之電性連接係藉由該凸塊 而進行。藉此，前述第1電極部和第2電極部可適當地導 通。該凸塊宜係熔點為80〜400°C之金屬或合金。又，該凸 9 200415749 玖、發明說明 塊宜係由-素材所構成，而該素材係選自於由LΜ 、（:U、In、Α卜Au、Bi、Ζη及Sb所構成之群組者。 本發明之另一實施形態中，更包含有於前述開口部充 填含金屬之金屬糊的充填步驟’而前述導體部係藉該金屬 * 5糊固化而形成者。藉由依此形成之導體部，前述第工電極 . 部和弟2電極部亦可適當地導通。 又，前述金屬糊宜含有樹脂成分，且在前述連接步驟 中’使該樹脂成分硬化。 亦可在前述充填步驟之前，於前述接著層上設置對應 10前述開口部而開口之遮罩，且在前述充填步驟中，藉由該 遮罩而於前述接著層之開口部充填前述金屬糊。 本發明之再另-實施形態中，前述導 或無電極電鐘而形成者。藉此，前述^電極部=及電 極部可適當地導通。此時，前述導體部亦可具有由多數之 15層所構成之積層構造，且各層具有與相鄰之層不同之金屬 組成。 依據本發明之第2方面，可提供一種電極間連接對象 物。該電極間連接對象物包含有： 表面具有第1電極部之第1連接對象物； 2〇 咖該第1電極部對向之第2電極部的第2連接對 * 象物； > 用以連接該第i電極部和該第2電極部的導 ，用士以充填該第1連接對象物和該第2連接對象物之間 ，同時大致覆蓋前述表面全體的接著層。 10 200415749 玖、發明說明 · 此種構造之電極間連接構造體係可藉本發明之第ι方 2之方法而«者。因此，其形成過封，亦可發揮與如 前關於第1方面所述者同樣之效果。 本發明之其他目的、特徵和優點，可由以下依附加圖 · 5示所說明之適當實施形態而更加清楚明瞭。 · 圖式簡單說明 第la〜If圖係顯示利用本發明第i實施形態之電極間 連接構造體形成方法之娜接合之_連串㈣的概略截自 · 圖。 10 第2a〜2f圖係顯示利用本發明第2實施形態之電極間 連接構造體形成方法之倒裝接合之一連串步驟的概略截面 圖。 第3a~3f圖係顯不利用本發明第3實施形態之電極間 連接構造體形成方法之倒裝接合之一連串步驟的概略截面 15 圖。 第4圖係藉連接半導體晶片而獲得之電極間連接構造 φ 體的概略截面圖。 第5a~5e圖係顯示利用習知電極間連接構造體形成方 法之倒裝接合之一連串步驟的概略截面圖。 20 【實施方式】 用以實施發明之最佳形態 第la〜If圖顯示本發明第丨實施形態之電極間連接構 造體形成方法的一連串步驟。本實施形態中係舉倒裝接合 為例來加以說明。 11 200415749 玖、發明說明 首先，如第la圖所示，對表面_設有電極⑴及 配線112之配線基板110，積層形成接著層13〇，俾覆蓋電 極111及配線U2。形成接著層130 t，係載置膜狀樹脂 、、且成物，使其大致覆蓋配線基板11〇之表面li〇a之全體之 5後，一邊以5〇〜14〇°C加熱一邊壓接。或者，亦可藉旋轉塗 布等，塗佈液狀樹脂組成物，俾大致覆蓋配線基板ιι〇之 表面110a之全體，且使其乾燥。 用以形成接著層130之樹脂組成物係在作為主劑之熱 硬化性樹脂中適當地添加硬化劑和無機填料等而作成者。 10該樹脂組成物可預先成形為膜狀，亦可以液狀之狀態塗佈 於配線基板110形成薄膜狀。接著層13〇之厚度係依據配 線基板110之電極間距、電極尺寸及接合可靠性等觀點而 決定。 為熱硬化性樹脂之主劑宜係環氧樹脂。環氧樹脂可使 15用固形種類或液狀種類之雙酚A型環氧樹脂、雙酚F型環 氧樹脂、萘型環氧樹脂、溴化環氧樹脂、苯酚酚醛清漆型 環氧樹脂、甲酚酚醛清漆型環氧樹脂、聯苯型環氧樹脂等 〇 前述硬化劑可使用咪唑系硬化劑、酸酐硬化劑、胺系 2〇硬化劑、苯酚系硬化劑等。咪唑系硬化劑可使用2-笨基一‘ 甲基咪唑、2-十一烷基咪唑、2,4_二胺基<·〔2一甲基咪唑_ (1)〕-乙基-S-三氮啡、丨-氰乙基-2_乙基_4_甲基咪唑、卜 氰乙基-2-十一烷基咪唑、2-苯基-4-曱基-5-羥甲基咪唑、孓 苯基-4,5-二羥甲基咪唑等。酸酐硬化劑可使用酞酐、順丁 12 200415749 玖、發明說明 烯二酸酐、四氫酞酐、六氫酞酐、甲基四氫酞酐、甲基六 氫酞酐、無水/、彳酸（商品名，正式名稱為内伸甲 基四氫酞酐（endomethylene tetrahydrophthalic anhydrate)) 、四〉臭酞酐、偏苯三酸肝、苯均四酸肝、二苯基嗣四幾酸 5 酐等。胺系硬化劑可使用二伸乙三胺、三伸乙四胺、蓋稀 薄荷稀二胺、異佛爾酮二胺、間二甲苯二胺、二胺基二苯 基甲烷、間苯二胺、二胺基二苯颯等。 前述無機填料可使用氧化矽粉末和氧化鋁粉末。用以 形成接著層130之清漆中，宜令無機填料之含有率為 10 30〜70wt%。 若欲於接著層130賦與感光性時，可對用以形成該接 著層130之樹脂組成物添加丙烯基單體及光聚合起始劑。 丙烯基單體可使用異丁基丙稀酸酯、t_丁基丙稀酸酯、丨，6_ 己烷二醇丙烯酸酯、月桂基丙烯酸酯、烷基丙烯酸酯、鯨 15 堰基丙烯酸酯、硬脂醯基丙烯酸酯、環己基丙烯酸酯、異 福基丙烯酸酯、苄基丙烯酸酯、2-曱氧乙基丙烯酸酯、3-甲氧丁基丙烯酸酯、伸乙基卡必醇丙烯酸酯、苯氧乙基丙 烯酸酯、四氫吱喃甲基丙烯酸酯、苯氧基聚乙烯丙烯酸酯 甲氧基二伸丙基乙—醉丙婦酸S旨、2 -經乙基丙婦酸醋、 20 羥基丙基丙烯酸酯、2-丙烯醯基氧基乙基羥基丙基酞 酸酯、2-經基-3=苯氧基丙基丙烯酸酯、2-丙稀酸基經乙基 氫酞酸酯、環己烷-1，2-二羧酸單-(2-丙烯醯基氧基-1-甲 基-乙基）酯、4-環己烯-l，2-二羧酸單-(2-丙烯醯基氧基-甲基-乙基）酯、二曱胺基乙基丙烯酸酯、三氟基乙基丙 13 200415749 玖、發明說明 稀酸醋、六氟基丙基丙婦酸酯等單功能單體，和i木丁烧 二醇二丙烯酸酯、K己烷二醇二丙烯酸酯、1，9-壬烷二醇 二丙烯酸酯、新戊基乙二醇二丙烯酸酯、四伸乙甘醇二丙 烯酸醋、二伸丙基乙二醇二丙婦酸醋、雙齡Α，Ε〇附加& · 5二丙烯酸酯、甘油甲基丙烯酸酯丙烯酸酯等2功能單體， . 以及二羥甲基丙烷三丙烯酸酯、三甲基丙烷Ε〇附加三丙 烯酸酯、季戊四醇三丙烯酸酯、三羥甲基丙烷Ε〇附加物 二丙烯酸酯、甘油ΡΟ附加物三丙烯酸酯、三丙烯醯基氧 · 基乙基磷酸酯、季戊四醇四丙烯酸酯等多功能單體等。不 10過，亦可使用雙酚Α-二環氧基-丙烯酸附加物等低聚合物 來取代丙烯基單體，或同時使用兩者。用以形成接著層 130之樹脂組成物中，丙烯基單體之含有率宜為uow% 〇 又’前述光聚合起始劑可使用2,2-二甲氧基-1，2-二苯 15 基乙烷-1-酮、1-羥基-環己基-苯基-酮、2-甲基-1-〔 4-(甲 硫基）苯基〕-2-嗎福琳基丙烧_ι_嗣、2-苄基-2-二甲基胺 鲁 基-1- ( 4_嗎福琳基苯基）-丁烧_ι_酮、2-經基_2-甲基-1-苯 基-丙烷-1-酮、1-〔4- (2-羥基乙氧基）_苯基〕_2-羥基-2_ 曱基-1-丙烷-1-酮、雙（7/ 5-2,4-環戊二烯-1-基）_雙（2,心 20 二氟基-3- ( 1H-11比洛-1-基）-苯基）鈦等。用以形成接著層 130之樹脂組成物中，光聚合起始劑之含有率宜為 0.1 〜15wt%。 另，更可於用以形成接著層130之樹脂組成物中添加 聚酯樹脂和丙烯酸樹脂等熱塑性樹脂。 14 200415749 玖、發明說明 如第lb圖所示，形成接著層130之後，對接著層13〇 / ，在與各電極111對應之處形成開口部13〇a。形成開口部 13〇a時，可使用UV_YAG雷射、二氧化碳雷射、激生分子 雷射等。若是形成具有感光性之接著層13〇，則欲形成開 -- 5 口。卩13〇a時，可採用微影成像法。從可抑制對電極之損傷 · 的觀點來看，宜採用微影成像法。採用微影成像法時，係 對接著層130’進行隔著預定光罩（圖中未顯示）之曝光 處理及其後之顯像處理，藉此形成開口部1，使各電極 鲁 路出。另，若使用預先成形之樹脂膜形成接著層13〇， 10亦可在將接著層130載置於配線基板110之表面UOa之前 ’預先於預定位置形成開口部13〇a。 接著，如第lc圖所示，在較配線基板11()之表面 UOa之面積更小的封裝面積之表面具有電極121的半導體 晶片120中，於該電極121形成金屬凸塊14〇。在此，半 15導體晶片120係於基板120a之表面形成有絕緣層120b及 電極121者。形成金屬凸塊14〇時，可使用蒸鍍法、鍍敷 Φ 法、塗糊式印刷法、球形黏著法等公知方法來進行。金屬 凸塊140之組成可係選自於Sn、Pb、Ag、Cu、In、八卜Furthermore, an opening is provided in the adhesive layer, and a part of the adhesive layer is prevented from being interposed between the first electrode portion and the second electrode portion, thereby suppressing an increase in the bulk resistance. The adhesive layer is preferably formed using a photosensitive material. In this case, the lithography can be used to form the opening. The adhesive layer preferably contains an inorganic filler. By containing an inorganic filler, the thermal expansion coefficient of the adhesive layer can be appropriately reduced. 20 In an embodiment of the present invention, the conductor portion is a metal bump formed in advance on one of the first electrode portion or the second electrode portion, and the electrical connection system between the first electrode portion and the second electrode portion is This is performed by the bump. Thereby, the first electrode portion and the second electrode portion can be properly conducted. The bump is preferably a metal or alloy with a melting point of 80 ~ 400 ° C. Also, the convex 9 200415749, the invention description block should be composed of-material, and the material is selected from the group consisting of LM, (: U, In, A, Au, Bi, Zη, and Sb In another embodiment of the present invention, a filling step of filling a metal-containing metal paste in the opening portion is further included, and the conductor portion is formed by curing the metal * 5 paste. The conductor portion is formed by this. The aforementioned electrode section and the second electrode section can also be properly conducted. In addition, the metal paste should preferably contain a resin component, and the resin component should be 'hardened' in the aforementioned connecting step. Alternatively, the aforementioned filling step may be performed before the filling step. A mask which is opened corresponding to the aforementioned 10 openings is provided on the adhesive layer, and in the filling step, the metallic paste is filled in the openings of the adhesive layer with the mask. Yet another embodiment of the present invention The above-mentioned conductive or electrodeless electric clock is formed. By this, the ^ electrode portion = and the electrode portion can be properly conducted. At this time, the conductor portion may have a multilayer structure composed of a plurality of 15 layers, and each layer With phase The adjacent layers are composed of different metals. According to the second aspect of the present invention, an object for connection between electrodes can be provided. The object for connection between electrodes includes: a first connection object having a first electrode portion on the surface; The second connection object * of the first electrode portion facing the second electrode portion; > A guide for connecting the i-th electrode portion and the second electrode portion, and filling the first connection object with a nail And the second connection object, covering the entire surface of the bonding layer at the same time. 10 200415749 发明 、 Explanation of the invention · The electrode connection structure system of this structure can be obtained by the method of the second aspect of the present invention. Therefore, it can be over-sealed and can exert the same effect as that described in the first aspect. Other objects, features, and advantages of the present invention can be achieved by the following suitable embodiments as shown in the attached FIG. 5 It is more clear and clear. Schematic illustrations from la to If are diagrams showing the outline of na-joint _ tandem ㈣ using the method of forming an inter-electrode connection structure of the i-th embodiment of the present invention. Fig. 10 2a ~ 2f picture display A schematic cross-sectional view of a series of steps of flip-chip bonding using the method for forming an inter-electrode connection structure according to the second embodiment of the present invention. Figures 3a to 3f show the method for forming the inter-electrode connection structure without using the third embodiment of the present invention. Fig. 15 is a schematic cross-sectional view of a series of steps of flip-chip bonding. Fig. 4 is a schematic cross-sectional view of an electrode connection structure φ body obtained by connecting a semiconductor wafer. Figs. 5a to 5e show a conventional electrode connection structure A schematic cross-sectional view of a series of steps of flip-chip bonding of the forming method. [Embodiment] The best mode for implementing the invention The la to If diagrams show a series of steps of the method for forming an inter-electrode connection structure according to the first embodiment of the present invention. In this embodiment, a description will be given by taking a flip joint as an example. 11 200415749 发明 Description of the invention First, as shown in FIG. 1a, a wiring substrate 110 provided with electrodes ⑴ and wirings 112 is laminated on the surface to form an adhesive layer 13, which covers electrodes 111 and wirings U2. After forming an adhesive layer 130 t, a film-like resin was placed on the substrate so as to substantially cover 5 of the entire surface lia of the wiring substrate 11o, and then the pressure bonding was performed while heating at 50 to 14 ° C. . Alternatively, the liquid resin composition may be applied by spin coating or the like, so that the entire surface 110a of the wiring substrate ι0 is substantially covered and dried. The resin composition for forming the adhesive layer 130 is prepared by appropriately adding a hardener, an inorganic filler, and the like to a thermosetting resin as a main agent. The resin composition may be formed into a film shape in advance, or may be applied to the wiring substrate 110 in a liquid state to form a thin film. The thickness of the bonding layer 130 is determined based on the electrode pitch, electrode size, and bonding reliability of the wiring substrate 110. The main agent of the thermosetting resin is preferably an epoxy resin. The epoxy resin can be used in 15 types of solid or liquid bisphenol A epoxy resin, bisphenol F epoxy resin, naphthalene epoxy resin, brominated epoxy resin, phenol novolac epoxy resin, Cresol novolac-type epoxy resin, biphenyl-type epoxy resin, and the like. As the curing agent, an imidazole-based curing agent, an acid anhydride curing agent, an amine-based 20 curing agent, a phenol-based curing agent, and the like can be used. As the imidazole-based hardener, 2-benzyl-'methylimidazole, 2-undecylimidazole, 2,4-diamino group < · [2-methylimidazole_ (1)]-ethyl-S -Triazine, 丨 -cyanoethyl-2_ethyl_4-methylimidazole, cyanoethyl-2-undecylimidazole, 2-phenyl-4-fluorenyl-5-hydroxymethyl Imidazole, fluorenyl-4,5-dimethylol imidazole and the like. The acid anhydride hardener can use phthalic anhydride, cis butadiene 12 200415749 玖, description of the invention oxalic anhydride, tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, anhydrous /, acetic acid ( Trade name, formal name is endomethylene tetrahydrophthalic anhydride), 4> phthalic anhydride, trimellitic acid liver, pyromellitic acid liver, diphenyl sulfonic acid tetrahydrophthalic anhydride, etc. As the amine hardener, diethylene glycol triamine, triethylene glycol tetraamine, dilute mint diamine, isophorone diamine, m-xylylene diamine, diaminodiphenylmethane, m-phenylenediamine can be used. , Diaminodiphenylhydrazone and the like. As the inorganic filler, silica powder and alumina powder can be used. In the varnish used to form the adhesive layer 130, the content of the inorganic filler should preferably be 10 to 30 to 70% by weight. In order to impart photosensitivity to the adhesive layer 130, a propylene-based monomer and a photopolymerization initiator may be added to the resin composition for forming the adhesive layer 130. As the propylene-based monomer, isobutyl acrylate, t-butyl acrylate, 6-hexanediol acrylate, lauryl acrylate, alkyl acrylate, whale 15 weir acrylate, Stearyl methacrylate, cyclohexyl acrylate, isophoryl acrylate, benzyl acrylate, 2-oxoethyl acrylate, 3-methoxybutyl acrylate, ethyl carbitol acrylate, Phenoxyethyl acrylate, tetrahydrocrylic methacrylate, phenoxypolyethylene acrylate methoxydipropane-ethyl-propionate, 2-ethylpropionate, 20 Hydroxypropyl acrylate, 2-propenyloxyethyl hydroxypropyl phthalate, 2-mercapto-3 = phenoxypropyl acrylate, 2-propionate via ethylhydrophthalate , Cyclohexane-1,2-dicarboxylic acid mono- (2-propenyloxy-1-methyl-ethyl) ester, 4-cyclohexene-1,2-dicarboxylic acid mono- (2 -Propenyloxy-methyl-ethyl) ester, diamidoethyl acrylate, trifluoroethylpropane 13 200415749, description of the invention, dilute vinegar, hexafluoropropylpropionate, etc. Monofunctional monomer, and i wood Burned glycol diacrylate, Khexanediol diacrylate, 1,9-nonanediol diacrylate, neopentyl glycol diacrylate, tetraethylene glycol diacrylate, dipropylene glycol 2-functional monomers, such as diethylene glycol dipropionate, double age A, E 0 addition & 5 diacrylate, glycerol methacrylate, etc .; and dimethylolpropane triacrylate, three Methylpropane E0 added triacrylate, pentaerythritol triacrylate, trimethylolpropane E0 added diacrylate, glycerol P0 added triacrylate, tripropenyloxy · ethylethyl phosphate, pentaerythritol tetra Multifunctional monomers such as acrylate. In addition, it is also possible to use oligomers such as bisphenol A-diepoxy-acryl addition to replace the propylene-based monomer, or use both. In the resin composition used to form the adhesive layer 130, the content rate of the propylene-based monomer should preferably be uow%. Also, the aforementioned photopolymerization initiator can use 2,2-dimethoxy-1,2-diphenyl 15 Ethane-1-one, 1-hydroxy-cyclohexyl-phenyl-one, 2-methyl-1- [4- (methylthio) phenyl] -2-morpholinyl Hydrazone, 2-benzyl-2-dimethylamine rudi-1- (4-morpholinylphenyl) -butanyl-1, 2-keto-2-methyl-1-phenyl -Propane-1-one, 1- [4- (2-hydroxyethoxy) _phenyl] _2-hydroxy-2_fluorenyl-1-propane-1-one, bis (7 / 5-2,4- Cyclopentadien-1-yl) -bis (2,2-difluoro-3- (1H-11bilo-1-yl) -phenyl) titanium and the like. The content of the photopolymerization initiator in the resin composition used to form the adhesive layer 130 is preferably 0.1 to 15% by weight. Further, a thermoplastic resin such as a polyester resin and an acrylic resin may be added to the resin composition for forming the adhesive layer 130. 14 200415749 (ii) Description of the invention As shown in FIG. 1b, after the bonding layer 130 is formed, an opening portion 13a is formed on the bonding layer 13o / at a position corresponding to each electrode 111. When forming the opening 13a, a UV_YAG laser, a carbon dioxide laser, an excimer laser, or the like can be used. If the photosensitive adhesive layer 13 is formed, it is desired to form an opening-5 openings. For 卩 130a, lithography can be used. From the viewpoint of suppressing damage to the counter electrode, a lithography method is preferably used. When the lithography method is used, the adhesive layer 130 'is subjected to an exposure process through a predetermined mask (not shown in the figure) and a subsequent development process, thereby forming the opening portion 1 so that each electrode is routed out. In addition, if the adhesive layer 13 is formed using a resin film formed in advance, the opening portion 13a may be formed in a predetermined position before the adhesive layer 130 is placed on the surface UOa of the wiring substrate 110 '. Next, as shown in FIG. 1c, in a semiconductor wafer 120 having an electrode 121 on a surface having a smaller package area than the surface UOa of the wiring substrate 11 (), a metal bump 14 is formed on the electrode 121. Here, the semi-conductor wafer 120 is formed by forming an insulating layer 120b and an electrode 121 on the surface of the substrate 120a. When the metal bumps 140 are formed, known methods such as a vapor deposition method, a plating Φ method, a paste printing method, and a spherical adhesion method can be used. The composition of the metal bump 140 may be selected from the group consisting of Sn, Pb, Ag, Cu, In, and

Au、Bi、Zn及Sb等之單體金屬，或者可係由選自於由該 20等金屬之多數單體金屬所構成的合金等。其中，為了減小 / 電極間之導通電阻，尤宜使用熔點為8〇〜4〇〇cc之金屬，該 金屬可例舉如Sn-Ag合金、Sn_Ag_Cu合金、Sn-Pb合金、The individual metals such as Au, Bi, Zn, and Sb may be an alloy composed of a plurality of individual metals selected from the metals such as 20 and the like. Among them, in order to reduce the on-resistance between the electrodes, it is particularly suitable to use a metal having a melting point of 80 to 400 cc. Examples of the metal include Sn-Ag alloy, Sn_Ag_Cu alloy, Sn-Pb alloy,

Sn-Zn合金、Sn-Bi合金等。若藉此種較低熔點之金屬形成 金屬凸塊140，後述之步驟中，便可將用以使接著層13〇 200415749 玖、發明說明 硬化之温度設定成比較低溫。因此，亦可在最終獲得之連 接構造體中，抑制因配線基板110及半導體晶片120之熱 膨脹差而產生之影響，例如由於配線基板110或半導體晶 片120之翹曲等所導致之連接部的形成不良。另，可令金 5 屬凸塊140形成於電極111側，亦可令其形成於電極111 及電極121兩側。Sn-Zn alloy, Sn-Bi alloy, etc. If the metal bump 140 is formed from this kind of metal with a lower melting point, the temperature for hardening the adhesive layer 130 200415749 发明, description of the invention can be set to a relatively low temperature in the steps described later. Therefore, in the finally obtained connection structure, it is also possible to suppress the influence caused by the difference in thermal expansion between the wiring substrate 110 and the semiconductor wafer 120, such as the formation of the connection portion due to the warpage of the wiring substrate 110 or the semiconductor wafer 120 bad. In addition, the metallic bump 140 may be formed on the electrode 111 side, or it may be formed on both sides of the electrode 111 and the electrode 121.

接下來，如第Id圖所示，在接著層130之開口部 130a中，進行對位，使金屬凸塊140和配線基板110之電 極111對向後，將半導體晶片120搭載於配線基板上。 10 然後，如第le圖所示，一邊增加負載f，一邊以金屬 凸塊140之熔點以上之溫度（例如250°C )瞬間地加熱， 藉此接合配線基板110和半導體晶片120。在此，「瞬間地 」係指為了減輕對於半導體晶片120之熱負荷而在短時間 内進行加熱，例如約1~30秒的時間。因此，金屬凸塊140Next, as shown in FIG. Id, the opening 130a of the bonding layer 130 is aligned so that the metal bump 140 and the electrode 111 of the wiring substrate 110 face each other, and the semiconductor wafer 120 is mounted on the wiring substrate. 10 Then, as shown in FIG. 1e, while increasing the load f, the wiring substrate 110 and the semiconductor wafer 120 are bonded by instantaneously heating them at a temperature higher than the melting point of the metal bump 140 (for example, 250 ° C). Here, "instantaneously" means heating in a short period of time in order to reduce the thermal load on the semiconductor wafer 120, for example, a period of about 1 to 30 seconds. Therefore, the metal bump 140

15 可熔化而電性連接電極111及電極121。又，此時之昇溫 過程中，由於接著層130 —旦軟化，且金屬凸塊140融化 ，所以開口部130a之空隙會被接著層130之樹脂及/或熔 化金屬填埋。另可令該步驟之加熱溫度為較金屬凸塊140 之熔點還高，例如5〜50°C。 20 之後，如第If圖所示，藉由進行熱處理，使接著層 130加熱硬化。熱處理時之昇溫過程中，在到達硬化開始 溫度（例如170°C )之間，由於接著層130 —度軟化，故 開口部130a内之空隙會由接著層130之樹脂所填埋。接著 ，若到達硬化開始溫度，接著層130中便會進行硬化反應 16 200415749 玖、發明說明 。藉接著層130之硬化，可接合配線基板110和半導體晶 片120，同時完成兩者間之密封。15 The electrodes 111 and 121 can be electrically connected by melting. During the temperature rise at this time, since the bonding layer 130 is softened once and the metal bump 140 is melted, the void of the opening 130a is filled with the resin and / or molten metal of the bonding layer 130. In addition, the heating temperature in this step can be higher than the melting point of the metal bump 140, for example, 5 ~ 50 ° C. After 20, as shown in the If diagram, the adhesive layer 130 is heat-hardened by performing a heat treatment. During the heating process during the heat treatment, the adhesive layer 130 is softened to a degree when the hardening start temperature (for example, 170 ° C) is reached, so the voids in the opening 130a are filled with the resin of the adhesive layer 130. Then, if the hardening start temperature is reached, a hardening reaction will occur in the next layer 130 16 200415749 发明, description of the invention. By hardening the adhesive layer 130, the wiring substrate 110 and the semiconductor wafer 120 can be bonded, and the sealing therebetween can be completed at the same time.

依據本實施形態之連接方法，使大致覆蓋配線基板 110之表面110a全體之接著層130硬化，藉此可密封配線 5 基板110和半導體晶片120之間，同時位於半導體晶片 120之搭載區域外A (參考第If圖）之配線112及配線基 板110本身亦可獲得保護。藉此，由於不須另外形成用以 保護配線112和配線基板110本身之保護層，故可提高作 業效率。 10 又，在使接著層130與配線基板110和半導體晶片 120接觸之狀態中，令接著層130固定，藉由硬化時產生 之收縮而可相互地壓擠電極111及電極121。藉此，隔著 金屬凸塊140之電極111和電極121之電性連接愈發良好 ，而更提高配線基板110和半導體晶片120之連接可靠性 15 。According to the connection method of this embodiment, the adhesive layer 130 that substantially covers the entire surface 110a of the wiring substrate 110 is hardened, thereby sealing the wiring 5 between the substrate 110 and the semiconductor wafer 120 and being located outside the mounting area of the semiconductor wafer 120. The wiring 112 and the wiring substrate 110 themselves can also be protected (refer to the If figure). Thereby, since it is not necessary to form a protective layer for protecting the wiring 112 and the wiring substrate 110 itself, operation efficiency can be improved. 10. In a state where the adhesive layer 130 is in contact with the wiring substrate 110 and the semiconductor wafer 120, the adhesive layer 130 is fixed, and the electrodes 111 and 121 can be pressed against each other by shrinkage generated during curing. As a result, the electrical connection between the electrode 111 and the electrode 121 through the metal bump 140 becomes better, and the connection reliability of the wiring substrate 110 and the semiconductor wafer 120 is further improved 15.

更進一步，於接著層130設置開口部130a，且防止一 部份之接著層130介於電極111和電極121之間，藉此亦 可抑制導通電阻增大。 第2a〜2f圖顯示本發明第2實施形態之電極間連接構 20 造體形成方法的一連串步驟。本實施形態中亦係舉倒裝接 合為例來加以說明。 首先，如第2a圖所示，對表面210a設有電極211及 配線212之配線基板210，積層形成接著層230，俾覆蓋電 極211及配線212。至於接著層230之形成方法，則是與 17 200415749 玖、發明說明 如前關於第1實施形態所述者相同。 接著，如第2b圖所示，對接著層230，在與各電極 211對應之處形成開口部230a。至於開口部230a之形成方 法，則是與如前關於第1實施形態所述者相同。另，與第 5 1實施形態一樣，若使用預先成形之樹脂膜形成接著層230 ，亦可在將接著層230載置於配線基板210之表面210a之 前，預先於預定位置形成開口部230a。Furthermore, an opening portion 130a is provided in the bonding layer 130, and a part of the bonding layer 130 is prevented from being interposed between the electrode 111 and the electrode 121, thereby suppressing an increase in the on-resistance. Figures 2a to 2f show a series of steps in a method for forming an inter-electrode connection structure 20 in a second embodiment of the present invention. In this embodiment, an explanation will be given by taking a flip-chip joint as an example. First, as shown in FIG. 2a, a wiring substrate 210 having electrodes 211 and wirings 212 provided on the surface 210a is laminated to form an adhesive layer 230, and the electrodes 211 and wirings 212 are covered. The formation method of the bonding layer 230 is the same as that of the first embodiment described in 17 200415749. Next, as shown in Fig. 2b, an opening 230a is formed in the bonding layer 230 at a position corresponding to each electrode 211. The method of forming the opening 230a is the same as that described in connection with the first embodiment. In addition, as in the case of the 51st embodiment, if the bonding layer 230 is formed using a preformed resin film, the opening 230a may be formed in a predetermined position before the bonding layer 230 is placed on the surface 210a of the wiring substrate 210.

接著，如第2c圖所示，於開口部230a充填金屬糊 240。金屬糊240之充填可藉公知之壓擠法，和於接著層 10 230上設置對應開口部230a而開口之遮罩（圖中未顯示） 後，再藉印刷法等來進行。另，將金屬糊240充填至開口 部230a，並不限於前述方法。Next, as shown in Fig. 2c, a metal paste 240 is filled in the opening 230a. The filling of the metal paste 240 can be performed by a known pressing method, and a mask (not shown) corresponding to the opening 230a is provided on the adhesive layer 10 230, and then printed by a printing method or the like. The filling of the metal paste 240 into the opening 230a is not limited to the aforementioned method.

金屬糊240係由金屬粉末，及用以將金屬粉末糊化之 樹脂成分所構成。本實施形態中，金屬粉末係將選自於由 15 Sn、Pb、Ag、Cu、In、A卜 Au、Bi、Zn 及 Sb 等之單體金 屬，或者選自於由該等金屬之多數單體金屬所構成的合金 粉末化而製成者。又，令金屬糊240中金屬粉末之含有率 為20〜95wt°/。。若小於20wt% ，將有難以適當地連接電極 之間的傾向。若較95wt%更多，則金屬糊240之粘度便過 20 高，變得難以充填至開口部230a。另可以樹脂成分來控制 組成，使之後的加熱步驟中，於金屬粉末熔化後可與接著 層230 —體化。另，樹脂成分亦可使用關於接著層230所 列舉之主劑及硬化劑。 再者，亦可於金屬糊240添加用以提高對於電極211 18 200415749 玖、發明說明 、221之濕潤性的松香。松香可使用例如松香酸、松香酸 醋、松香酐、脂肪酸、松脂酸、異海松酸、新松脂酸、海 松酸、二氫松脂酸、脫氫松脂酸等。又，為了金屬表面之 活性化，亦可於金屬糊240添加與硬化劑不同之有機羧酸 5 和胺，更進一步，為了調整粘度，亦可添加二伸乙基乙二 醇和四伸乙基乙二醇等高級醇。The metal paste 240 is composed of a metal powder and a resin component for pasting the metal powder. In this embodiment, the metal powder is selected from a single metal consisting of 15 Sn, Pb, Ag, Cu, In, Au, Bi, Zn, and Sb, or a single metal consisting of a majority of these metals. An alloy made of a bulk metal is powdered and made. The content of the metal powder in the metal paste 240 is set to 20 to 95% by weight. . If it is less than 20% by weight, it may be difficult to properly connect the electrodes. If it is more than 95% by weight, the viscosity of the metal paste 240 becomes too high, and it becomes difficult to fill the opening 230a. In addition, the resin composition can be used to control the composition so that in the subsequent heating step, the metal powder can be integrated with the adhesion layer 230 after the metal powder is melted. For the resin component, the main agents and hardeners listed for the adhesive layer 230 may be used. Furthermore, rosin may be added to the metal paste 240 to improve the wettability of the electrode 211 18 200415749 玖, the description of the invention, and 221. As the rosin, for example, rosin acid, rosin acid vinegar, rosin anhydride, fatty acid, rosin acid, isopimaric acid, neo-rosin acid, rosin acid, dihydro rosin acid, dehydrorosin acid, and the like can be used. In addition, in order to activate the metal surface, an organic carboxylic acid 5 and an amine different from the hardener may be added to the metal paste 240. Furthermore, in order to adjust the viscosity, diethylene glycol and tetraethylene glycol may be added. Higher alcohols such as diols.

如第2d圖所示，充填金屬糊240之後，將具有較該配 線基板210之表面210a之面積小之封裝面積的半導體晶片 220搭載於配線基板210。在此，半導體晶片220係於基板 10 220a之表面形成有絕緣層220b及電極221者，且在接著 層230之開口部230a中經過對位，使金屬糊240和電極 221對向。另，亦可將對半導體晶片220之電極221形成 如第1實施形態中所說明之金屬凸塊者搭載於配線基板 210 °As shown in FIG. 2d, after the metal paste 240 is filled, a semiconductor wafer 220 having a smaller packaging area than the surface 210a of the wiring substrate 210 is mounted on the wiring substrate 210. Here, the semiconductor wafer 220 is formed on the surface of the substrate 10 220a with an insulating layer 220b and an electrode 221, and is aligned in the opening 230a of the bonding layer 230 so that the metal paste 240 and the electrode 221 face each other. It is also possible to mount the electrode 221 on the semiconductor wafer 220 with a metal bump as described in the first embodiment on a wiring substrate 210 °

15 接下來，如第2e圖所示，一邊增加負載f，一邊加熱 至金屬糊240所含之金屬粉末之熔點以上，藉此接合配線 基板210和半導體晶片220。因此，金屬糊240所含之金 屬粉末熔化而一體化，且電性連接電極211及電極221。 本實施形態中，係使用焊料粉末作為金屬糊240所含之金 20 屬粉末，且令接合時之加熱溫度為較該焊料之熔點高5〜50 °C之溫度。另，金屬糊240所含之樹脂成分係與金屬粉末 分離。 接著，如第2f圖所示，藉由進行熱處理，使接著層 230加熱硬化。此時，金屬糊240中之分離之樹脂成分將 19 200415749 玖、發明說明 與接著層230 —體化。藉接著層230之硬化，配線基板 21〇和半導體晶片220可接合。 第3a~3f圖顯示本發明第3實施形態之電極間連接構 造體形成方法的一連串步驟。本實施形態中亦係舉倒裝接 5 合為例來加以說明。15 Next, as shown in FIG. 2e, the wiring substrate 210 and the semiconductor wafer 220 are bonded by heating to a melting point of the metal powder contained in the metal paste 240 while increasing the load f. Therefore, the metal powder contained in the metal paste 240 is melted and integrated, and the electrode 211 and the electrode 221 are electrically connected. In this embodiment, solder powder is used as the metal 20 powder contained in the metal paste 240, and the heating temperature during bonding is set to a temperature 5 to 50 ° C higher than the melting point of the solder. The resin component contained in the metal paste 240 is separated from the metal powder. Next, as shown in FIG. 2f, the adhesive layer 230 is heat-hardened by performing a heat treatment. At this time, the separated resin component in the metal paste 240 is integrated into the body. By hardening the bonding layer 230, the wiring substrate 21 and the semiconductor wafer 220 can be bonded. Figures 3a to 3f show a series of steps in a method for forming an inter-electrode connection structure in a third embodiment of the present invention. In this embodiment, the flip joint 5 is used as an example for explanation.

首先，如第3a圖所示，對表面310a設有電極311及 配線312之配線基板310，積層形成接著層330，俾覆蓋電 極311及配線312。至於接著層330之形成方法，則是與 如前關於第1實施形態所述者相同。 10 接著，如第3b圖所示，對接著層330，在與各電極First, as shown in FIG. 3a, a wiring substrate 310 having electrodes 311 and wirings 312 on the surface 310a is laminated to form an adhesive layer 330, and the electrodes 311 and wirings 312 are covered. The method for forming the bonding layer 330 is the same as that described in connection with the first embodiment. 10 Next, as shown in FIG. 3b, the bonding layer 330 is

311對應之處形成開口部330a。至於開口部330a之形成方 法，則是與如前關於第1實施形態所述者相同。另，與第 1實施形態一樣，若使用預先成形之樹脂膜形成接著層330 ，亦可在將接著層330載置於配線基板310之表面310a之 15 前，預先於預定位置形成開口部330a。 接著，如第3c圖所示，在開口部330a中，於電極 311之上形成導體部313。導體部313可藉電鍍法或無電極 電鍍法而形成。 用以形成導體部313之材料，可使用Ab Au、In、Sn 20 、Cu、Ag、Pd等單體金屬，或者選自於由Sn、Pb、Ag、Corresponding to 311, an opening 330a is formed. The method of forming the opening 330a is the same as that described in connection with the first embodiment. In addition, as in the first embodiment, if the adhesive layer 330 is formed using a resin film formed in advance, the opening portion 330a may be formed at a predetermined position before the adhesive layer 330 is placed on the surface 310a of the wiring substrate 310. Next, as shown in Fig. 3c, a conductor portion 313 is formed on the electrode 311 in the opening portion 330a. The conductive portion 313 can be formed by a plating method or an electrodeless plating method. The material for forming the conductor portion 313 may be a single metal such as Ab Au, In, Sn 20, Cu, Ag, Pd, or a material selected from the group consisting of Sn, Pb, Ag,

Cu、In、Bi、Zn、Sb、A1、Au等之多數單體金屬所構成的 合金。其中，為了減小電極間之導通電阻，尤宜使用熔點 為80〜400°C之金屬，該金屬可例舉如In和Sn-Bi合金、 Sn-Pb合金、Sn-Zn合金、Sn-Ag-Cu合金等。另，亦可藉 20 200415749 玖、發明說明 依次積層不同組成之金屬而形成導體部313。 如第3d圖所示，形成導體部313之後，將具有較該配 線基板310之表面310a之面積小之封裝面積的半導體晶片 320搭載於配線基板310。在此，半導體晶片320係於基板 5 320a之表面形成有絕緣層320b及電極321者，且在接著An alloy composed of most of single metals such as Cu, In, Bi, Zn, Sb, A1, and Au. Among them, in order to reduce the on-resistance between the electrodes, it is particularly suitable to use a metal having a melting point of 80 to 400 ° C. The metal can be exemplified by In and Sn-Bi alloys, Sn-Pb alloys, Sn-Zn alloys, and Sn-Ag -Cu alloy, etc. In addition, the conductor portion 313 can also be formed by sequentially laminating metals of different compositions by 20 200415749 玖, description of the invention. As shown in FIG. 3d, after the conductor portion 313 is formed, a semiconductor wafer 320 having a smaller packaging area than the area 310a of the wiring substrate 310 is mounted on the wiring substrate 310. Here, the semiconductor wafer 320 is formed by forming an insulating layer 320b and an electrode 321 on the surface of the substrate 5 320a.

層330之開口部330a中經過對位，使導體部313和電極 321對向。另，亦可將對半導體晶片320之電極321形成 如第1實施形態中所說明之金屬凸塊者搭載於配線基板 310 ° 10 接下來，如第3e圖所示，一邊增加負載f，一邊加熱 ，藉此接合配線基板310和半導體晶片320。此時，導體 部313對電極311及電極321熔接，且電性連接電極311 及電極321。The opening 330a of the layer 330 is aligned so that the conductor portion 313 and the electrode 321 face each other. In addition, the electrode 321 of the semiconductor wafer 320 may be formed on the wiring substrate 310 ° 10 as a metal bump as described in the first embodiment. Next, as shown in FIG. 3e, the load f is increased while heating. Thereby, the wiring substrate 310 and the semiconductor wafer 320 are bonded. At this time, the conductor portion 313 is welded to the electrode 311 and the electrode 321, and is electrically connected to the electrode 311 and the electrode 321.

接著，如第3f圖所示，藉由進行熱處理，使接著層 15 330加熱硬化。藉接著層330之硬化，配線基板310和半 導體晶片320可接合。 本發明之第1〜第3實施形態中，係舉半導體晶片和配 線基板之連接為例而說明者，不過接合對象物並不限於此 。舉例而言，如第4圖所示，接合對象物亦可係於基板 20 410a之表面形成絕緣層410b、電極411及配線412而獲得 之半導體晶片410，和藉由在較該表面之面積小之封裝面 積之表面形成絕緣層420b及電極421而獲得之半導體晶片 420的半導體晶片，亦可係一方封裝面積較另一方之表面 面積小的配線基板等。 21 200415749 玖、發明說明 〔實施例1〕 〈液狀樹脂組成物之調整〉 令作為主劑之固形種類之酸偏基型環氧丙烯酸酯樹脂 (曰本優比卡股份有限公司（Japan U-PiCA Co·，Ltd.;日 5 本二匕力株式会社）製）為25wt% ，作為主劑之固形種類 之聯苯型環氧樹脂（商品名：艾比寇特（Epikote ;工匕口 一卜）YX4000，曰本環氧樹脂股份有限公司（Japan EpoxyNext, as shown in FIG. 3f, the adhesive layer 15 330 is heat-hardened by performing a heat treatment. By hardening the bonding layer 330, the wiring substrate 310 and the semiconductor wafer 320 can be bonded. In the first to third embodiments of the present invention, the connection between the semiconductor wafer and the wiring substrate is described as an example, but the bonding target is not limited to this. For example, as shown in FIG. 4, the bonding object may also be a semiconductor wafer 410 obtained by forming an insulating layer 410b, an electrode 411, and a wiring 412 on the surface of the substrate 20 410a, and a smaller area than the surface The semiconductor wafer of the semiconductor wafer 420 obtained by forming the insulating layer 420b and the electrode 421 on the surface of the package area may also be a wiring substrate having a smaller package area on one side than the other. 21 200415749 发明, Description of the invention [Example 1] <Adjustment of liquid resin composition> The solid type of acid-based epoxy acrylate resin used as the main agent (Japanese U-Bica Corporation (Japan U- PiCA Co., Ltd .; manufactured by Japan Nippon Erjili Co., Ltd.) is a 25% by weight, solid type biphenyl epoxy resin (trade name: Epikote; industrial dagger) (B) YX4000, Japan Epoxy Corporation

Resins Co·，Ltd·;工求夺シ卜夕^株式会社）製 )為8.5wt% ，為丙烯基單體之二季戊四醇六丙烯酸酯（商Resins Co., Ltd .; manufactured by Industrial Engineering Co., Ltd.) is 8.5% by weight, and is a pentaerythritol hexaacrylate (quote

10 品名：阿洛尼庫斯（alonex ; 了 口二v夕只）M-402，東亞 合成股份有限公司（Toagosei Limited;東亜合成株式会社 )製）為8.0% ，為光聚合起始劑之2-曱基-1〔 4-(甲硫基 )苯基〕-2-嗎福琳基丙烧-1-闕（商品名·伊路葛克爾（ Irgacure ;彳少方导二了）907，季霸特殊化學材料（Ciba 15 Speciality Chemicals K. K.;于/只夂シ亇Ρ亍彳少S力少 文）製）為7.0% ，令卡必醇乙酯為10.6%作為溶劑，而調 製成含有40.9%之溶劑之甲基乙基酮的中間樹脂組成物。 將該中間樹脂組成物和平均粒徑4 // m之矽粉末，以重量 比1 : 1 (氧化矽粉末之添加率為50wt% )混合，且調整成 20 樹脂膜形成用之液狀樹脂組成物。 〈樹脂膜之製作〉 將前述之液狀樹脂組成物塗布於PET膜（厚20/zm) 上形成厚70# m之後，再以90°C乾燥3分鐘，藉此除去溶 劑，而製成膜厚40 // m之樹脂膜。 22 200415749 玖、發明說明 〈倒裝接合〉 利用滾動式貼件機（MCK股份有限公司（MCK c〇.， LTD·;(株）工A · ·卜）製）而在8(Γ(：之加熱下 ，將依前述而製成之樹脂膜黏合而形成接著層，俾覆蓋配 5線基板（電極徑# m )之表面全體。接著，對該接著層 進行曝光及顯像，而形成直徑1〇〇 Am之開口部，使電極 露出。顯像係使用2.38%氫氧化四甲基銨來進行。將電極 上形成有Sn-3.5% Ag凸塊（高35“ m)之半導體晶片搭載 於該配線基板。此時，在開口部中進行對位，使Sn_3 5% 10 Ag凸塊和配線基板之電極對向。接著，對半導體晶片，在 250°C中增加5000g之負載，且瞬間地接合。之後，對半導 體晶片和配線基板之接合體，以17〇它進行15分鐘熱處理 ，藉此使接著層完全硬化。因此，獲得半導體晶片倒裝接 合於配線基板之電極間連接構造體。 15 〔實施例2〕 除了於該電極形成Sn-37% Pb凸塊（高35/zm),以取 代實施例1中形成於半導體晶片之電極之Sn_3 5% Ag凸塊 (高35&quot;m)，以及令接合時之加熱溫度為22(rc以外，其 他皆與實施例1相同而進行倒裝接合，而獲得本實施例之 20 電極間連接構造體。 〔實施例3〕 除了形成開口部後’對該開口部直接充填含環氧系之 树脂的焊糊（商品名·填充糊（underfill paste ; 了 y夕、、1— 卜）#2〇〇〇，千住金屬工業股份有限公司（ 23 200415749 玖、發明說明10 Product name: Alone Kuss (alonex; 二 二 v 夕 only) M-402, manufactured by Toagosei Limited (Toagosei Limited; Tohosei Co., Ltd.) is 8.0%, which is 2 of the photopolymerization initiator -Fluorenyl-1 [4- (methylthio) phenyl] -2-morpholinylpropan-1-ol (trade name · Irgacure; 彳 少 方 引 二 了) 907, quarter Specialty Chemicals (Ciba 15 Speciality Chemicals KK; manufactured by 夂 シ 亇 Ρ 亍 彳 少 S 力 少 文)) is 7.0%, carbitol ethyl ester is 10.6% as a solvent, and is prepared to contain 40.9% An intermediate resin composition of methyl ethyl ketone in a solvent. The intermediate resin composition and silicon powder having an average particle diameter of 4 // m are mixed at a weight ratio of 1: 1 (the addition ratio of the silicon oxide powder is 50% by weight), and adjusted to a liquid resin composition for forming a resin film of 20 Thing. <Production of Resin Film> The aforementioned liquid resin composition was coated on a PET film (thickness 20 / zm) to form a thickness of 70 # m, and then dried at 90 ° C. for 3 minutes to remove the solvent and form a film. 40 / m thick resin film. 22 200415749 发明, Description of the invention <Flip-chip bonding> Using a rolling type placement machine (MCK Co., Ltd. (MCK Co., Ltd .; Co., Ltd .; A. · Bu)) at 8 (Γ (: of Under heating, the resin film made as described above is adhered to form an adhesive layer, and the entire surface of the 5-wire substrate (electrode diameter # m) is covered. Then, the adhesive layer is exposed and developed to form a diameter of 1 The opening of 〇〇Am exposes the electrode. Development is performed using 2.38% tetramethylammonium hydroxide. A semiconductor wafer with Sn-3.5% Ag bumps (35 "m high) formed on the electrode is mounted on this Wiring substrate. At this time, the alignment is performed in the opening so that the Sn_3 5% 10 Ag bumps and the electrodes of the wiring substrate face each other. Next, a 5000g load is added to the semiconductor wafer at 250 ° C and the bonding is instantaneous Then, the bonded body of the semiconductor wafer and the wiring substrate was heat-treated at 170 ° C for 15 minutes to completely harden the adhesive layer. Therefore, a semiconductor wafer flip-chip bonded structure to the electrode connection structure of the wiring substrate was obtained. 15 [ Example 2] Except for the electrode formation Sn-37% Pb bump (35 / zm high) to replace the Sn_3 5% Ag bump (35 &quot; m) of the electrode formed on the semiconductor wafer in Example 1, and the heating temperature during bonding was 22 ( Except for rc, the other parts were flip-chip bonded in the same manner as in Example 1 to obtain the 20-electrode connection structure of this example. [Example 3] Except for forming the opening portion, the opening portion was directly filled with an epoxy-containing system. Resin solder paste (trade name · underfill paste; 夕夕 ,, 1— 卜) # 2〇〇〇, Senju Metal Industry Co., Ltd. (23 200415749), invention description

Senju Metal Industry Co.，Ltd。；千住金属工業株式会社） 製），以及令形成於半導體晶片之電極之Sn-3.5% Ag凸塊 的高度為15/zm以外，其他皆與實施例1相同而進行倒裝 接合，而獲得本實施例之電極間連接構造體。 5 〔實施例4〕Senju Metal Industry Co., Ltd. ; Manufactured by Senju Metal Industry Co., Ltd.), and the height of the Sn-3.5% Ag bump formed on the electrode of the semiconductor wafer is 15 / zm, and other parts are the same as in Example 1 and flip-chip bonding is performed to obtain the present invention. The structure for connecting electrodes between the examples. 5 [Example 4]

除了在接著層上設置對應形成於接著層之開口部而開 口之金屬遮罩（開口直徑80 # m，厚30 # m)後，於開口 部充填焊糊，以及令形成於半導體晶片之電極之Sn-3.5% Ag凸塊的高度為10/zm以外，其他皆與實施例3相同而 10 進行倒裝接合，而獲得本實施例之電極間連接構造體。 〔實施例5〕In addition to setting a metal mask (opening diameter 80 # m, thickness 30 # m) corresponding to the opening formed on the adhesive layer on the adhesive layer, filling the opening with a solder paste and filling the electrode formed on the semiconductor wafer The height of the Sn-3.5% Ag bump is other than 10 / zm, and the other parts are the same as in Example 3 and 10 is flip-chip bonded to obtain an electrode connection structure of this example. [Example 5]

除了於該電極形成Au柱形凸塊（高30/zm)，以取代 實施例1中形成於半導體晶片之電極之Sn-3.5% Ag凸塊（ 高35/zm)，以及令形成於接著層之開口部的直徑為50/zm 15 以外，其他皆與實施例1相同而進行倒裝接合，而獲得本 實施例之電極間連接構造體。 〔實施例6〕 除了形成開口部後，對該開口部直接充填含環氧系之 樹脂的焊糊（商品名：填充糊（underfill paste ; 了 V〆一 20 7 &lt;少义一只卜）# 2000，千住金屬工業股份有限公司（In addition to forming Au stud bumps (30 / zm high) on the electrode, it replaces the Sn-3.5% Ag bumps (35 / zm high) of the electrode formed on the semiconductor wafer in Example 1, and formed on the adhesive layer. Except that the diameter of the opening is 50 / zm 15, the other parts are the same as in Example 1 and are flip-chip bonded to obtain an electrode connection structure of this example. [Example 6] Except for forming the opening, the opening was directly filled with a solder paste containing an epoxy-based resin (trade name: underfill paste; V〆-20 7 &lt; one less) # 2000, Senju Metal Industry Co., Ltd. (

Senju Metal Industry Co·，Ltd·;千住金属工業株式会社） 製）以外，其他皆與實施例5相同而進行倒裝接合，而獲 得本實施例之電極間連接構造體。 〔實施例7〕 24 200415749 玖、發明說明 除了在接著層上設置對應形成於接著層之開口部而開 口之金屬遮罩（開口直徑30 // m，厚20 // m)後，於開口 部充填焊糊以外，其他皆與實施例6相同而進行倒裝接合 ，而獲得本實施例之電極間連接構造體。 5 〔實施例8〕Except for Senju Metal Industry Co., Ltd .; manufactured by Senju Metal Industry Co., Ltd.), the other parts were flip-chip bonded in the same manner as in Example 5 to obtain an electrode connection structure of this example. [Example 7] 24 200415749 发明, description of the invention Except for providing a metal mask (opening diameter 30 // m, thickness 20 // m) corresponding to the opening portion formed on the adhesive layer on the adhesive layer, the opening portion Except for filling the solder paste, the other parts were the same as in Example 6 and flip-chip bonding was performed to obtain an inter-electrode connection structure of this example. 5 [Example 8]

除了將樹脂膜黏合於配線基板之表面之前，在PET膜 上預先藉曝光及顯影形成開口部以外，其他皆與實施例1 相同而進行倒裝接合，而獲得本實施例之電極間連接構造 體。 10 〔實施例9〕Except that the resin film was adhered to the surface of the wiring substrate, the PET film was opened in advance by exposure and development to form openings, and other parts were flip-chip bonded in the same manner as in Example 1 to obtain an electrode connection structure of this example. . 10 [Example 9]

除了於該電極形成Au柱形凸塊（高30// m)，以取代 實施例8中形成於半導體晶片之電極之Sn-3.5% Ag凸塊（ 高35 // m )，以及令開口部之直徑為50 // m以外，其他皆 與實施例8相同而進行倒裝接合，而獲得本實施例之電極 15 間連接構造體。 (溫度循環測試） 分別就實施例1〜9之電極間連接構造體，藉溫度循環 測試，調查連接可靠性。具體而言，首先就電極間連接構 造體之各電極間連接部測量初始導通電阻。接著，在一55 20 °C~125°C之範圍内進行溫度循環測試後，再次測量各連接 部之導通電阻。溫度循環測試係令以一55°C冷卻15分鐘， 在室溫中放置10分鐘，及以125t加熱15分鐘為1循環 ，且反覆該循環2000次。結果，就實施例1〜9全部之電極 間連接構造體而言，各連接部之電阻上昇在10%以下，確 25 200415749 玖、發明說明 認其形成良好之連接部。 (耐濕測試）In addition to forming an Au stud bump (30 // m high) on the electrode, it replaces the Sn-3.5% Ag bump (35 // m) of the electrode formed on the semiconductor wafer in Example 8 and the opening Except that the diameter is 50 // m, the other parts are the same as in Example 8 and flip-chip bonding is performed to obtain the electrode 15 connection structure of this example. (Temperature cycle test) The connection reliability of each of the electrode connection structures of Examples 1 to 9 was examined by a temperature cycle test. Specifically, first, the initial on-resistance was measured for each electrode-electrode connection portion of the electrode-to-electrode connection structure. Next, after performing a temperature cycle test within a range of 55 to 20 ° C to 125 ° C, measure the on-resistance of each connection again. The temperature cycle test was performed by cooling at -55 ° C for 15 minutes, leaving it at room temperature for 10 minutes, and heating at 125t for 15 minutes as a cycle, and this cycle was repeated 2000 times. As a result, for all the connection structures between the electrodes of Examples 1 to 9, the resistance of each connection portion increased by 10% or less, and it was confirmed that the connection portions formed well. (Moisture resistance test)

分別就實施例1〜9之電極間連接構造體，藉耐濕測試 ，調查連接可靠性。具體而言，首先就電極間連接構造體 5 之各電極間連接部，在25°C及溼度60%之環境下，測量初 始導通電阻。接著，將各電極間連接構造體放置於121°C 及溼度85%之環境下，且再測量經過1000小時後之各連 接部之導通電阻。結果，就實施例1〜9全部之電極間連接 構造體而言，各連接部之電阻上昇在10%以下，確認其形 10 成良好之連接部。 〔比較例〕 除了配線基板之表面所形成之接著層未形成開口部以 外，其他皆與實施例1相同而進行倒裝接合，而獲得本比 較例之電極間連接構造體。For the connection structures between the electrodes of Examples 1 to 9, the reliability of the connection was investigated by a moisture resistance test. Specifically, the initial on-resistance of the inter-electrode connection portion of the inter-electrode connection structure 5 was measured in an environment of 25 ° C and 60% humidity. Next, the connection structure between the electrodes was placed in an environment of 121 ° C and 85% humidity, and the on-resistance of each connection portion after 1,000 hours had elapsed was measured. As a result, in all of the electrode connection structures of Examples 1 to 9, the resistance of each connection portion was increased by 10% or less, and it was confirmed that the connection portion formed a good connection portion. [Comparative Example] Except that the adhesive layer formed on the surface of the wiring substrate was not formed with an opening portion, it was subjected to flip-chip bonding in the same manner as in Example 1 to obtain an electrode connection structure of this comparative example.

15 就此種藉倒裝接合而形成之電極間連接構造體，進行 與實施例1〜9相同之溫度循環測試，結果係就各連接部， 確認有20%之電阻上昇。又，進行與實施例1~9相同之耐 濕測試，結果係與溫度循環測試一樣，就各連接部，確認 有30%以上之電阻上昇。 20 【圖式簡單說明】 第la~lf圖係顯示利用本發明第1實施形態之電極間 連接構造體形成方法之倒裝接合之一連串步驟的概略截面 圖。 第2a〜2f圖係顯示利用本發明第2實施形態之電極間 26 200415749 玖、發明說明 連接構造體形成方法之倒裝接合之一連串步驟的概略截面 圖。 第3a〜3f圖係顯示利用本發明第3實施形態之電極間 連接構造體形成方法之倒裝接合之一連串步驟的概略截面 5 圖。 第4圖係藉連接半導體晶片而獲得之電極間連接構造 體的概略截面圖。15 The same temperature cycle test as in Examples 1 to 9 was performed on the electrode-to-electrode connection structure formed by flip-chip bonding. As a result, it was confirmed that the resistance of each connection portion increased by 20%. Further, the same humidity resistance test as in Examples 1 to 9 was performed. As a result, it was confirmed that the resistance of each connection portion was increased by 30% or more in the same manner as in the temperature cycle test. 20 [Brief description of the drawings] Figures la to lf are schematic cross-sectional views showing a series of steps of flip-chip bonding using the method for forming an electrode connection structure according to the first embodiment of the present invention. Figures 2a to 2f are schematic cross-sectional views showing a series of steps in a flip-chip bonding method of forming a connection structure using the inter-electrode cell according to the second embodiment of the present invention. Figures 3a to 3f are schematic cross-sectional views showing a series of steps of flip-chip bonding using the method for forming an electrode connection structure according to the third embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of an inter-electrode connection structure obtained by connecting a semiconductor wafer.

第5a~5e圖係顯示利用習知電極間連接構造體形成方 法之倒裝接合之一連串步驟的概略截面圖。 10 【圖式之主要元件代表符號表】 110,210,310,510. · ·配線基板 UOa^lOa^lOa …表面5a to 5e are schematic cross-sectional views showing a series of steps of flip-chip bonding using a conventional method for forming a connection structure between electrodes. 10 [Representative symbols for the main components of the diagram] 110,210,310,510. ·· Wiring substrate UOa ^ lOa ^ lOa… surface

111，121，211，221，311，321，411，421，511,521...電極 112,212,312,412,512···配線 120,220,320,410,420,520...半導體晶片 120a,220a,320a,410a,520a.. 120b,220b,320b, 410b,420b,520b&quot;.絕緣層 130,230,330.。.接著層 130^230a330a…開口部 140…金屬凸塊 240…金屬糊 313…導體部 530···填充劑（接著劑） 540…凸塊 27 200415749 玖、發明說明 560…助溶劑 A.。.搭載區域外 f···負載111, 121, 211, 221, 311, 321, 411, 421, 511, 521 ... electrodes 112, 212, 312, 412, 512 ... wiring 120, 220, 320, 410, 420, 520 ... semiconductor wafers 120a, 220a, 320a, 410a, 520a ... 120b, 220b, 320b, 410b , 420b, 520b &quot;. Insulating layer 130,230,330 ... .Adhesive layer 130 ^ 230a330a ... opening 140 ... metal bump 240 ... metal paste 313 ... conductor 530 ... filler (adhesive) 540 ... bump 27 200415749 发明, description of the invention 560 ... cosolvent A .. .. Outside the loading area f ...

Claims (1)

200415749 拾、申請專利範圍 L 一種電極間連接構造體之形成方法，包含有： 對表面具有第1電極部之第丨連接對象物，形成 具有開口部之接著層，使該第!電極部由該開口部 路出，且至少覆蓋該表面之一部份的步驟； 5 對該第1連接對象物，將具有第2電極部之第2 連接對象物配置成該第i電極部和該第2電極部對向 且該接著層與該第2連接對象物相接的步驟；及 +進行加熱處理，使該第！電極部及該第2電極部 藉由導體部而電性連接，同時該接著層硬化的連接 10 步驟。 2·如申請專利第！項之電極間連接構造體之形成 方法’其巾前述接著層係使用具有感光性之材料而 形成者。 3·如申請專利第丨項之電_連接構造體之形成 15 方法，其中前述接著層含有無機填料。 4.如申請專利範圍第！項之電極間連接構造體之形成 方法’其巾前料體部係預先形錢科帛丨電極 部或前述第2電極部其中—方之金屬凸塊，而前述 第1電極朴W述帛2電極部之電性連接係藉由該 20 凸塊而進行。 5·如申請專利範圍第4項之電極間連接構造體之形成 方法，其中前述凸塊係熔點為8〇〜4〇〇t之金屬或合 金。 6.如申請專利範圍第4項之電極間連接構造體之形成 29 200415749 拾、申請專利範圍 方法’其中前述凸塊係由一夸好 I材所構成，而該素材 係選自於由 Sn、Pb、Ag、Cu、In、ai、Au Bi、 Zn及Sb所構成之群組者。 5 7·如申請專㈣圍第i項之電極間連接構造體之形成 方法，更包含有於前述開口部充填含金屬之金屬糊 的充填步驟’而前述導體部係藉該金屬糊固化而形 成者。200415749 Patent application scope L A method for forming a connection structure between electrodes includes: a first object to be connected with a first electrode portion on a surface thereof, forming an adhesive layer having an opening portion, so that the first electrode portion is formed by the first electrode portion; A step of opening the opening and covering at least a part of the surface; 5 for the first connection object, disposing a second connection object having a second electrode portion into the i-th electrode portion and the second electrode A step where the parts face each other and the adhesive layer is in contact with the second connection object; and + heat treatment is performed to make the first! The electrode portion and the second electrode portion are electrically connected through a conductor portion, and the bonding layer is hardened and connected in 10 steps. 2 · If you apply for a patent! The method of forming the connection structure between electrodes of the item 'is a method in which the aforementioned adhesive layer is formed using a material having photosensitivity. 3. The method for forming an electrical connection structure as described in Patent Application No. 丨, wherein the aforementioned adhesive layer contains an inorganic filler. 4. If the scope of patent application is the first! The method of forming the connection structure between the electrodes of the item 'its front material body is a pre-shaped money section of the electrode section or the second electrode section of which is a metal bump, and the first electrode is described above. 2 The electrical connection of the electrode portions is performed by the 20 bumps. 5. The method for forming an inter-electrode connection structure according to item 4 of the application, wherein the bump is a metal or alloy having a melting point of 80 to 400 t. 6. The formation of the connection structure between the electrodes according to item 4 of the scope of patent application 29 200415749 The method of applying for the scope of patent application, wherein the aforementioned bumps are composed of a material I, and the material is selected from the group consisting of Sn, Group consisting of Pb, Ag, Cu, In, ai, Au Bi, Zn, and Sb. 5 7 · If the application method for forming the connection structure between the electrodes in the item i is applied, the method further includes a filling step of filling the opening with a metal-containing metal paste. By. 8.如申請專利範圍第Μ之電極間連接構造體之形成 10 方法其中别述導體部係藉電鑛及/或無電極電鑛而 形成者。 種電極間連接構造體，包含有： 表面具有第1電極部之第i連接對象物； Λ有與该第1電極部對向之第2電極部的第2連 接對象物； 15 用以連接該第1電極部和該第2電極部的導體部 ;及8. The method for forming the connection structure between electrodes according to the scope of the patent application. 10 Method, in which the conductor part is formed by electric ore and / or electrodeless electric ore. An inter-electrode connection structure includes: an i-th connection object having a first electrode portion on a surface; Λ a second connection object having a second electrode portion opposite to the first electrode portion; 15 for connecting the The first electrode portion and the conductor portion of the second electrode portion; and 用以充填該第1連接對象物和該第2連接對象物 之間，同時大致覆蓋前述表面全體的接著層。 20 30The bonding layer is used to fill the space between the first connection object and the second connection object, while covering substantially the entire surface of the surface. 20 30
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