JP2004296917A - Substrate for mounting semiconductor and semiconductor device - Google Patents

Substrate for mounting semiconductor and semiconductor device Download PDF

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Publication number
JP2004296917A
JP2004296917A JP2003089065A JP2003089065A JP2004296917A JP 2004296917 A JP2004296917 A JP 2004296917A JP 2003089065 A JP2003089065 A JP 2003089065A JP 2003089065 A JP2003089065 A JP 2003089065A JP 2004296917 A JP2004296917 A JP 2004296917A
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Prior art keywords
resin
semiconductor
sealing resin
mounting substrate
solder
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JP2003089065A
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Japanese (ja)
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Hitoshi Aoki
仁 青木
Shinichiro Ito
真一郎 伊藤
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Sumitomo Bakelite Co Ltd
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Sumitomo Bakelite Co Ltd
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Priority to JP2003089065A priority Critical patent/JP2004296917A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor and a semiconductor device capable of preventing the occurrence of voids in a sealing resin, in the flip chip mounting method of a semiconductor chip. <P>SOLUTION: This is a substrate 120 for mounting a semiconductor for flip chip mounting a semiconductor chip 110 where a bump 111 is formed through a sealing resin 130. A pad 122 is formed at a position corresponding to the bump 111. A gas barrier film 121 is formed on the surface contacting with the sealing resin 130. The gas barrier film 121 is formed at a part except for a part where the pad 111 is exposed of the surface contacting with the sealing resin 130. The semiconductor chip 110 where the bump 111 is formed is flip chip mounted on the substrate 120 for mounting the semiconductor through the sealing resin 130. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体搭載用基板および半導体装置に関するものである。更に詳しくは、半導体チップを、封止樹脂を介して、フリップチップ実装するための半導体搭載用基板、および、それに半導体チップを実装した半導体装置に関するものである。
【０００２】
【従来の技術】
近年、半導体チップを半導体搭載用基板上に実装する方法として、フリップチップ実装法が注目されている。フリップチップ実装法とは、チップ電極に、半田パンプを設け、更に、半田バンプ上に、半田ボールを有する半導体チップを、フェースダウンにて、半導体搭載用基板の配線パターンの半田バンプ又は半田ランド上に、直接、半田接合する方法である。フリップチップ実装法による電極接合では、半田接合を適用したＣ４（Ｃｏｎｔｒｏｌｌｅｄ Ｃｏｌｌａｐｓｅ Ｃｈｉｐ Ｃｏｎｎｅｃｔｉｏｎ）プロセスが代表的な工法として挙げられる。
【０００３】
Ｃ４プロセスによるフリップチップ実装では、半導体チップと半導体搭載用基板との半田接合部を、外部環境から遮断して保護するために、かつ、半導体チップと半導体搭載用基板の線膨張係数の差により発生する熱応力が、半田接合部に集中するのを防ぐために、半田接合部封止用の樹脂が、半導体チップと半導体搭載用基板の間隙に充填され、半田接合部を封止している。
【０００４】
フリップチップ実装用の封止樹脂を、半導体チップと半導体搭載用基板との間隙に充填する際に、Ｃ４プロセスで広く使用されている封止樹脂の充填方式は、キャピラリ・フロー法と圧縮フロー法とに大別される。最近では、生産性を向上させる充填方法として、圧縮フロー法が注目されている。圧縮フロー法による例としては、まず、熱硬化性樹脂にフラックス剤を含有させたフラックス剤含有樹脂を、フリップチップ実装用の封止樹脂として使用する。圧縮フロー法では、半導体チップを半導体搭載用基板上に搭載する前に、熱硬化性樹脂にフラックス剤を添加したフラックス剤含有樹脂を、半導体搭載用基板上に塗布する。次いで、半導体チップを半導体搭載用基板上に配置し、その際、半導体チップを押圧することにより、熱硬化性樹脂の塗布層を押し拡げる。次いで、半導体チップと半導体搭載用基板とを、リフロー炉に入れ、熱硬化性樹脂中のフラックス剤で、半田バンプ及び半田ボールの酸化皮膜を除去すると共に、半田をリフローさせて半田接合させる。同時に、半導体チップと半導体搭載用基板との間隙に充填された熱硬化性樹脂を硬化させる。これにより、半導体チップの半田バンプと半導体搭載用基板の半田バンプとが半田接合されて、半田接合部が形成されると共に、半導体チップと半導体搭載用基板都の間の間隙が封止樹脂で充填され、半田接合部が封止される（例えば、特許文献１参照。）。
【０００５】
一方、他のフリップチップ実装法として、圧接工法と呼ばれる方法が注目されている。この工法の特徴は、半田、導電性樹脂等の接合材料を供給する必要がなく、半導体素子の電極と半導体搭載用基板上のパッドとを、半導体素子と半導体搭載用基板の間に充填する封止樹脂の収縮力により、機械的な接触のみで、電気的に接続させるものである。この工法では、まず、半導体搭載用基板上の半導体素子搭載部に、封止樹脂を供給し、この上に、半導体素子を搭載し、この状態で加熱・加圧して、封止樹脂を硬化させ、電極同士の接続を得ている（例えば、特許文献２参照。）。
【０００６】
【特許文献１】
特開平４−２８０４４３号公報（第６頁、第１図、第２図）
【特許文献２】
特開９−０９７８１６号公報（第６頁、第１図）
【０００７】
【発明が解決しようとする課題】
しかしながら、上述の工法においては、半導体チップを半導体搭載用基板に実装する際に、半導体搭載用基板の絶縁樹脂に含まれる吸湿による水分、絶縁樹脂に含まれる熱硬化性樹脂の未硬化成分、絶縁樹脂に含まれる加熱による樹脂の分解成分、あるいは、絶縁樹脂がシアネート樹脂を含む場合には、シアネート樹脂の加水分解成分が、封止樹脂に拡散してボイドになるという問題があった。このボイド発生現象は、封止樹脂が流動状態あるいは軟化状態となるときに、最も発生しやすいが、封止樹脂が封止・接着機能を発現するためには、封止樹脂が流動状態あるいは軟化状態にならざるを得ない。
【０００８】
本発明は、半導体チップのフリップチップ実装法における、このような現状の問題点に鑑み、封止樹脂にボイドの発生させない半導体搭載用基板および半導体装置を提供することを目的とする。
【０００９】
【課題を解決するための手段】
即ち、本発明は、
１． バンプが形成された半導体チップを、封止樹脂を介してフリップチップ実装するための半導体搭載用基板であって、前記バンプに対応する位置にパッドが形成されており、前記封止樹脂と接する面にガスバリア膜が形成されていることを特徴とする半導体搭載用基板、
２． 前記封止樹脂と接する面のうち、前記パッドが露出している部分以外にガスバリア膜が形成されてなる第１項記載の半導体搭載用基板、
３． 前記封止樹脂と接する面が有機物および無機物から構成され、少なくとも有機物からなる面にはガスバリア膜が形成されてなる第１項または第２項に記載の半導体搭載用基板、
４． 前記ガスバリア膜が、無機物からなる第１項〜第３項のいずれかに記載の半導体搭載用基板、
５． 第１項〜第４項のいずれかに記載の半導体搭載用基板に、バンプが形成された半導体チップを、封止樹脂を介してフリップチップ実装した半導体装置、
６． 前記バンプが、金または半田を含んでなる第５項記載の半導体装置、
７． 前記封止樹脂が、表面清浄化機能を有してなる第５項または第６項に記載の半導体装置、
を提供するものである。
【００１０】
【発明の実施の形態】
従来の実施形態（図示せず）においては、加熱する際に半導体搭載用基板の絶縁樹脂に含まれる吸湿による水分、熱硬化性樹脂の未硬化成分、樹脂の加熱による分解成分などが、流動状態あるいは軟化状態になる封止樹脂に拡散してボイドになることがあったが、本発明の実施形態（図１参照）においては、ガスバリア膜１２１によって、半導体搭載用基板に含まれるボイド発生成分の封止樹脂１３０への拡散が抑制されるためボイドは発生しない。
【００１１】
以下、図面を参照して、本発明の実施形態について具体的に説明するが、本発明はこれによって何ら限定されるものではない。
【００１２】
図１は、本発明の実施形態である半導体装置の製造方法の一例を説明するための図で、図１（ｂ）は得られる半導体装置の構造を示す断面図である。また、図１（ａ）には本発明の半導体搭載用基板の構造を示す断面図も記載されている。
【００１３】
本発明に用いる半導体チップ１１０は、チップの電極上に、半導体搭載用基板のパッド１２２と電気的接続をするためのバンプ１１１が形成されたものである。前記バンプ１１１の材質は、パッド１２２に熱圧着することで、適度に変形して、パッド１２２に熱拡散しやすい金、または、パッド１２２と金属接合可能な半田を含むことが好ましい。金を含むバンプ１１１を形成する方法としては、電解めっきや無電解めっきによる方法の他に、ワイヤーボンダーを利用したスタッドバンプ方式などが挙げられる。半田の材質としては、パッド１１１と金属接合可能な金属であればどのようなものでもよいが、ＳｎやＩｎ、もしくはＳｎ、Ａｇ、Ｃｕ、Ｚｎ、Ｂｉ、Ｐｄ、Ｓｂ、Ｐｂ、Ｉｎ、Ａｕの少なくとも二種からなる半田を使用することが好ましい。より好ましくは、環境に優しいＰｂフリー半田である。半田を含むバンプ１１１を形成する方法としては、電解めっきや無電解めっきによる方法の他に、蒸着による方法、半田ペーストを印刷してリフローする方法などが挙げられる。一方で、パッド１２２上に半田被膜または半田バンプが形成されている場合には、半導体チップ１１０に形成されたバンプ１１１の材質に関係なく、その半田被膜または半田バンプにより、半導体チップと半導体搭載用基板との電気的接続を得ることができる。
【００１４】
本発明の半導体搭載用基板１２０は、主として絶縁樹脂等の有機物からなる基材１２４上に、少なくとも前記半導体チップのバンプに相対する位置にパッド１２２が形成され、前記半導体チップを実装する際に用いる封止樹脂に接する面にはガスバリア膜１２１が形成されたものである。好ましくは、パッド１２２の必要箇所が露出するように、有機物であるソルダーレジスト１２３が形成されており、ソルダーレジスト１２３の表面にはガスバリア膜１２１が形成されたものである。さらに好ましくは、半導体搭載用基板１２０にはパッド１２２を含む導体回路が形成されているとともに、導体回路や絶縁樹脂層が多層構造を有するものであり、封止樹脂に接する面にはガスバリア膜１２１が形成されたものである。より具体的には、ガラスエポキシなどを基材とする銅張積層板を加工して得られるリジッド回路基板、そのようなリジッド回路基板をコア基板として両面あるいは片面にビルドアップ層を形成したビルドアップ基板、絶縁層と導体回路と層間を接続するための導体ポストを有する単層基板を複数枚積層して得られる多層回路基板、ポリイミドなどを基材とするフレキシブル材を加工して得られるフレキシブル回路基板などの各種回路基板を用いて、封止樹脂に接する面にガスバリア膜１２１を形成することで、本発明の半導体搭載用基板１２０を得ることができる。
【００１５】
ガスバリア膜１２１としては、ボイド発生成分の封止樹脂１３０への拡散抑制効果の高い無機物からなることが好ましい。より具体的には、珪素酸化物、ホウ素酸化物、りん酸化物、ナトリウム酸化物、カリウム酸化物、鉛酸化物、チタン酸化物、マグネシウム酸化物、バリウム酸化物などの無機物が挙げられる。また、ガスバリア膜１２１の形成方法としては、プラズマＣＶＤ、熱ＣＶＤ、光ＣＶＤなどのＣＶＤ（化学的気相成長法）や、真空蒸着、スパッタリング、イオンプレーティングなどのＰＶＤ（物理的気相成長法）のようなドライプロセスによるものだけでなく、スプレー、溶射法、ウエット・オン・ウエット法、液相析出法、ゾルゲル法などのウエットプロセスによる方法が挙げられる。
【００１６】
半導体搭載用基板１２０の封止樹脂と接する面の必要箇所にのみに、選択的にガスバリア膜１２１を形成する方法としては、（１）全面にガスバリア膜を形成して、レーザーにより不要箇所のガスバリア膜を除去する方法、（２）全面にガスバリア膜を形成して、その上に感光性レジストを形成して不要箇所のガスバリア膜をエッチングなどにより除去し、最後に感光性レジストを除去する方法、（３）薄膜の感光性レジストを形成しておき、その上に全面ガスバリア膜を形成した後に、感光性レジストを除去する方法、（４）メカニカルマスクを介して、ガスバリア膜を形成することで予め必要箇所にのみガスバリア膜を形成する方法などが挙げられる。
【００１７】
本発明に用いる封止樹脂１３０を構成する樹脂としては、一般的に、加熱工程における最高温度において、流動状態または軟化状態となる特性を有するものであり、常温での状態は任意でよく、流動状態とする以外にも、常温時にフィルム状にして、加熱時に軟化状態とするなどが挙げられる。
これら封止樹脂１３０に用いる樹脂としては、エポキシ、フェノール、ポリイミド、ポリアミドイミドなど、耐熱性と絶縁性が良好な樹脂を用いることができる。さらには、封止樹脂が、表面清浄化機能を有し、かつ、絶縁信頼性の高い樹脂（以下、金属接合樹脂と呼ぶ）であることが好ましい。表面清浄化機能としては、例えば、半田表面やパッド表面に存在する酸化膜の除去機能や、酸化膜の還元機能である。この表面清浄化機能により、半田と接続するための表面との濡れ性が十分に高まり、半田の濡れ拡がりの力により、金属接合部における金属接合樹脂が排除され、金属接合樹脂を用いた金属接合には、樹脂残りが発生しにくく、且つその電気的接続信頼性は高いものとなる。
【００１８】
金属接合樹脂としては、少なくとも１つ以上のフェノール性水酸基を有する樹脂（Ａ）と、その硬化剤として作用する樹脂（Ｂ）とを必須成分する接着剤や、エポキシ樹脂（Ｃ）と、イミダゾール環を有し且つエポキシ樹脂（Ｃ）の硬化剤として作用する化合物（Ｄ）とを必須成分とする接着剤が好ましい。
【００１９】
第１の好ましい金属接合樹脂において、フェノール性水酸基を有する樹脂（Ａ）の、フェノール性水酸基は、その表面清浄化機能により、半田および金属表面の酸化物などの汚れの除去あるいは、酸化物を還元し、金属接合のフラックスとして作用する。更に、その硬化剤として作用する樹脂（Ｂ）により、良好な硬化物を得ることができるため、金属接合後の洗浄除去が必要なく、高温、多湿雰囲気でも電気絶縁性を保持し、接合強度、信頼性の高い金属接合を可能とする。
【００２０】
本発明において第１の好ましい金属接合樹脂に用いる、少なくとも１つ以上のフェノール性水酸基を有する樹脂（Ａ）としては、フェノールノボラック樹脂、アルキルフェノールノボラック樹脂、レゾール樹脂、クレゾールノボラック樹脂および、ポリビニルフェノール樹脂から選ばれるのが好ましく、これらの１種以上を用いることができる。
【００２１】
また、硬化剤として作用する樹脂（Ｂ）としては、エポキシ樹脂やイソシアネート樹脂などが用いられる。具体的にはいずれも、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系やレソルシノール系などのフェノールベースのものや、脂肪族、環状脂肪族や不飽和脂肪族などの骨格をベースとして変性されたエポキシ化合物やイソシアネート化合物が挙げられる。
【００２２】
フェノール性水酸基を有する樹脂（Ａ）は、接合強度と信頼性から、金属接合樹脂中に、２０ｗｔ％以上８０ｗｔ％以下で含まれることが好ましい。更に好ましい上限値は、６０ｗｔ％である。一方、硬化剤として作用する樹脂（Ｂ）は、金属接合樹脂中に、２０ｗｔ％以上８０ｗｔ％以下で含まれることが好ましい。また、金属接合樹脂に、着色料や、硬化触媒、無機充填材、各種のカップリング剤、溶媒などを添加しても良い。
【００２３】
第２の好ましい金属接合樹脂において、化合物（Ｄ）のイミダゾール環は、三級アミンの不対電子に起因する表面清浄化機能により、半田および金属表面の酸化物などの汚れの除去あるいは、酸化膜を還元し、金属接合のフラックスとして作用する。更に、イミダゾール環は、エポキシ樹脂（Ｃ）をアニオン重合する際の硬化剤としても作用するため、良好な硬化物を得ることができ、半田接合後の洗浄除去が必要なく、高温、多湿雰囲気でも電気絶縁性を保持し、接合強度、信頼性の高い金属接合を可能とする。化合物（Ｄ）の添加量は、金属接合の強度や信頼性から１ｗｔ％以上１０ｗｔ％以下であることが好ましい。より好ましい上限値としては５ｗｔ％である。
【００２４】
イミダゾール環を有し且つエポキシ樹脂（Ｃ）の硬化剤として作用する化合物（Ｄ）としては、イミダゾール、２−メチルイミダゾール、２−エチル−４−メチルイミダゾール、２−フェニルイミダゾール、１−ベンジル−２−メチルイミダゾール、２−ウンデシルイミダゾール、２−フェニル−４−メチルイミダゾール、ビス（２−エチル−４−メチル−イミダゾール）、２−フェニル−４−メチル−５−ヒドロキシメチルイミダゾール、２−フェニル−４、５−ジヒドロキシメチルイミダゾール、１−シアノエチル−２−エチル−４−メチルイミダゾール、１−シアノエチル−２−メチルイミダゾール、１−シアノエチル−２−フェニルイミダゾール、あるいはトリアジン付加型イミダゾール等が挙げられる。また、これらをエポキシアダクト化したものや、マイクロカプセル化したものも使用できる。これらは単独で使用しても２種類以上を併用しても良い。
【００２５】
また、化合物（Ｄ）と組合わせて用いるエポキシ樹脂（Ｃ）としては、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系やレソルシノール系などの、フェノールベースのエポキシ樹脂や、脂肪族、環状脂肪族や不飽和脂肪族などの骨格をベースとして変性されたエポキシ化合物が挙げられる。
【００２６】
エポキシ樹脂（Ｃ）の配合量は、金属接合樹脂全体の３０〜９９ｗｔ％が好ましい。３０ｗｔ％未満であると、十分な硬化物が得られなくなる恐れがある。エポキシ樹脂（Ｃ）とその硬化剤として作用する化合物（Ｄ）以外の成分としては、金属接合樹脂に用いる樹脂に、シアネート樹脂、アクリル酸樹脂、メタクリル酸樹脂、マレイミド樹脂等の熱硬化性樹脂や熱可塑性樹脂を配合しても良い。また、金属接合樹脂に、着色料や、硬化触媒、無機充填材、各種のカップリング剤、溶媒などを添加しても良い。
【００２７】
金属接合樹脂の調製方法は、例えば、固形のフェノール性水酸基を有する樹脂（Ａ）と固形の硬化剤として作用する樹脂（Ｂ）を溶媒に溶解して調製する方法、固形のフェノール性水酸基を有する樹脂（Ａ）を液状の硬化剤として作用する樹脂（Ｂ）に溶解して調製する方法、固形の硬化剤として作用する樹脂（Ｂ）を液状のフェノール性水酸基を有する樹脂（Ａ）に溶解して調製する方法、固形のエポキシ樹脂（Ｃ）を溶媒に溶解した溶液に、イミダゾール環を有し且つエポキシ樹脂（Ｃ）の硬化剤として作用する化合物（Ｄ）を分散もしくは溶解する方法、液状のエポキシ樹脂（Ｃ）にイミダゾール環を有し且つエポキシ樹脂（Ｃ）の硬化剤として作用する化合物（Ｄ）を分散もしくは溶解する方法等が挙げられる。
【００２８】
金属接合樹脂の調整に使用する溶媒としては、アセトン、メチルエチルケトン、メチルイソブチルケトン、シクロヘキサノン、トルエン、メシチレン、キシレン、ヘキサン、イソブタノール、ｎ−ブタノール、１−メトキシ，２−プロパノールアセテート、ブチルセルソルブ、エチルセルソルブ、メチルセルソルブ、セルソルブアセテート、乳酸エチル、酢酸エチル、フタル酸ジメチル、フタル酸ジエチル、フタル酸ジブチル、ジエチレングリコール、安息香酸−ｎ−ブチル、Ｎ−メチルピロリドン、Ｎ，Ｎ−ジメチルホルムアミド、テトラヒドロフラン、γ−ブチルラクトン、アニソール等が挙げられる。好ましくは、沸点が２００℃以下の溶媒である。
【００２９】
本発明の半導体装置を製造する方法の例としては、まず、バンプ１１１に対応する位置にパッド１２２が形成された半導体搭載用基板１２０の上に封止樹脂１３０を適量供給し、バンプ１１１とパッド１２２の位置が合うように半導体チップ１１０を位置決めしておく（図１（ａ））。
【００３０】
前記封止樹脂１２０の供給方法としては、封止樹脂１３０が流動状態であれば、ディスペンサにより供給すればよい。封止樹脂１３０がフィルム状であれば、フィルムマウンターなどの加圧・加熱できる装置を用いて、貼り付ければよい。
【００３１】
続いて、半導体チップ１１０を半導体搭載用基板１２０に搭載し、加熱して、バンプ１１１とパッド１２２とを、溶融して、接続させて、半導体装置１００を得る（図１（ｂ））。加熱する温度は、封止樹脂１３０の特性や、バンプ１１１およびパッド１２２の材質などに応じて決めればよい。また、封止樹脂１３０を硬化させるために、さらに加熱工程を加えてもよい。さらには、必要に応じて加圧工程を加えても良い。
【００３２】
加熱する方法としては、半導体装置１００をリフロー炉に入れ、適切な温度プロファイルで処理する方法が挙げられる。特に、バンプ１１１が半田を含む場合には、最高加熱温度が半田の融点以上となるように、温度プロファイルを設定することが好ましい。また、パッド１２２上に半田被膜または半田バンプが形成されている場合には、その半田の融点以上となるような温度プロファイルにて加熱処理することで、半導体チップ１１０に形成されたバンプ１１１の材質に関係なく、その半田被膜または半田バンプにより、半導体チップと半導体搭載用基板との電気的接続を得ることができる。あるいは、フリップチップボンダーなどのように加熱・加圧機構を有する装置を用いて、適切な加熱・加圧条件にてプレスする方法が挙げられる。
【００３３】
図１においては、半導体搭載用基板１２０の表面に封止樹脂１３０を供給した例を示したが、場合によっては、半導体チップ１１０側に封止樹脂１３０を供給しても構わない。あるいは、封止樹脂１３０を単独のフィルム状にすることができるのであれば、半導体チップ１１０と半導体搭載用基板１２０の間にフィルム状の封止樹脂１３０を挟み込んでも構わない。
【００３４】
【発明の効果】
本発明によれば、封止樹脂を介して半導体搭載用基板に半導体チップを実装した半導体装置において、ガスバリア膜の効果により封止樹脂にボイドが発生することがない。
【図面の簡単な説明】
【図１】本発明の実施形態である半導体装置の製造方法の一例を説明するための断面図である。
【符号の説明】
１００：半導体装置
１１０：半導体チップ
１１１：バンプ
１２０：半導体搭載用基板
１２１：ガスバリア膜
１２２：パッド
１２３：ソルダーレジスト
１２４：基材[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor mounting substrate and a semiconductor device. More particularly, the present invention relates to a semiconductor mounting substrate for flip-chip mounting a semiconductor chip via a sealing resin, and a semiconductor device having the semiconductor chip mounted thereon.
[0002]
[Prior art]
In recent years, flip chip mounting has attracted attention as a method for mounting a semiconductor chip on a semiconductor mounting substrate. The flip chip mounting method is to provide a solder pump on a chip electrode, and further, a semiconductor chip having a solder ball on a solder bump is placed face down on a solder bump or a solder land of a wiring pattern of a semiconductor mounting substrate. In this method, soldering is directly performed. In the electrode bonding by the flip-chip mounting method, a C4 (Controlled Collapse Chip Connection) process to which solder bonding is applied is given as a typical method.
[0003]
In the flip chip mounting by the C4 process, the solder joint between the semiconductor chip and the semiconductor mounting substrate is shielded from the external environment and protected, and is generated due to a difference in linear expansion coefficient between the semiconductor chip and the semiconductor mounting substrate. In order to prevent heat stress from concentrating on the solder joints, a resin for sealing the solder joints is filled in the gap between the semiconductor chip and the semiconductor mounting substrate to seal the solder joints.
[0004]
When filling the gap between the semiconductor chip and the semiconductor mounting substrate with the sealing resin for flip chip mounting, the sealing resin filling method widely used in the C4 process includes a capillary flow method and a compression flow method. They are roughly divided into Recently, a compression flow method has attracted attention as a filling method for improving productivity. As an example of the compression flow method, first, a flux agent-containing resin obtained by adding a flux agent to a thermosetting resin is used as a sealing resin for flip chip mounting. In the compression flow method, a flux agent-containing resin obtained by adding a flux agent to a thermosetting resin is applied onto a semiconductor mounting substrate before the semiconductor chip is mounted on the semiconductor mounting substrate. Next, the semiconductor chip is placed on the semiconductor mounting substrate, and at this time, the semiconductor chip is pressed to spread out the coating layer of the thermosetting resin. Next, the semiconductor chip and the semiconductor mounting substrate are placed in a reflow oven, and the solder bumps and the oxide films on the solder balls are removed with a flux agent in the thermosetting resin, and the solder is reflowed and soldered. At the same time, the thermosetting resin filled in the gap between the semiconductor chip and the semiconductor mounting substrate is cured. As a result, the solder bumps of the semiconductor chip and the solder bumps of the semiconductor mounting substrate are soldered to form a solder joint, and the gap between the semiconductor chip and the semiconductor mounting substrate is filled with a sealing resin. Then, the solder joint is sealed (for example, see Patent Document 1).
[0005]
On the other hand, as another flip chip mounting method, a method called a pressure welding method has been receiving attention. The feature of this method is that there is no need to supply a bonding material such as solder or conductive resin, and the sealing of the electrode of the semiconductor element and the pad on the semiconductor mounting board is filled between the semiconductor element and the semiconductor mounting board. Electrical connection is made only by mechanical contact due to the contraction force of the resin. In this method, first, a sealing resin is supplied to a semiconductor element mounting portion on a semiconductor mounting substrate, and a semiconductor element is mounted thereon, and then heated and pressed in this state to cure the sealing resin. The connection between the electrodes is obtained (for example, see Patent Document 2).
[0006]
[Patent Document 1]
JP-A-4-280443 (page 6, FIG. 1, FIG. 2)
[Patent Document 2]
JP-A-9-097816 (page 6, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, in the above-described method, when a semiconductor chip is mounted on a semiconductor mounting substrate, moisture due to moisture absorption contained in the insulating resin of the semiconductor mounting substrate, uncured components of the thermosetting resin included in the insulating resin, and insulation. When the resin contained in the resin is decomposed by heating or the insulating resin contains a cyanate resin, the hydrolysis component of the cyanate resin is diffused into the sealing resin to form voids. This void generation phenomenon is most likely to occur when the sealing resin is in a flowing state or a softened state. However, in order for the sealing resin to exhibit a sealing / adhesion function, the sealing resin is in a flowing state or a softened state. I have to be in a state.
[0008]
An object of the present invention is to provide a semiconductor mounting substrate and a semiconductor device in which voids are not generated in a sealing resin in view of such a current problem in a flip chip mounting method of a semiconductor chip.
[0009]
[Means for Solving the Problems]
That is, the present invention
1. A semiconductor mounting substrate for flip-chip mounting a semiconductor chip having a bump formed thereon via a sealing resin, wherein a pad is formed at a position corresponding to the bump and a surface in contact with the sealing resin. A semiconductor mounting substrate, wherein a gas barrier film is formed on
2. 2. The semiconductor mounting substrate according to claim 1, wherein a gas barrier film is formed on a surface in contact with the sealing resin, except for a portion where the pad is exposed.
3. 3. The semiconductor mounting substrate according to claim 1 or 2, wherein a surface in contact with the sealing resin is made of an organic material and an inorganic material, and a gas barrier film is formed on at least a surface made of the organic material.
4. 4. The semiconductor mounting substrate according to any one of Items 1 to 3, wherein the gas barrier film is made of an inorganic substance.
5. A semiconductor device in which a semiconductor chip on which a bump is formed is flip-chip mounted on a semiconductor mounting substrate according to any one of Items 1 to 4 via a sealing resin.
6. 6. The semiconductor device according to claim 5, wherein the bumps include gold or solder.
7. The semiconductor device according to claim 5 or 6, wherein the sealing resin has a surface cleaning function,
Is provided.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
In the conventional embodiment (not shown), when heated, moisture contained in the insulating resin of the semiconductor mounting substrate due to moisture absorption, uncured components of the thermosetting resin, decomposed components due to heating of the resin, and the like are in a fluid state. Alternatively, the gas may diffuse into the softened sealing resin and become voids. However, in the embodiment of the present invention (see FIG. 1), the gas barrier film 121 causes the void-generating component contained in the semiconductor mounting substrate to be removed. Since the diffusion into the sealing resin 130 is suppressed, no void is generated.
[0011]
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, but the present invention is not limited thereto.
[0012]
FIG. 1 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view illustrating a structure of the obtained semiconductor device. FIG. 1A also shows a cross-sectional view illustrating the structure of the semiconductor mounting substrate of the present invention.
[0013]
The semiconductor chip 110 used in the present invention is formed by forming bumps 111 for electrical connection with pads 122 of a semiconductor mounting substrate on electrodes of the chip. It is preferable that the material of the bumps 111 includes gold which is appropriately deformed by thermocompression bonding to the pads 122 and easily diffuses heat to the pads 122, or solder which can be metal-bonded to the pads 122. As a method of forming the bump 111 containing gold, a stud bump method using a wire bonder or the like may be used in addition to a method using electrolytic plating or electroless plating. As the material of the solder, any material may be used as long as it is a metal that can be metal-bonded to the pad 111. Sn or In, or Sn, Ag, Cu, Zn, Bi, Pd, Sb, Pb, In, or Au may be used. It is preferable to use at least two types of solder. More preferably, it is an environment-friendly Pb-free solder. As a method for forming the bump 111 containing solder, there are a method by vapor deposition, a method of printing a solder paste, and a method of reflowing, in addition to a method by electrolytic plating or electroless plating. On the other hand, when a solder coating or a solder bump is formed on the pad 122, the semiconductor chip and the semiconductor chip are mounted on the semiconductor chip 110 by the solder coating or the solder bump regardless of the material of the bump 111 formed on the semiconductor chip 110. An electrical connection with the substrate can be obtained.
[0014]
The semiconductor mounting substrate 120 of the present invention has pads 122 formed at least at positions corresponding to the bumps of the semiconductor chip on a base material 124 mainly made of an organic material such as an insulating resin, and is used when mounting the semiconductor chip. The gas barrier film 121 is formed on the surface in contact with the sealing resin. Preferably, an organic solder resist 123 is formed so that necessary portions of the pad 122 are exposed, and a gas barrier film 121 is formed on the surface of the solder resist 123. More preferably, a conductor circuit including a pad 122 is formed on the semiconductor mounting substrate 120, and the conductor circuit and the insulating resin layer have a multilayer structure. Is formed. More specifically, a rigid circuit board obtained by processing a copper-clad laminate made of glass epoxy or the like as a base material, a build-up in which such a rigid circuit board is used as a core substrate and a build-up layer is formed on both surfaces or one surface. Substrate, multi-layer circuit board obtained by laminating a plurality of single-layer boards having conductor posts for connecting insulating layers to conductive circuits and layers, flexible circuits obtained by processing flexible materials based on polyimide, etc. The semiconductor mounting substrate 120 of the present invention can be obtained by forming the gas barrier film 121 on the surface in contact with the sealing resin using various circuit substrates such as a substrate.
[0015]
The gas barrier film 121 is preferably made of an inorganic material having a high effect of suppressing the diffusion of the void generation component into the sealing resin 130. More specifically, inorganic substances such as silicon oxide, boron oxide, phosphorus oxide, sodium oxide, potassium oxide, lead oxide, titanium oxide, magnesium oxide, and barium oxide can be used. In addition, as a method for forming the gas barrier film 121, a CVD (chemical vapor deposition) such as plasma CVD, thermal CVD, or optical CVD, or a PVD (physical vapor deposition) such as vacuum deposition, sputtering, or ion plating. ), But also wet processes such as spraying, thermal spraying, wet-on-wet, liquid phase deposition, and sol-gel.
[0016]
The method of selectively forming the gas barrier film 121 only on a necessary portion of the surface of the semiconductor mounting substrate 120 which is in contact with the sealing resin includes the following methods. (2) a method of forming a gas barrier film on the entire surface, forming a photosensitive resist thereon, removing unnecessary portions of the gas barrier film by etching or the like, and finally removing the photosensitive resist; (3) A method in which a thin-film photosensitive resist is formed, a gas barrier film is formed on the entire surface, and then the photosensitive resist is removed. (4) A gas barrier film is formed in advance through a mechanical mask. For example, a method of forming a gas barrier film only at a necessary portion is exemplified.
[0017]
The resin constituting the sealing resin 130 used in the present invention generally has a property of being in a fluidized state or a softened state at the highest temperature in the heating step, and may be in any state at normal temperature. In addition to the state, the film may be formed into a film at normal temperature and may be in a softened state when heated.
As a resin used for the sealing resin 130, a resin having good heat resistance and insulating properties, such as epoxy, phenol, polyimide, and polyamideimide, can be used. Further, it is preferable that the sealing resin is a resin having a surface cleaning function and having high insulation reliability (hereinafter, referred to as a metal bonding resin). The surface cleaning function is, for example, a function of removing an oxide film present on a solder surface or a pad surface or a function of reducing an oxide film. By this surface cleaning function, the wettability with the surface for connection with the solder is sufficiently increased, and the metal bonding resin at the metal bonding portion is eliminated by the spreading force of the solder, and the metal bonding using the metal bonding resin is performed. In this case, resin residue hardly occurs, and the electrical connection reliability is high.
[0018]
Examples of the metal bonding resin include an adhesive or an epoxy resin (C) which essentially comprises a resin (A) having at least one or more phenolic hydroxyl groups and a resin (B) acting as a curing agent thereof, and an imidazole ring. And an adhesive having a compound (D) acting as a curing agent for the epoxy resin (C) as an essential component.
[0019]
In the first preferred metal bonding resin, the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group removes stains such as oxides on solder and metal surfaces or reduces oxides by its surface cleaning function. And acts as a flux for metal bonding. Furthermore, since a good cured product can be obtained by the resin (B) acting as a curing agent, cleaning and removal after metal bonding is not required, and electrical insulation is maintained even in a high-temperature and high-humidity atmosphere. Enables highly reliable metal bonding.
[0020]
The resin (A) having at least one or more phenolic hydroxyl groups used for the first preferred metal bonding resin in the present invention includes a phenol novolak resin, an alkylphenol novolak resin, a resole resin, a cresol novolak resin, and a polyvinyl phenol resin. It is preferable that one or more of these can be used.
[0021]
As the resin (B) acting as a curing agent, an epoxy resin, an isocyanate resin, or the like is used. More specifically, all are based on phenol-based compounds such as bisphenols, phenol novolaks, alkylphenol novolaks, biphenols, naphthols and resorcinols, and skeletons such as aliphatic, cycloaliphatic and unsaturated aliphatics. Examples thereof include modified epoxy compounds and isocyanate compounds.
[0022]
The resin (A) having a phenolic hydroxyl group is preferably contained in the metal bonding resin in an amount of 20% by weight or more and 80% by weight or less from the viewpoint of bonding strength and reliability. A more preferred upper limit is 60 wt%. On the other hand, the resin (B) acting as a curing agent is preferably contained in the metal bonding resin in an amount of 20 wt% or more and 80 wt% or less. Further, a coloring agent, a curing catalyst, an inorganic filler, various coupling agents, a solvent, and the like may be added to the metal bonding resin.
[0023]
In the second preferred metal bonding resin, the imidazole ring of the compound (D) has a surface cleaning function attributable to unpaired electrons of the tertiary amine to remove dirt such as oxides on solder and metal surfaces or to form an oxide film. And acts as a flux for metal bonding. Furthermore, since the imidazole ring also acts as a curing agent when anionically polymerizing the epoxy resin (C), it is possible to obtain a good cured product, and it is not necessary to remove and wash it after soldering. Maintains electrical insulation and enables metal bonding with high bonding strength and high reliability. The addition amount of the compound (D) is preferably 1 wt% or more and 10 wt% or less from the viewpoint of the strength and reliability of metal bonding. A more preferred upper limit is 5 wt%.
[0024]
Examples of the compound (D) having an imidazole ring and acting as a curing agent for the epoxy resin (C) include imidazole, 2-methylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, and 1-benzyl-2. -Methylimidazole, 2-undecylimidazole, 2-phenyl-4-methylimidazole, bis (2-ethyl-4-methyl-imidazole), 2-phenyl-4-methyl-5-hydroxymethylimidazole, 2-phenyl- Examples thereof include 4,5-dihydroxymethylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, and a triazine-added imidazole. Further, those obtained by forming them into epoxy adducts or those obtained by microencapsulation can also be used. These may be used alone or in combination of two or more.
[0025]
Examples of the epoxy resin (C) used in combination with the compound (D) include phenol-based epoxy resins such as bisphenol-based, phenol novolak-based, alkylphenol novolak-based, biphenol-based, naphthol-based and resorcinol-based resins, and aliphatic resins. And epoxy compounds modified on the basis of a skeleton such as a cycloaliphatic or unsaturated aliphatic.
[0026]
The blending amount of the epoxy resin (C) is preferably 30 to 99 wt% of the entire metal bonding resin. If the amount is less than 30 wt%, a sufficient cured product may not be obtained. The components other than the epoxy resin (C) and the compound (D) acting as a curing agent thereof include thermosetting resins such as a cyanate resin, an acrylic resin, a methacrylic resin, and a maleimide resin in addition to the resin used for the metal bonding resin. A thermoplastic resin may be blended. Further, a coloring agent, a curing catalyst, an inorganic filler, various coupling agents, a solvent, and the like may be added to the metal bonding resin.
[0027]
The method for preparing the metal bonding resin is, for example, a method of dissolving a resin (A) having a solid phenolic hydroxyl group and a resin (B) acting as a solid curing agent in a solvent, and having a solid phenolic hydroxyl group. A method in which the resin (A) is prepared by dissolving the resin (B) acting as a liquid curing agent, and the resin (B) acting as a solid curing agent is dissolved in the resin (A) having a liquid phenolic hydroxyl group. A method of dispersing or dissolving a compound (D) having an imidazole ring and acting as a curing agent for the epoxy resin (C) in a solution obtained by dissolving a solid epoxy resin (C) in a solvent; A method of dispersing or dissolving a compound (D) having an imidazole ring in the epoxy resin (C) and acting as a curing agent for the epoxy resin (C), may be mentioned.
[0028]
Solvents used for adjusting the metal bonding resin include acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, toluene, mesitylene, xylene, hexane, isobutanol, n-butanol, 1-methoxy, 2-propanol acetate, butyl cellosolve, Ethyl cellosolve, methyl cellosolve, cellosolve acetate, ethyl lactate, ethyl acetate, dimethyl phthalate, diethyl phthalate, dibutyl phthalate, diethylene glycol, n-butyl benzoate, N-methylpyrrolidone, N, N-dimethylformamide , Tetrahydrofuran, γ-butyllactone, anisole and the like. Preferably, the solvent has a boiling point of 200 ° C. or lower.
[0029]
As an example of the method of manufacturing the semiconductor device of the present invention, first, an appropriate amount of the sealing resin 130 is supplied onto the semiconductor mounting substrate 120 on which the pad 122 is formed at the position corresponding to the bump 111, and the bump 111 and the pad The semiconductor chip 110 is positioned so that the position of 122 is matched (FIG. 1A).
[0030]
As a method of supplying the sealing resin 120, if the sealing resin 130 is in a flowing state, it may be supplied by a dispenser. If the sealing resin 130 is in the form of a film, it may be attached using a device capable of applying pressure and heating such as a film mounter.
[0031]
Subsequently, the semiconductor chip 110 is mounted on the semiconductor mounting substrate 120, heated, and the bumps 111 and the pads 122 are melted and connected to obtain the semiconductor device 100 (FIG. 1B). The heating temperature may be determined according to the characteristics of the sealing resin 130, the materials of the bumps 111 and the pads 122, and the like. Further, in order to cure the sealing resin 130, a heating step may be further added. Further, a pressing step may be added as necessary.
[0032]
As a heating method, there is a method in which the semiconductor device 100 is placed in a reflow furnace and processed with an appropriate temperature profile. In particular, when the bump 111 includes solder, it is preferable to set the temperature profile so that the maximum heating temperature is equal to or higher than the melting point of the solder. In the case where a solder film or a solder bump is formed on the pad 122, the material of the bump 111 formed on the semiconductor chip 110 is subjected to a heat treatment with a temperature profile that is higher than the melting point of the solder. Irrespective of the above, the electrical connection between the semiconductor chip and the semiconductor mounting substrate can be obtained by the solder coating or the solder bump. Alternatively, there is a method in which an apparatus having a heating and pressing mechanism such as a flip chip bonder is used to press under appropriate heating and pressing conditions.
[0033]
Although FIG. 1 shows an example in which the sealing resin 130 is supplied to the surface of the semiconductor mounting substrate 120, the sealing resin 130 may be supplied to the semiconductor chip 110 in some cases. Alternatively, if the sealing resin 130 can be formed into a single film, the film-shaped sealing resin 130 may be interposed between the semiconductor chip 110 and the semiconductor mounting substrate 120.
[0034]
【The invention's effect】
According to the present invention, in a semiconductor device in which a semiconductor chip is mounted on a semiconductor mounting substrate via a sealing resin, no void is generated in the sealing resin due to the effect of the gas barrier film.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[Explanation of symbols]
100: semiconductor device 110: semiconductor chip 111: bump 120: substrate 121 for mounting semiconductor: gas barrier film 122: pad 123: solder resist 124: base material

Claims (7)

バンプが形成された半導体チップを、封止樹脂を介してフリップチップ実装するための半導体搭載用基板であって、前記バンプに対応する位置にパッドが形成されており、前記封止樹脂と接する面にガスバリア膜が形成されていることを特徴とする半導体搭載用基板。A semiconductor mounting substrate for flip-chip mounting a semiconductor chip having a bump formed thereon via a sealing resin, wherein a pad is formed at a position corresponding to the bump and a surface in contact with the sealing resin. A semiconductor mounting substrate, characterized in that a gas barrier film is formed on the substrate. 前記封止樹脂と接する面のうち、前記パッドが露出している部分以外にガスバリア膜が形成されてなる請求項１記載の半導体搭載用基板。2. The semiconductor mounting substrate according to claim 1, wherein a gas barrier film is formed on a portion of the surface in contact with the sealing resin, except for a portion where the pad is exposed. 前記封止樹脂と接する面が有機物および無機物から構成され、少なくとも有機物からなる面にはガスバリア膜が形成されてなる請求項１または２に記載の半導体搭載用基板。3. The semiconductor mounting substrate according to claim 1, wherein a surface in contact with the sealing resin is made of an organic material and an inorganic material, and a gas barrier film is formed on at least a surface made of the organic material. 前記ガスバリア膜が、無機物からなる請求項１〜３のいずれかに記載の半導体搭載用基板。The semiconductor mounting substrate according to claim 1, wherein the gas barrier film is made of an inorganic material. 請求項１〜４のいずれかに記載の半導体搭載用基板に、バンプが形成された半導体チップを、封止樹脂を介してフリップチップ実装した半導体装置。A semiconductor device comprising a semiconductor chip having bumps formed on the semiconductor mounting substrate according to any one of claims 1 to 4 by flip-chip mounting via a sealing resin. 前記バンプが、金または半田を含んでなる請求項５記載の半導体装置。The semiconductor device according to claim 5, wherein the bump includes gold or solder. 前記封止樹脂が、表面清浄化機能を有してなる請求項５または６に記載の半導体装置。The semiconductor device according to claim 5, wherein the sealing resin has a surface cleaning function.
JP2003089065A 2003-03-27 2003-03-27 Substrate for mounting semiconductor and semiconductor device Pending JP2004296917A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007063667A1 (en) * 2005-12-01 2007-06-07 Sharp Kabushiki Kaisha Circuit member, electrode connecting structure and display device provided with such electrode connecting structure
WO2008054011A1 (en) * 2006-10-31 2008-05-08 Sumitomo Bakelite Co., Ltd. Semiconductor electronic component and semiconductor device using the same
JP2014096608A (en) * 2008-11-06 2014-05-22 Sumitomo Bakelite Co Ltd Method of manufacturing electronic device and resin composition

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007063667A1 (en) * 2005-12-01 2007-06-07 Sharp Kabushiki Kaisha Circuit member, electrode connecting structure and display device provided with such electrode connecting structure
JPWO2007063667A1 (en) * 2005-12-01 2009-05-07 シャープ株式会社 Circuit member, electrode connection structure, and display device including the same
US7957151B2 (en) 2005-12-01 2011-06-07 Sharp Kabushiki Kaisha Circuit component, electrode connection structure and display device including the same
JP4820372B2 (en) * 2005-12-01 2011-11-24 シャープ株式会社 Circuit member, electrode connection structure, and display device including the same
WO2008054011A1 (en) * 2006-10-31 2008-05-08 Sumitomo Bakelite Co., Ltd. Semiconductor electronic component and semiconductor device using the same
WO2008054012A1 (en) * 2006-10-31 2008-05-08 Sumitomo Bakelite Co., Ltd. Adhesive tape and semiconductor device using the same
JPWO2008054012A1 (en) * 2006-10-31 2010-02-25 住友ベークライト株式会社 Adhesive tape and semiconductor device using the same
US8319350B2 (en) 2006-10-31 2012-11-27 Sumitomo Bakelite Co., Ltd. Adhesive tape and semiconductor device using the same
JP5182094B2 (en) * 2006-10-31 2013-04-10 住友ベークライト株式会社 Semiconductor electronic component and semiconductor device using the same
US8629564B2 (en) 2006-10-31 2014-01-14 Sumitomo Bakelite Co., Ltd. Semiconductor electronic component and semiconductor device using the same
JP2014096608A (en) * 2008-11-06 2014-05-22 Sumitomo Bakelite Co Ltd Method of manufacturing electronic device and resin composition

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