JP5541157B2 - Mounting substrate, substrate, and manufacturing method thereof - Google Patents

Mounting substrate, substrate, and manufacturing method thereof Download PDF

Info

Publication number
JP5541157B2
JP5541157B2 JP2010516888A JP2010516888A JP5541157B2 JP 5541157 B2 JP5541157 B2 JP 5541157B2 JP 2010516888 A JP2010516888 A JP 2010516888A JP 2010516888 A JP2010516888 A JP 2010516888A JP 5541157 B2 JP5541157 B2 JP 5541157B2
Authority
JP
Japan
Prior art keywords
substrate
layer
metal layer
insulating layer
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010516888A
Other languages
Japanese (ja)
Other versions
JPWO2009151108A1 (en
Inventor
明 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2010516888A priority Critical patent/JP5541157B2/en
Publication of JPWO2009151108A1 publication Critical patent/JPWO2009151108A1/en
Application granted granted Critical
Publication of JP5541157B2 publication Critical patent/JP5541157B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

［関連出願の記載］
本発明は、日本国特許出願：特願２００８−１５４１７５号（２００８年６月１２日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、ベアチップ、ＣＳＰ（Chip Size Package）、ＢＧＡ（Ball Grid Array）などの電子部品を基板に実装した実装基板、及び基板、並びにそれらの製造方法に関し、特に、はんだバンプと導電性接着剤とを用いて電子部品と基板の間の接続を行なった実装基板、及び基板、並びにそれらの製造方法に関する。[Description of related applications]
The present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2008-154175 (filed on June 12, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a mounting substrate on which electronic components such as a bare chip, CSP (Chip Size Package), and BGA (Ball Grid Array) are mounted on a substrate, and a method of manufacturing the same, and in particular, a solder bump and a conductive adhesive. The present invention relates to a mounting board in which an electronic component and a board are connected using the board, a board, and a manufacturing method thereof.

電子機器の急速な発達に伴い、半導体素子にはこれまで以上に高機能化が求められるようになってきている。半導体素子の多機能化に伴い半導体素子の入出力端子数は増加し、また半導体素子を高速動作させるため配線長の短縮化が求められている。こうした要求を実現するために半導体素子と基板の接続方法として、半導体素子と基板をバンプ電極を用いて接続するフリップチップ接続がある。フリップチップ接続は、半導体素子の配線側の面にエリア上に接続パッドを設けることができるため、多ピン化に適している。また、ワイヤボンディングやテープオートメイティッドボンディングの様な他の接続方法と比較して、フリップチップ接続は、引き出し線を必要としないため、配線長の短縮化が可能である。以上のような理由から電子機器に用いられる半導体素子の基板への実装には、フリップチップ接続を使用したものが増加している。   With the rapid development of electronic devices, semiconductor devices are required to have higher functionality than ever. As the number of semiconductor elements increases, the number of input / output terminals of the semiconductor elements increases, and the wiring length is required to be shortened in order to operate the semiconductor elements at high speed. As a method for connecting the semiconductor element and the substrate to realize such a requirement, there is a flip chip connection in which the semiconductor element and the substrate are connected using bump electrodes. The flip chip connection is suitable for increasing the number of pins because a connection pad can be provided on the surface of the semiconductor element on the wiring side. Further, compared to other connection methods such as wire bonding and tape automated bonding, the flip chip connection does not require a lead wire, and therefore the wiring length can be shortened. For the reasons described above, the number of semiconductor devices used in electronic devices using flip chip connection is increasing for mounting on a substrate.

現在、フリップチップ接続に使用される一般的なバンプ電極の材料には、Ａｕやはんだ等が用いられている。はんだの具体例として、Ｓｎ−Ｐｂ共晶はんだがあるが、Ｓｎ−Ｐｂ共晶はんだに限定されず、例えば、Ｓｎ−Ｐｂ（共晶を除く）、Ｓｎ−Ａｇ、Ｓｎ−Ｃｕ、Ｓｎ−Ｚｎ、Ｓｎ−Ｂｉ、及びこれらの材料に特定の添加元素をさらに加えたもの等が挙げられ、目的に応じて材料が適宜選択される。   Currently, Au, solder, or the like is used as a material for a general bump electrode used for flip chip connection. Specific examples of the solder include Sn-Pb eutectic solder, but are not limited to Sn-Pb eutectic solder, for example, Sn-Pb (excluding eutectic), Sn-Ag, Sn-Cu, Sn-Zn. , Sn-Bi, and those obtained by further adding specific additive elements to these materials, and the like, and materials are appropriately selected according to the purpose.

一方、フリップチップ接続される半導体素子の多くは、半導体素子−基板間の熱膨張係数の違いによる応力を緩和するため、半導体素子−基板の隙間を樹脂封止することにより、接続信頼性を確保している。   On the other hand, in many flip-chip connected semiconductor elements, the connection reliability is ensured by resin-sealing the gap between the semiconductor element and the substrate in order to relieve stress due to the difference in thermal expansion coefficient between the semiconductor element and the substrate. doing.

例えば、特許文献１では、突起電極を有する回路素子と基板電極上にはんだを有する回路基板とからなり、該回路素子と回路基板との間に熱硬化性樹脂を介在するフリップチップ接続構造体において、前記突起電極と前記はんだとの金属接合は、前記熱硬化性樹脂の硬化が完了する前に形成されたフリップチップ接続構造体が開示されている（従来例１）。   For example, in Patent Document 1, a flip chip connection structure including a circuit element having a protruding electrode and a circuit board having solder on a substrate electrode, and a thermosetting resin is interposed between the circuit element and the circuit board. In addition, a flip chip connection structure is disclosed in which metal bonding between the protruding electrode and the solder is formed before the curing of the thermosetting resin is completed (conventional example 1).

また、特許文献２では、１個または複数個の半導体チップを搭載したＢＧＡ型半導体装置をはんだで実装するための電極パッド部が形成されているプリント配線基板において、前記電極パッド部２０５が、導電性パッド２０２と、該導電性パッド２０２上に形成された該導電性パッド径よりも小さい突起状の樹脂２０３とを有し、樹脂２０３の表面が、金属薄膜２１０で被覆されているものが開示されている（従来例２；図９参照）。   Further, in Patent Document 2, in a printed wiring board on which an electrode pad part for mounting a BGA type semiconductor device having one or a plurality of semiconductor chips mounted thereon by solder is formed, the electrode pad part 205 is electrically conductive. Having a conductive pad 202 and a protruding resin 203 smaller than the conductive pad diameter formed on the conductive pad 202, and the surface of the resin 203 is covered with a metal thin film 210. (Conventional example 2; see FIG. 9).

さらに、特許文献３では、コア基板３１２の少なくとも片面に導体回路層３２４と絶縁層３２２とが交互に形成され各導体回路層３２４間が前記絶縁層３２２を貫通するスルーホール導体３１８又はバイアホールを介して電気的に接続されると共に実装面に実装される電子部品（ＩＣチップ３５０）が前記導体回路層３２４と電気的に接続されるプリント配線板３１０であって、前記複数の導体回路層３２４のうち外層に最も近い外層導体回路層３２４ａを覆うように形成され前記絶縁性樹脂（絶縁層３２２）よりも弾性率の低い材料からなる応力緩和層３３０と、前記応力緩和層３３０を貫通する貫通孔３３２と、前記貫通孔３３２の内壁に形成されたバリア層３３６と該バリア層３３６の内側に形成されたはんだ製の芯体（はんだ芯体３３７）とからなり前記外層導体回路層３２４ａと前記電子部品（ＩＣチップ３５０）とを電気的に接続する導体ポスト３３４と、を備え、前記導体ポスト３３４は、アスペクト比が１．５以上であるプリント配線板が開示されている（従来例３；図１０参照）。   Further, in Patent Document 3, conductor circuit layers 324 and insulating layers 322 are alternately formed on at least one surface of the core substrate 312, and through-hole conductors 318 or via holes penetrating the insulating layer 322 are formed between the conductor circuit layers 324. An electronic component (IC chip 350) that is electrically connected to the printed circuit board and is mounted on the mounting surface is a printed wiring board 310 that is electrically connected to the conductor circuit layer 324, and includes the plurality of conductor circuit layers 324. A stress relaxation layer 330 made of a material having a lower elastic modulus than that of the insulating resin (insulating layer 322) and covering the outer layer conductor circuit layer 324a closest to the outer layer, and a through hole penetrating the stress relaxation layer 330 A hole 332, a barrier layer 336 formed on the inner wall of the through-hole 332, and a solder core (solder core 3) formed inside the barrier layer 336. 7) and a conductor post 334 that electrically connects the outer conductor circuit layer 324a and the electronic component (IC chip 350), and the conductor post 334 has an aspect ratio of 1.5 or more. A printed wiring board is disclosed (conventional example 3; see FIG. 10).

特開平１１−２３３５５８号公報Japanese Patent Laid-Open No. 11-233558 特開２００４−１１１７５３号公報JP 2004-111753 A 特開２００６−６６５９７号公報JP 2006-66597 A

なお、上記特許文献１から３の全開示内容はその引用をもって本書に繰込み記載する。以下の分析は、本発明によって与えられたものである。
しかしながら、従来例１〜３は、それぞれ次のような問題がある。Note that the entire disclosures of Patent Documents 1 to 3 are incorporated herein by reference. The following analysis is given by the present invention.
However, Conventional Examples 1 to 3 have the following problems.

まず、従来例１（特許文献１）に係るフリップチップ接続構造体では、弾性率が高いはんだバンプ接合部（はんだ）に対し、半導体集積回路素子−回路基板間の熱膨張差により高い応力が発生し、この応力により接合部近傍の素子、バンプ、基板等が破壊されるといった問題がある。この問題を防ぐために、従来例１では、半導体集積回路素子と回路基板の隙間を熱硬化性樹脂（アンダーフィル樹脂）で封止し、はんだバンプにかかる応力を緩和することで接続信頼性を向上させている。ところが、従来例１では、熱硬化性樹脂で封止する工程前に半導体集積回路素子を回路基板に位置決めをして加熱する工程で、半導体集積回路素子−回路基板間の熱膨張差により高い応力が発生し、はんだバンプ接合部に集中的に応力がかかるため、製造工程における応力対策が必要となる。特に、弾性率が高い鉛フリーはんだを適用したり、半導体集積回路素子において機械的強度が低いＬｏｗ−ｋ膜を使用する製品が増えてくると、この問題は一層深刻になる。また、熱硬化性樹脂で封止した後においても、はんだは熱硬化性樹脂の弾性率と比較してはるかに弾性率が高い。例えば、Ａｇ（３ｗｔ％）−Ｃｕ（０．５ｗｔ％）−Ｓｎ（残余）のはんだの弾性率は約４０ＧＰａであるのに対し、熱硬化性樹脂の弾性率は充填剤を混入して高弾性率化した場合でも１０ＧＰａ程度である。このため、弾性率の高いはんだ接合部分に依然として応力が集中して、繰返しの温度変化等により、はんだバンプやその接続部近傍の素子、あるいは基板にクラックが発生するといった問題がある。   First, in the flip-chip connection structure according to Conventional Example 1 (Patent Document 1), a high stress is generated due to a difference in thermal expansion between the semiconductor integrated circuit element and the circuit board with respect to a solder bump joint (solder) having a high elastic modulus. However, there is a problem that elements, bumps, substrates, and the like in the vicinity of the joint are destroyed by this stress. To prevent this problem, Conventional Example 1 improves the connection reliability by sealing the gap between the semiconductor integrated circuit element and the circuit board with a thermosetting resin (underfill resin) and relieving the stress applied to the solder bumps. I am letting. However, in the conventional example 1, in the process of positioning and heating the semiconductor integrated circuit element on the circuit board before the process of sealing with the thermosetting resin, a high stress is caused by the difference in thermal expansion between the semiconductor integrated circuit element and the circuit board. Occurs and stress is concentrated on the solder bump joints, so that it is necessary to take measures against stress in the manufacturing process. In particular, when a lead-free solder having a high elastic modulus is applied or a product using a low-k film having a low mechanical strength in a semiconductor integrated circuit element increases, this problem becomes more serious. Moreover, even after sealing with a thermosetting resin, the solder has a much higher elastic modulus than the elastic modulus of the thermosetting resin. For example, the elastic modulus of the solder of Ag (3 wt%)-Cu (0.5 wt%)-Sn (residue) is about 40 GPa, whereas the elastic modulus of the thermosetting resin is high by mixing the filler. Even when the rate is increased, it is about 10 GPa. For this reason, there is a problem that stress is still concentrated on the solder joint portion having a high elastic modulus, and cracks are generated in the solder bump, the element in the vicinity of the connection portion, or the substrate due to repeated temperature changes.

そこで、バンプ接合部の弾性率を下げる試みとして、従来例２（特許文献２；図９参照）では、絶縁基板２０１側の導電性パッド２０２上に突起状の樹脂２０３を形成し、これにより接合部の応力緩和を図っている。しかしながら、従来例２の構成の場合、絶縁基板２０１側の導電性パッド２０２と突起状の樹脂２０３の接着強度が不足しやすく、基板導電性パッド２０２と突起状の樹脂２０３の接着界面で剥離が発生するといった問題がある。   Therefore, as an attempt to lower the elastic modulus of the bump bonding portion, in Conventional Example 2 (Patent Document 2; see FIG. 9), a protruding resin 203 is formed on the conductive pad 202 on the insulating substrate 201 side, thereby bonding. The stress of the part is reduced. However, in the case of the configuration of Conventional Example 2, the adhesive strength between the conductive pad 202 on the insulating substrate 201 side and the protruding resin 203 tends to be insufficient, and peeling occurs at the bonding interface between the substrate conductive pad 202 and the protruding resin 203. There is a problem that occurs.

また、従来例３（特許文献３；図１０参照）では、多層プリント配線板Ａ上に応力緩和層３３０を形成するとともに、導体ポスト３３４であるはんだ芯体３３７のアスペクト比を制御することで、実装時の応力を緩和している。ところが、実施例３の構成の場合、導体ポスト３３４であるはんだ芯体３３７のアスペクト比の調整に加え、周囲の応力緩和層３３０による応力緩和効果が期待できるが、はんだ芯体３３７は全て弾性率の高いはんだで形成されており、はんだ芯体３３７の接合部近傍には、依然として高い応力が発生する。この構造で応力緩和を実現する際に重要な点は、はんだ芯体３３７の高さをいかに高くして弾性率が高いはんだ芯体３３７をいかに変形しやすくするかということになるが、応力緩和層３３０を厚くして導体ポスト３３４を高くしようとした場合、導体ポスト３３４の形成の際にはんだの充填不良が発生しやすくなり、応力緩和構造と接続信頼性の両立が難しいという問題がある。   Further, in Conventional Example 3 (Patent Document 3; see FIG. 10), by forming the stress relaxation layer 330 on the multilayer printed wiring board A and controlling the aspect ratio of the solder core 337 that is the conductor post 334, The stress at the time of mounting is relieved. However, in the case of the configuration of Example 3, in addition to the adjustment of the aspect ratio of the solder core 337 that is the conductor post 334, the stress relaxation effect by the surrounding stress relaxation layer 330 can be expected. In the vicinity of the joint portion of the solder core body 337, a high stress is still generated. An important point in realizing stress relaxation with this structure is how to increase the height of the solder core 337 to facilitate deformation of the solder core 337 having a high elastic modulus. If the layer 330 is made thicker and the conductor post 334 is made higher, solder filling defects are likely to occur when the conductor post 334 is formed, and there is a problem that it is difficult to achieve both the stress relaxation structure and the connection reliability.

本発明の主な課題は、はんだバンプと導電性接着剤とを用いて電子部品と基板の間の接続を行なった実装基板における前記問題に対して、高信頼性の確保が可能な実装基板、及び基板、並びにそれらの製造方法を提供することである。   The main problem of the present invention is a mounting substrate capable of ensuring high reliability for the above-mentioned problem in the mounting substrate in which the connection between the electronic component and the substrate is performed using the solder bump and the conductive adhesive, And a substrate, and a method of manufacturing the same.

本発明の第１の視点においては、基板において、電極パッドが形成された基板と、前記電極パッドを含む前記基板上に形成された第１絶縁層と、前記第１絶縁層上に形成されるとともに、前記第１絶縁層よりも弾性率が低い応力緩和層と、前記第１絶縁層及び前記応力緩和層に形成されるとともに前記電極パッドに通ずる開口部と、前記開口部に充填されるとともに導電粒子及び樹脂を含んだ導電性接着剤と、前記導電性接着剤の表面に形成された金属層と、を備え、前記第１絶縁層と前記応力緩和層の界面は、前記開口部において前記導電性接着剤と接することを特徴とする。   In a first aspect of the present invention, a substrate is formed on a substrate on which an electrode pad is formed, a first insulating layer formed on the substrate including the electrode pad, and the first insulating layer. And a stress relaxation layer having a lower elastic modulus than the first insulating layer, an opening formed in the first insulating layer and the stress relaxation layer and leading to the electrode pad, and filling the opening. A conductive adhesive containing conductive particles and a resin, and a metal layer formed on a surface of the conductive adhesive, and an interface between the first insulating layer and the stress relaxation layer is the opening in the opening. It is characterized by being in contact with a conductive adhesive.

本発明の第２の視点においては、基板上に電子部品が実装された実装基板であって、前記基板（前記第１の視点の基板）と、電極パッドが形成された電子部品と、前記金属層と、前記電子部品の前記電極パッドとを接合するはんだバンプと、を備えることを特徴とする。   According to a second aspect of the present invention, there is provided a mounting board on which an electronic component is mounted on a board, the board (the board of the first viewpoint), an electronic part on which an electrode pad is formed, and the metal A solder bump for joining the layer and the electrode pad of the electronic component.

本発明の第３の視点においては、基板の製造方法において、電極パッドが形成された基板上に第１絶縁層を形成する工程と、前記第１絶縁層上に前記第１絶縁層よりも弾性率の低い応力緩和層を形成する工程と、前記第１絶縁層及び応力緩和層に、前記電極パッドに通ずる開口部を形成する工程と、前記開口部に樹脂及び導電粒子を含む導電性接着剤を充填する工程と、前記導電性接着剤の表面に前記導電粒子を露出させる工程と、前記導電性接着剤の表面に金属層を形成する工程と、を含むことを特徴とする。   In a third aspect of the present invention, in the method for manufacturing a substrate, a step of forming a first insulating layer on the substrate on which the electrode pad is formed, and a more elastic than the first insulating layer on the first insulating layer A step of forming a stress relaxation layer having a low rate; a step of forming an opening in the first insulating layer and the stress relaxation layer; the conductive adhesive including a resin and conductive particles in the opening; , A step of exposing the conductive particles on the surface of the conductive adhesive, and a step of forming a metal layer on the surface of the conductive adhesive.

本発明の第４の視点においては、実装基板の製造方法において、電子部品の電極パッド上にはんだバンプを形成する工程と、前記電子部品と、前記基板の製造方法によって製造された基板とを位置合わせして、前記基板上に前記電子部品を搭載する工程と、前記はんだバンプを溶融させて、前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程と、を含むことを特徴とする。   In a fourth aspect of the present invention, in a method for manufacturing a mounting substrate, a step of forming solder bumps on electrode pads of an electronic component, the electronic component, and a substrate manufactured by the substrate manufacturing method are positioned. And mounting the electronic component on the substrate, and melting the solder bump to bond the metal layer of the substrate and the electrode pad of the electronic component. It is characterized by.

本発明によれば、電極の一部に低弾性な導電性接着剤を使用しているため、はんだバンプ接合部の応力を緩和した信頼性の高い接続構造を実現できる。また、基板側表層の構造として、第１絶縁層と応力緩和層の２層構造にするとともに第１絶縁層よりも応力緩和層の弾性率を低くしておくことで、導電性接着剤に対しては第１絶縁層と応力緩和層の界面近傍付近に意図的に応力を発生させている。この効果により、基板側の電極パッドと導電性接着剤の接着界面にかかる応力は小さくなるため、実装後の応力による導電性接着剤と基板パッド界面における剥離を抑制し、高い接続信頼性を確保することが可能となる。さらに、応力緩和層と導電性接着剤の弾性率、伸びといった機械的特性を近い値に設計することで、導電性接着剤を含めた応力緩和層は、導電層、絶縁層を問わず一様で、局部的な応力集中が発生しないため、半導体素子や基板の寿命が延び、高信頼な接続を実現できる。   According to the present invention, since a low-elastic conductive adhesive is used for a part of the electrode, a highly reliable connection structure in which the stress at the solder bump joint is relaxed can be realized. In addition, the structure of the substrate side surface layer is a two-layer structure of a first insulating layer and a stress relaxation layer, and the elastic modulus of the stress relaxation layer is lower than that of the first insulating layer. In particular, stress is intentionally generated in the vicinity of the interface between the first insulating layer and the stress relaxation layer. Due to this effect, the stress applied to the bonding interface between the electrode pad on the board side and the conductive adhesive is reduced. Therefore, peeling at the interface between the conductive adhesive and the board pad due to the stress after mounting is suppressed, and high connection reliability is ensured. It becomes possible to do. Furthermore, by designing the mechanical properties such as elastic modulus and elongation of the stress relaxation layer and the conductive adhesive to be close to each other, the stress relaxation layer including the conductive adhesive is uniform regardless of the conductive layer or the insulating layer. Since local stress concentration does not occur, the life of the semiconductor element and the substrate is extended, and a highly reliable connection can be realized.

本発明の実施例１に係る実装基板の構成を模式的に示した部分断面図である。It is the fragmentary sectional view which showed typically the structure of the mounting substrate which concerns on Example 1 of this invention. 本発明の実施例１に係る実装基板の変形例１の構成を模式的に示した部分断面図である。It is the fragmentary sectional view which showed typically the structure of the modification 1 of the mounting substrate which concerns on Example 1 of this invention. 本発明の実施例１に係る実装基板の変形例２の構成を模式的に示した部分断面図である。It is the fragmentary sectional view which showed typically the structure of the modification 2 of the mounting substrate which concerns on Example 1 of this invention. 本発明の実施例１に係る実装基板における導電性接着剤と金属層の状態を示した模式図であり、（Ａ）導電性接着剤の表面に導電粒子の表面に樹脂が被覆された状態、（Ｂ）導電性接着剤の表面に導電粒子が露出した状態、（Ｃ）導電性接着剤と金属層が密着した状態である。It is the schematic diagram which showed the state of the conductive adhesive and metal layer in the mounting substrate which concerns on Example 1 of this invention, (A) The state by which resin was coat | covered on the surface of the conductive particle on the surface of the conductive adhesive, (B) The conductive particles are exposed on the surface of the conductive adhesive, and (C) the conductive adhesive and the metal layer are in close contact with each other. 本発明の実施例１に係る実装基板の製造方法を模式的に示した第１の工程断面図である。It is the 1st process sectional view showing typically the manufacturing method of the mounting board concerning Example 1 of the present invention. 本発明の実施例１に係る実装基板の製造方法を模式的に示した第２の工程断面図である。It is the 2nd process sectional view showing typically the manufacturing method of the mounting board concerning Example 1 of the present invention. 本発明の実施例１に係る実装基板の製造方法を模式的に示した第３の工程断面図である。It is the 3rd process sectional view showing typically the manufacturing method of the mounting board concerning Example 1 of the present invention. 本発明の実施例２に係る実装基板の製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the mounting substrate which concerns on Example 2 of this invention. 従来例２に係るプリント配線基板の構成を模式的に示した断面図である。It is sectional drawing which showed the structure of the printed wiring board concerning the prior art example 2 typically. 従来例３に係るプリント配線板の構成を模式的に示した断面図である。It is sectional drawing which showed the structure of the printed wiring board concerning the prior art example 3 typically.

１ 半導体素子
２ 基板
３ 電極パッド（半導体素子側）
４ 電極パッド（基板側）
５ はんだバンプ
５ａ はんだバンプ（基板側）
５ｂ はんだバンプ（半導体素子側）
６ 導電性接着剤
７ 金属層
８ 第１絶縁層
９ 応力緩和層
１０ 第２絶縁層
１０ａ 絶縁樹脂
１１ 導電粒子
１２ 樹脂
１３ 樹脂最外層
１４ 印刷用マスク
１５ フラックス
１６ 第３絶縁層
２０１ 絶縁基板
２０２ 導電性パッド
２０３ 樹脂
２０５ 電極パッド部
２０７ ソルダレジスト
２１０ 金属薄膜
３１０ プリント配線板
３１２ コア基板
３１４ コア基板本体
３１６ 配線パターン
３１８ スルーホール導体
３２０ ビルドアップ層
３２２ 絶縁層
３２４ 導体回路層
３２４ａ 外層導体回路層
３２６ フィルドビア
３３０ 応力緩和層
３３２ 貫通孔
３３４ 導体ポスト
３３６ バリア層
３３６ａ ランド部
３３７ はんだ芯体
３３８ はんだバンプ部
３４０ 実装面
３４８ はんだバンプ
３５０ ＩＣチップ
３５２ パッド
Ａ 多層プリント配線板
Ｄ 径
ｈ 高さ1 Semiconductor element 2 Substrate 3 Electrode pad (semiconductor element side)
4 Electrode pads (substrate side)
5 Solder bump 5a Solder bump (board side)
5b Solder bump (Semiconductor element side)
6 conductive adhesive 7 metal layer 8 first insulating layer 9 stress relaxation layer 10 second insulating layer 10a insulating resin 11 conductive particles 12 resin 13 resin outermost layer 14 printing mask 15 flux 16 third insulating layer 201 insulating substrate 202 conductive Conductive pad 203 resin 205 electrode pad portion 207 solder resist 210 metal thin film 310 printed wiring board 312 core substrate 314 core substrate body 316 wiring pattern 318 through hole conductor 320 buildup layer 322 insulating layer 324 conductor circuit layer 324a outer layer conductor circuit layer 326 filled via 330 Stress relaxation layer 332 Through hole 334 Conductor post 336 Barrier layer 336a Land portion 337 Solder core body 338 Solder bump portion 340 Mounting surface 348 Solder bump 350 IC chip 352 Pad A Multi-layer printed wiring board D diameter h height

本発明の実施形態に係る基板では、電極パッド（図１の４）が形成された基板（図１の２）と、前記電極パッド（図１の４）を含む前記基板（図１の２）上に形成された第１絶縁層（図１の８）と、前記第１絶縁層（図１の８）上に形成されるとともに、前記第１絶縁層（図１の８）よりも弾性率が低い応力緩和層（図１の９）と、前記第１絶縁層（図１の８）及び前記応力緩和層（図１の９）に形成されるとともに前記電極パッド（図１の４）に通ずる開口部と、前記開口部に充填されるとともに導電粒子及び樹脂を含んだ導電性接着剤（図１の６）と、前記導電性接着剤（図１の６）の表面に形成された金属層（図１の７）と、を備え、前記第１絶縁層（図１の８）と前記応力緩和層（図１の９）の界面は、前記開口部（領域ａ）において前記導電性接着剤（図１の６）と接する（形態１）。
さらに、以下の形態も可能である。
前記導電性接着剤は、前記金属層と接している前記導電性接着剤の表層部において、少なくとも前記導電粒子が前記樹脂の最外層よりも突出しており、前記金属層は、前記樹脂を介することなく前記導電粒子と直接密着していることが好ましい（形態１−１）。
前記金属層は、少なくともＮｉ層を含んでいることが好ましい（形態１−２）。
前記金属層は、前記Ｎｉ層の表面にＡｕ層が形成されていることが好ましい（形態１−３）。
前記応力緩和層上に形成されるとともに、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を備え、前記金属層の表面は、前記第３絶縁層の表面よりも低いことが好ましい（形態１−４）。
前記金属層の表面を覆うように形成されたはんだバンプを備えることが好ましい（形態１−５）。
本発明の実施形態に係る実装基板では、基板上に電子部品が実装された実装基板であって、前記基板と、電極パッドが形成された電子部品と、前記金属層と、前記電子部品の前記電極パッドとを接合するはんだバンプと、を備えることを特徴とする（形態２）。
さらに、以下の形態も可能である。
前記電子部品と前記基板の隙間を封止するとともに、前記応力緩和層よりも弾性率が高い第２絶縁層を備えることが好ましい（形態２−１）。In the substrate according to the embodiment of the present invention, the substrate (2 in FIG. 1) on which the electrode pad (4 in FIG. 1) is formed, and the substrate (2 in FIG. 1) including the electrode pad (4 in FIG. 1). A first insulating layer (8 in FIG. 1) formed thereon and an elastic modulus higher than that of the first insulating layer (8 in FIG. 1) formed on the first insulating layer (8 in FIG. 1). Is formed on the low stress relaxation layer (9 in FIG. 1), the first insulating layer (8 in FIG. 1) and the stress relaxation layer (9 in FIG. 1), and on the electrode pad (4 in FIG. 1). A conductive opening (6 in FIG. 1) filled with the opening and containing conductive particles and a resin, and metal formed on the surface of the conductive adhesive (6 in FIG. 1) 1 (7 in FIG. 1), and the interface between the first insulating layer (8 in FIG. 1) and the stress relaxation layer (9 in FIG. 1) is in the opening (region a). The conductive adhesive in contact with (6 in Fig. 1) (Embodiment 1).
Furthermore, the following forms are also possible.
In the conductive adhesive, in the surface layer portion of the conductive adhesive in contact with the metal layer, at least the conductive particles protrude from the outermost layer of the resin, and the metal layer passes through the resin. It is preferable that the conductive particles are in direct contact with each other (Embodiment 1-1).
The metal layer preferably includes at least a Ni layer (Mode 1-2).
The metal layer preferably has an Au layer formed on the surface of the Ni layer (Embodiment 1-3).
A third insulating layer formed on the stress relieving layer and having an opening so that the metal layer is exposed at a position corresponding to the opening; and the surface of the metal layer has the third insulating layer It is preferable that it is lower than the surface (form 1-4).
It is preferable to provide solder bumps formed so as to cover the surface of the metal layer (Mode 1-5).
The mounting substrate according to the embodiment of the present invention is a mounting substrate in which an electronic component is mounted on the substrate, the electronic component having the electrode pad formed thereon, the metal layer, and the electronic component. And solder bumps for joining the electrode pads (form 2).
Furthermore, the following forms are also possible.
It is preferable that a gap between the electronic component and the substrate is sealed and a second insulating layer having a higher elastic modulus than the stress relaxation layer is provided (Mode 2-1).

本発明の実施形態に係る基板の製造方法では、基板の製造方法において、電極パッド（図５の４）が形成された基板（図５の２）上に第１絶縁層（図５の８）を形成する工程と（図５（Ｂ））、前記第１絶縁層（図５の８）上に前記第１絶縁層（図５の８）よりも弾性率の低い応力緩和層（図５の９）を形成する工程と（図５（Ｃ））、前記第１絶縁層（図５の８）及び応力緩和層（図５の９）に、前記電極パッド（図５の４）に通ずる開口部を形成する工程と（図５（Ｄ））、前記開口部に樹脂及び導電粒子を含む導電性接着剤（図６の６）を充填する工程と（図６（Ｂ））、前記導電性接着剤（図６の６）の表面に前記導電粒子（図４の１１）を露出させる工程と（図４（Ｂ））、前記導電性接着剤（図６の６）の表面に金属層（図６の７）を形成する工程と（図６（Ｃ））、を含む（形態３）。
さらに、以下の形態も可能である。
前記導電粒子を露出させる工程の後であって前記金属層を形成する工程の前に、前記応力緩和層上に、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を形成する工程を含むことが好ましい（形態３−１）。
前記金属層を形成する工程の後に、前記応力緩和層上に、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を形成する工程を含むことが好ましい（形態３−２）。
前記金属層上にはんだバンプを形成する工程を含むことが好ましい（形態３−３）。
本発明の実施形態に係る実装基板の製造方法では、電子部品の電極パッド上にはんだバンプを形成する工程と、前記電子部品と、前記基板の製造方法によって製造された基板とを位置合わせして、前記基板上に前記電子部品を搭載する工程と、前記はんだバンプを溶融させて、前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程と、を含むことを特徴とする（形態４）。
さらに、以下の形態も可能である。
前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程では、前記電子部品側の温度よりも前記基板側の温度を低く保ちながら接合することが好ましい（形態４−１）。
前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程の後に、前記電子部品と前記基板の隙間に第２絶縁層を封入する工程を含むことが好ましい（形態４−２）。
請求項１２記載の基板の製造方法によって製造された基板上に絶縁樹脂を供給する工程と、
本発明の実施形態に係る実装基板の製造方法において、電子部品の電極パッド上にはんだバンプを形成する工程と、前記電子部品と前記基板を位置合わせして、前記基板上に前記電子部品を搭載する工程と、前記はんだバンプを溶融させて、前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程と、を含むことを特徴とする（形態５）。
さらに、以下の形態も可能である。
前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程では、前記電子部品側の温度よりも前記基板側の温度を低く保ちながら接合し、その際、前記絶縁樹脂を硬化することが好ましい（形態５−１）。In the substrate manufacturing method according to the embodiment of the present invention, in the substrate manufacturing method, the first insulating layer (8 in FIG. 5) is formed on the substrate (2 in FIG. 5) on which the electrode pads (4 in FIG. 5) are formed. (FIG. 5B) and a stress relaxation layer (FIG. 5) having a lower elastic modulus than the first insulating layer (8 of FIG. 5) on the first insulating layer (8 of FIG. 5). 9) (FIG. 5C), an opening that communicates with the electrode pad (4 in FIG. 5) in the first insulating layer (8 in FIG. 5) and the stress relaxation layer (9 in FIG. 5). Forming a portion (FIG. 5D), filling the opening with a conductive adhesive (6 in FIG. 6) containing resin and conductive particles (FIG. 6B), the conductive A step of exposing the conductive particles (11 in FIG. 4) on the surface of the adhesive (6 in FIG. 6) (FIG. 4 (B)), and a metal layer (6 in FIG. 6) on the surface Of FIG. ) Forming a (FIG. 6 (C)), including (Embodiment 3).
Furthermore, the following forms are also possible.
After the step of exposing the conductive particles and before the step of forming the metal layer, the metal layer was opened on the stress relaxation layer so as to be exposed at a position corresponding to the opening. It is preferable to include a step of forming a third insulating layer (Mode 3-1).
It is preferable that after the step of forming the metal layer, a step of forming a third insulating layer opened on the stress relaxation layer so as to expose the metal layer at a position corresponding to the opening. (Form 3-2).
It is preferable to include a step of forming solder bumps on the metal layer (Mode 3-3).
In the mounting substrate manufacturing method according to the embodiment of the present invention, the step of forming solder bumps on the electrode pads of the electronic component, the electronic component, and the substrate manufactured by the substrate manufacturing method are aligned. A step of mounting the electronic component on the substrate; and a step of melting the solder bump to join the metal layer of the substrate and the electrode pad of the electronic component. (Form 4)
Furthermore, the following forms are also possible.
In the step of bonding the metal layer of the substrate and the electrode pad of the electronic component, it is preferable to bond while maintaining the temperature on the substrate side lower than the temperature on the electronic component side (Mode 4-1). .
Preferably, after the step of bonding the metal layer of the substrate and the electrode pad of the electronic component, a step of encapsulating a second insulating layer in a gap between the electronic component and the substrate (Mode 4-2) ).
Supplying an insulating resin on the substrate manufactured by the substrate manufacturing method according to claim 12;
In the mounting board manufacturing method according to the embodiment of the present invention, the step of forming solder bumps on the electrode pads of the electronic component, the electronic component and the substrate are aligned, and the electronic component is mounted on the substrate And a step of melting the solder bump and joining the metal layer of the substrate and the electrode pad of the electronic component (mode 5).
Furthermore, the following forms are also possible.
In the step of bonding the metal layer of the substrate and the electrode pad of the electronic component, bonding is performed while keeping the temperature on the substrate side lower than the temperature on the electronic component side, and at that time, the insulating resin is cured It is preferable to perform (Form 5-1).

本発明の実施例１に係る実装基板について図面を用いて説明する。図１は、本発明の実施例１に係る実装基板の構成を模式的に示した部分断面図である。図２は、本発明の実施例１に係る実装基板の変形例１の構成を模式的に示した部分断面図である。図３は、本発明の実施例１に係る実装基板の変形例２の構成を模式的に示した部分断面図である。図４は、本発明の実施例１に係る実装基板における導電性接着剤と金属層の状態を示した模式図であり、（Ａ）導電性接着剤の表面に導電粒子の表面に樹脂が被覆された状態、（Ｂ）導電性接着剤の表面に導電粒子が露出した状態、（Ｃ）導電性接着剤と金属層が密着した状態である。   A mounting substrate according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a partial cross-sectional view schematically showing a configuration of a mounting board according to the first embodiment of the present invention. FIG. 2 is a partial cross-sectional view schematically showing the configuration of Modification 1 of the mounting board according to Embodiment 1 of the present invention. FIG. 3 is a partial cross-sectional view schematically showing the configuration of Modification Example 2 of the mounting board according to Embodiment 1 of the present invention. FIG. 4 is a schematic diagram showing the state of the conductive adhesive and the metal layer in the mounting substrate according to Example 1 of the present invention. (A) The surface of the conductive adhesive is coated with a resin on the surface of the conductive adhesive. (B) a state where conductive particles are exposed on the surface of the conductive adhesive, and (C) a state where the conductive adhesive and the metal layer are in close contact with each other.

図１を参照すると、実装基板は、電子部品となる半導体素子１を基板２上に実装したものである。実装基板では、半導体素子１の電極パッド３と基板２の電極パッド４とがはんだバンプ５と導電性接着剤６を用いて電気的に接続されている。   Referring to FIG. 1, the mounting substrate is obtained by mounting a semiconductor element 1 serving as an electronic component on a substrate 2. On the mounting substrate, the electrode pad 3 of the semiconductor element 1 and the electrode pad 4 of the substrate 2 are electrically connected using the solder bump 5 and the conductive adhesive 6.

基板２の表面には、電極パッド４が形成されている。電極パッド４を含む基板２上には、第１絶縁層８が形成されている。第１絶縁層８上には、応力緩和層９が形成されている。応力緩和層９及び第１絶縁層８には、電極パッド４に通ずる開口部が形成されている。開口部には、導電粒子１１及び樹脂１２を含んだ導電性接着剤６が充填されている。導電性接着剤６の表面には、金属層７が形成されている。金属層７と半導体素子１の電極パッド３とは、はんだバンプ５にて接合されている。応力緩和層９は、第１絶縁層８と比較して弾性率が小さくなっている。   Electrode pads 4 are formed on the surface of the substrate 2. A first insulating layer 8 is formed on the substrate 2 including the electrode pads 4. A stress relaxation layer 9 is formed on the first insulating layer 8. In the stress relaxation layer 9 and the first insulating layer 8, an opening communicating with the electrode pad 4 is formed. The opening is filled with a conductive adhesive 6 containing conductive particles 11 and a resin 12. A metal layer 7 is formed on the surface of the conductive adhesive 6. The metal layer 7 and the electrode pad 3 of the semiconductor element 1 are joined by solder bumps 5. The stress relaxation layer 9 has a smaller elastic modulus than the first insulating layer 8.

半導体素子１は、ＣＳＰ、ＢＧＡ、ベアチップ等いずれの形態でもよく、特に限定されるものではない。電極パッド３の材質は、Ｃｕが一般的である。   The semiconductor element 1 may be in any form such as CSP, BGA, bare chip, and is not particularly limited. The material of the electrode pad 3 is generally Cu.

基板２は、特に制約はなく、ビルドアップ基板でもよいし、セラミック基板でもよい。   The substrate 2 is not particularly limited, and may be a build-up substrate or a ceramic substrate.

電極パッド４の材質は、Ｃｕが一般的である。電極パッド４は、導電性接着剤６との密着強度を確保するために、電極パッド４の表面を数ミクロン程度、粗化しておくことが効果的である。   The material of the electrode pad 4 is generally Cu. In order to ensure the adhesion strength of the electrode pad 4 with the conductive adhesive 6, it is effective to roughen the surface of the electrode pad 4 by several microns.

はんだバンプ５には、例えば、Ｓｎ／Ｐｂ、Ｓｎ／Ａｇ、Ｓｎ／Ｃｕ、Ｓｎ／Ｚｎ、Ｓｎ／Ｂｉ、及びこれら前記した材料に特定の添加元素をさらに加えた材料を用いることができる。はんだバンプ５の形成方法として、例えば、フラックスを含んだはんだペーストをメタルマスク等を使用してパッド上に印刷し、リフローしたのちにフラックス洗浄する方法でもよいし、パッド上に塗布したフラックスにハンダボールを転写して、リフローした後にフラックス洗浄を行なう方法でもよい。   For the solder bump 5, for example, Sn / Pb, Sn / Ag, Sn / Cu, Sn / Zn, Sn / Bi, and a material obtained by further adding a specific additive element to these materials can be used. As a method for forming the solder bump 5, for example, a solder paste containing a flux may be printed on a pad using a metal mask or the like, reflowed and then washed with flux, or solder applied to the flux applied on the pad. A method of performing flux cleaning after transferring the ball and reflowing may be used.

第１絶縁層８には、例えば、熱硬化性のエポキシ樹脂等を用いることができる。第１絶縁層８の形成方法として、例えば、液状の第１絶縁層８をスクリーン印刷法等により基板２の表面に塗布し、加熱硬化によって形成することができる。第１絶縁層８の弾性率は、材質の種類によって差があるが、２〜４ＧＰａが一般的である。第１絶縁層８の厚さは、電極パッド４によって適正な厚さが決定され、電極パッド４の直径を８０〜１３０μｍとした場合、１５〜４０μｍ程度が望ましく、電極間ピッチが大きい場合は、ピッチに合わせて厚みを増した方がよい。   For the first insulating layer 8, for example, a thermosetting epoxy resin or the like can be used. As a method of forming the first insulating layer 8, for example, the liquid first insulating layer 8 can be applied to the surface of the substrate 2 by a screen printing method or the like, and can be formed by heat curing. The elastic modulus of the first insulating layer 8 varies depending on the type of material, but is generally 2 to 4 GPa. When the thickness of the first insulating layer 8 is determined by the electrode pad 4 and the electrode pad 4 has a diameter of 80 to 130 μm, it is preferably about 15 to 40 μm, and when the pitch between the electrodes is large, It is better to increase the thickness according to the pitch.

応力緩和層９は、半導体素子１を基板２上に実装した際に、半導体素子１と基板２の熱膨張差に起因した応力を緩和する役割がある。応力緩和層９の形成範囲は、少なくとも半導体素子１が搭載される領域以上とすることが望ましい。応力緩和層９には、例えば、エポキシ樹脂、シリコーン樹脂等を用いることができ、第１絶縁層８との密着性がよく、さらに応力緩和効果を得るために２％以上の伸び率を有していることが望まれる。従って、密着性と伸び率を両立する目的で、応力緩和層９には、密着性のよいエポキシ樹脂にシリコーン粒子を配合したり、エポキシ樹脂とシリコーン樹脂のハイブリッドタイプの樹脂を用いることもできる。また、応力緩和層９の熱膨張係数や弾性率を調整する目的で、応力緩和層９において、シリカ等の無機フィラーを充填することもできる。応力緩和層９は、厚い方が、応力緩和効果が大きいが、厚すぎると基板２の電極パッド４上の開口部が深くなり、導電性接着剤６の充填が困難になるため、開口部の開口径に合わせて適正な厚さとすることが望ましい。一例としては、開口部が開口径１００μｍの場合、応力緩和層９の厚さは４０〜６０μｍ程度が目安となり、使用する導電性接着剤６の充填性に合わせて、適正な厚さに調整することが望ましい。応力緩和層９の弾性率に関しては、第１絶縁層８よりも小さくする必要がある。その理由は、半導体素子１と基板２の熱膨張差に起因する応力がはんだバンプ５を介して導電性接着剤６にかかった場合、応力緩和層９の弾性率が第１絶縁層８の弾性率より低い場合は、図１に示す領域ａに応力が集中しやすくなり、導電性接着剤６と電極パッド４の界面にかかる応力を緩和することができ、導電性接着剤６の剥離を防止する効果があるからである。   The stress relaxation layer 9 has a role to relieve stress caused by the difference in thermal expansion between the semiconductor element 1 and the substrate 2 when the semiconductor element 1 is mounted on the substrate 2. It is desirable that the stress relaxation layer 9 is formed at least in a region where the semiconductor element 1 is mounted. For example, an epoxy resin, a silicone resin, or the like can be used for the stress relaxation layer 9, which has good adhesion to the first insulating layer 8 and has an elongation of 2% or more in order to obtain a stress relaxation effect. It is hoped that Therefore, in order to achieve both adhesion and elongation, the stress relaxation layer 9 can be blended with epoxy particles having good adhesion, or a hybrid type resin of epoxy resin and silicone resin can be used. Moreover, in order to adjust the thermal expansion coefficient and elastic modulus of the stress relaxation layer 9, the stress relaxation layer 9 can be filled with an inorganic filler such as silica. The thicker the stress relaxation layer 9 is, the greater the stress relaxation effect is. However, if the thickness is too thick, the opening on the electrode pad 4 of the substrate 2 becomes deep and it becomes difficult to fill the conductive adhesive 6. It is desirable to make the thickness appropriate for the opening diameter. As an example, when the opening has an opening diameter of 100 μm, the thickness of the stress relaxation layer 9 is about 40 to 60 μm as a guide, and is adjusted to an appropriate thickness according to the filling property of the conductive adhesive 6 to be used. It is desirable. The elastic modulus of the stress relaxation layer 9 needs to be smaller than that of the first insulating layer 8. The reason is that when the stress due to the thermal expansion difference between the semiconductor element 1 and the substrate 2 is applied to the conductive adhesive 6 via the solder bumps 5, the elastic modulus of the stress relaxation layer 9 is the elasticity of the first insulating layer 8. If the ratio is lower than the rate, the stress tends to concentrate on the region a shown in FIG. 1, the stress applied to the interface between the conductive adhesive 6 and the electrode pad 4 can be relaxed, and the peeling of the conductive adhesive 6 is prevented. This is because there is an effect to do.

電極パッド４上の第１絶縁層８および応力緩和層９に形成された開口部は、レーザを利用して、電極パッド４上の応力緩和層９および第１絶縁層８を選択的に除去することで、容易に形成できる。開口部には、導電性接着剤６が充填されている。   The openings formed in the first insulating layer 8 and the stress relaxation layer 9 on the electrode pad 4 selectively remove the stress relaxation layer 9 and the first insulating layer 8 on the electrode pad 4 using a laser. Therefore, it can be formed easily. The opening is filled with a conductive adhesive 6.

導電性接着剤６は、応力緩和層９と同様に、応力緩和効果を得るために２％以上の伸び率を有していることが望ましい。導電性接着剤６の材料構成は、例えば、エポキシ樹脂、シリコーン樹脂、またはエポキシ樹脂とシリコーン樹脂のハイブリッド樹脂等の樹脂１２に導電粒子１１を含んだものを用いることができる（図４参照）。導電粒子１１には、金属粒子等、導電性を有する様々なものを用いることができるが、導電性に優れるＡｇが一般的であり、その他Ｃｕ等を用いることも可能である。導電粒子１１のサイズ（粒径）は、例えば、１μｍ前後とすることができる。導電粒子１１の形状は、球形やフレーク状とすることができるが、これに限定されない。導電粒子１１の含有量は、５０〜９０ｗｔ％が目安となるが、導電率や弾性率を考慮して決定することが望ましい。一例として、シリコーン系導電性接着剤は、導電粒子（金属フィラー）を８０〜８５ｗｔ％添加した場合でも、弾性率が０．１ＧＰａ以下の低弾性率を実現することができる。   Similarly to the stress relaxation layer 9, the conductive adhesive 6 desirably has an elongation of 2% or more in order to obtain a stress relaxation effect. As the material configuration of the conductive adhesive 6, for example, a resin 12 containing conductive particles 11 such as an epoxy resin, a silicone resin, or a hybrid resin of an epoxy resin and a silicone resin can be used (see FIG. 4). As the conductive particles 11, various conductive materials such as metal particles can be used, but Ag having excellent conductivity is generally used, and Cu or the like can also be used. The size (particle diameter) of the conductive particles 11 can be, for example, around 1 μm. The shape of the conductive particles 11 can be a spherical shape or a flake shape, but is not limited thereto. The content of the conductive particles 11 is 50 to 90 wt% as a standard, but it is desirable to determine the content in consideration of the conductivity and elastic modulus. As an example, the silicone-based conductive adhesive can achieve a low elastic modulus of 0.1 GPa or less even when 80 to 85 wt% of conductive particles (metal filler) are added.

導電性接着剤６の開口部への充填方法は、例えば、開口部に合わせてパターン形成した印刷用マスク（図６（Ａ）の１４参照；メタルマスク）を使用し、印刷法により充填し、所定の温度で硬化させることで導電性接着剤６を形成することができる。この際、導電性接着剤６は、応力緩和層９の表面に対して極端に突出させる必要がないため、印刷用マスクの厚さは極力薄くすることが望ましい。印刷用マスクを薄くすることによって印刷性が良くなるだけでなく、応力緩和層９の表層より突出する導電性接着剤６の高さのバラツキを抑えることができ、生産性が向上する。なお、印刷用マスクについては、上記で示したメタルマスクを使用するほか、応力緩和層９のさらに上に、剥離可能な樹脂マスクを形成しておき、電極部の開口形成時に同時に加工して導電性接着剤６の硬化後に前記樹脂マスクを剥離することで、形成することも可能である。なお、樹脂マスクの剥離に関しては、金属層７を形成した後でもよい。   The method of filling the opening with the conductive adhesive 6 is, for example, using a printing mask (see 14 in FIG. 6A; metal mask) patterned in accordance with the opening, and filling by a printing method. The conductive adhesive 6 can be formed by curing at a predetermined temperature. At this time, since the conductive adhesive 6 does not have to be extremely protruded from the surface of the stress relaxation layer 9, it is desirable to make the thickness of the printing mask as thin as possible. By making the printing mask thinner, not only printability is improved, but also variation in the height of the conductive adhesive 6 protruding from the surface layer of the stress relaxation layer 9 can be suppressed, and productivity is improved. As for the printing mask, in addition to using the metal mask shown above, a detachable resin mask is formed on the stress relaxation layer 9 and processed at the same time as the opening of the electrode portion is formed. It is also possible to form by peeling off the resin mask after curing of the adhesive 6. Note that the resin mask may be peeled after the metal layer 7 is formed.

導電性接着剤６の形状は、望ましくは、応力緩和層９表面上に形成された導電性接着剤６の端部が応力緩和層９の開口部と同じサイズでも大きく形成されていてもよい。同じサイズの場合は、導電性接着剤６の充填性を考慮して開口径を大きくする場合に適しており、この場合、開口径が大きくても、隣り合うはんだバンプ５との距離を保てるため、実装時にバンプ間のショートの問題が発生しにくい。導電性接着剤６の端部を応力緩和層９の開口より大きくした場合のメリットは、導電性接着剤６の一部が応力緩和層９の表面と密着しているため、導電性接着剤６の表面に金属層７を形成するメッキ工程において、メッキ液が導電性接着剤６と電極パッド４の接合界面に浸透しにくくなり、メッキ液の影響による導電性接着剤６と電極パッド４の接合界面における密着力低下や導通抵抗上昇等の悪影響の抑制に効果的であり、メッキ液の選定自由度が増す。さらには、導電性接着剤６の接着面積が増えることにより、導電性接着剤６の密着力を向上させることができる。どちらの構造を選定するかについては、対象となる半導体素子１の電極パッド３のピッチや使用する材料によって、それぞれ選定することが望ましい。また、前記それぞれの構造のメリットを両立できる構造の例として、図２に示す構造が挙げられる。本構造は、導電性接着剤６の端部を応力緩和層９の開口よりも大きく形成しておき、導電性接着剤６の表面に金属層７を形成した後、第３絶縁層１６を形成するとともに、第３絶縁層１６の開口径を調整することで、導電性接着剤６の接着面積を広げつつ、はんだバンプ５での接合時の濡れ広がりを制御し隣接バンプ間ショートを防止することが可能となる。なお、第３絶縁層１６を形成する工程は、金属層７形成後（図２に図示の場合）でも、第３絶縁層１６を形成した後に金属層７を形成でもよい。この場合、第３絶縁層１６の開口部のみに金属層７が形成される。接合部の強度を確保したい場合は、図２に図示する構造が適しており、生産性を考慮する場合は、第３絶縁層１６を形成した後に金属層７を形成するプロセスが適しており、対象となる半導体素子の仕様により、使い分けることが望ましい。   The shape of the conductive adhesive 6 may desirably be formed so that the end portion of the conductive adhesive 6 formed on the surface of the stress relaxation layer 9 is the same size or larger than the opening of the stress relaxation layer 9. In the case of the same size, it is suitable for increasing the opening diameter in consideration of the filling property of the conductive adhesive 6. In this case, the distance between the adjacent solder bumps 5 can be maintained even if the opening diameter is large. The problem of shorting between bumps is less likely to occur during mounting. The merit when the end portion of the conductive adhesive 6 is made larger than the opening of the stress relaxation layer 9 is that a part of the conductive adhesive 6 is in close contact with the surface of the stress relaxation layer 9. In the plating process for forming the metal layer 7 on the surface of the metal, the plating solution is less likely to penetrate the bonding interface between the conductive adhesive 6 and the electrode pad 4, and the bonding between the conductive adhesive 6 and the electrode pad 4 due to the influence of the plating solution. This is effective in suppressing adverse effects such as a decrease in adhesion at the interface and an increase in conduction resistance, and the degree of freedom in selecting a plating solution is increased. Furthermore, the adhesive force of the conductive adhesive 6 can be improved by increasing the bonding area of the conductive adhesive 6. Which structure is to be selected is preferably selected according to the pitch of the electrode pads 3 of the target semiconductor element 1 and the material to be used. Moreover, the structure shown in FIG. 2 is mentioned as an example of the structure which can make the merit of each said structure compatible. In this structure, the end of the conductive adhesive 6 is formed larger than the opening of the stress relaxation layer 9, the metal layer 7 is formed on the surface of the conductive adhesive 6, and then the third insulating layer 16 is formed. At the same time, by adjusting the opening diameter of the third insulating layer 16, the adhesion area of the conductive adhesive 6 is widened and the wetting and spreading at the time of joining with the solder bumps 5 is controlled to prevent a short circuit between adjacent bumps. Is possible. The step of forming the third insulating layer 16 may be performed after the metal layer 7 is formed (in the case shown in FIG. 2) or after the third insulating layer 16 is formed. In this case, the metal layer 7 is formed only in the opening of the third insulating layer 16. The structure shown in FIG. 2 is suitable when it is desired to ensure the strength of the joint, and when considering the productivity, the process of forming the metal layer 7 after forming the third insulating layer 16 is suitable. It is desirable to use properly depending on the specifications of the target semiconductor element.

金属層７については、導電性接着剤６の表面にＮｉ層、Ｎｉ層表面にＡｕ層が形成されている構造が望ましい。Ｎｉ層を形成する理由は、導電性接着剤６中に含まれているＡｇ等の導電粒子（図４の１１）がはんだバンプ５中に含まれているＳｎに取り込まれて消失し、導電性接着剤６中の金属粒子密度が低下することで、導通不良を引き起こす不具合を防止するバリア層としての役割がある。Ｎｉ層の厚さは、３μｍ程度が目安となる。Ａｕ層に関しては、半導体素子１と基板２を接続する際に、はんだバンプ５と金属層７の濡れ性を良好に保つための役割がある。Ａｕ層の厚さは、０．０２〜０．０５μｍ程度とすることができる。金属層７の形成方法として、例えば、無電解メッキにより形成することが可能である。この際に重要な点として、通常、導電性接着剤６を硬化したのみの状態では、図４（Ａ）に示すように、導電粒子１１の表面には、樹脂１２の薄膜が形成され、無電解メッキによる金属層の良好な形成自体が困難である。また、金属層が形成できたとしても、樹脂１２の薄膜の影響で良好な導通が得られない。そこで、図４（Ｂ）に示すように少なくとも樹脂最外層１３よりも突出した導電粒子１１の表面の樹脂１２を除去することで、導電粒子１１を露出させることが望ましく、この状態で無電解メッキ処理を行うことで、図４（Ｃ）に示すように導電粒子１１の表面と金属層７を直接密着させることが可能となり、強固で安定した金属層の形成及び良好な導通を得ることが可能となる。導電粒子１１を露出させる方法として、例えば、導電性接着剤６の表面に適正な条件のアルゴンや酸素によるプラズマ処理を施したり、酸やアルカリの薬液に適正な時間浸漬させる等が挙げられる。金属層７の表面は、はんだバンプ５で覆われており、はんだバンプ５が濡れ広がって強固に接続されている。これにより、半導体素子１と基板２の電極間は低応力かつ良好な電気的導通を得ることができる。   The metal layer 7 preferably has a structure in which a Ni layer is formed on the surface of the conductive adhesive 6 and an Au layer is formed on the surface of the Ni layer. The reason for forming the Ni layer is that conductive particles such as Ag (11 in FIG. 4) contained in the conductive adhesive 6 are taken in by Sn contained in the solder bumps 5 and disappear. Since the metal particle density in the adhesive 6 is lowered, it has a role as a barrier layer for preventing a failure that causes poor conduction. As a guideline, the thickness of the Ni layer is about 3 μm. The Au layer plays a role in maintaining good wettability between the solder bump 5 and the metal layer 7 when connecting the semiconductor element 1 and the substrate 2. The thickness of the Au layer can be about 0.02 to 0.05 μm. For example, the metal layer 7 can be formed by electroless plating. In this case, as an important point, normally, in a state where the conductive adhesive 6 is only cured, a thin film of resin 12 is formed on the surface of the conductive particles 11 as shown in FIG. Good formation of the metal layer by electrolytic plating is difficult. Even if a metal layer can be formed, good conduction cannot be obtained due to the influence of the resin 12 thin film. Therefore, it is desirable to expose the conductive particles 11 by removing the resin 12 on the surface of the conductive particles 11 protruding from at least the resin outermost layer 13 as shown in FIG. 4B. In this state, the electroless plating is performed. By performing the treatment, as shown in FIG. 4C, the surface of the conductive particle 11 and the metal layer 7 can be directly adhered, and formation of a strong and stable metal layer and good conduction can be obtained. It becomes. Examples of the method for exposing the conductive particles 11 include performing plasma treatment with argon or oxygen under appropriate conditions on the surface of the conductive adhesive 6, or immersing in an acid or alkali chemical solution for an appropriate time. The surface of the metal layer 7 is covered with the solder bumps 5, and the solder bumps 5 are spread and are firmly connected. Thereby, low stress and good electrical continuity can be obtained between the electrodes of the semiconductor element 1 and the substrate 2.

なお、バンプピッチが微細である場合等は、バンプ接合部を保護する目的で、図３に示すように、接合部の周囲、つまり半導体素子１と基板２との隙間を第２絶縁層１０にて封止することが望ましい。この場合、応力緩和層９は第２絶縁層１０と比較して弾性率を小さくする。   When the bump pitch is fine, etc., for the purpose of protecting the bump bonding portion, the periphery of the bonding portion, that is, the gap between the semiconductor element 1 and the substrate 2 is formed in the second insulating layer 10 as shown in FIG. It is desirable to seal. In this case, the stress relaxation layer 9 has a smaller elastic modulus than the second insulating layer 10.

第２絶縁層１０には、例えば、アクリル樹脂、メラミン樹脂、エポキシ樹脂、ポリオレフィン樹脂、ポリウレタン樹脂、ポリカーボネート樹脂、ポリスチレン樹脂、ポリエーテル樹脂、ポリアミド樹脂、ポリイミド樹脂、フッ素樹脂、ポリエステル樹脂、フェノール樹脂、フルオレン樹脂、ベンゾシクロブテン樹脂、シリコーン樹脂等、様々な材料を用いることができるが、特に限定されるものではなく、これらを１種あるいは２種以上組み合わせて用いることもできる。粘度、コスト、耐熱性、接着性等の面に優れるエポキシ樹脂が一般に用いられるが、２５℃程度の室温において液状である樹脂が望ましい。この場合、第２絶縁層１０の弾性率が応力緩和層９より高いことが望ましい。その理由は、第２絶縁層１０は、はんだバンプ５を保護する役割があるため、弾性率が高いほうが高弾性であるはんだバンプ５の保護性が良く、高信頼性を確保しやすいからである。本構造の場合、第２絶縁層１０の弾性率を高くした場合でも、応力緩和層９及び導電性接着剤６の低弾性効果により低応力実装構造を実現でき、第２絶縁層１０の高弾性化による接続信頼性向上と実装後の低応力構造の両立を実現できる。なお、第２絶縁層１０にはシリカ等の無機フィラーやアクリル、シリコーン等の有機フィラーを添加し、熱膨張係数や弾性率、熱時物性等を調整することができる。   Examples of the second insulating layer 10 include acrylic resin, melamine resin, epoxy resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluorine resin, polyester resin, phenol resin, Various materials such as a fluorene resin, a benzocyclobutene resin, and a silicone resin can be used, but the material is not particularly limited, and these can be used alone or in combination of two or more. Epoxy resins that are excellent in terms of viscosity, cost, heat resistance, adhesiveness, and the like are generally used, but resins that are liquid at room temperature of about 25 ° C. are desirable. In this case, it is desirable that the elastic modulus of the second insulating layer 10 is higher than that of the stress relaxation layer 9. The reason is that since the second insulating layer 10 has a role of protecting the solder bumps 5, the higher the elastic modulus, the better the protection of the solder bumps 5 having higher elasticity, and it is easy to ensure high reliability. . In the case of this structure, even when the elastic modulus of the second insulating layer 10 is increased, a low-stress mounting structure can be realized by the low elastic effect of the stress relaxation layer 9 and the conductive adhesive 6, and the high elasticity of the second insulating layer 10. This makes it possible to achieve both improved connection reliability and low stress structure after mounting. It should be noted that an inorganic filler such as silica or an organic filler such as acrylic or silicone can be added to the second insulating layer 10 to adjust the thermal expansion coefficient, elastic modulus, hot physical properties, and the like.

次に、本発明の実施例１に係る実装基板の製造方法について図面を用いて説明する。図５〜図７は、本発明の実施例１に係る実装基板の製造方法を模式的に示した工程断面図である。   Next, a method for manufacturing a mounting board according to the first embodiment of the present invention will be described with reference to the drawings. 5-7 is process sectional drawing which showed typically the manufacturing method of the mounting substrate which concerns on Example 1 of this invention.

まず、基板２を用意する（ステップＡ１；図５（Ａ）参照）。基板２は、既に電極パッド４が形成されたものでよく、電極パッド４の表面は、導電性接着剤（図１の６）の密着強度を向上する目的で、数ミクロン程度、粗化しておくことが望ましい。基板２の材質は特に制約は無く、ビルドアップ基板でもよいし、セラミック基板でもよい。   First, the substrate 2 is prepared (Step A1; see FIG. 5A). The substrate 2 may be one in which the electrode pad 4 has already been formed, and the surface of the electrode pad 4 is roughened by several microns for the purpose of improving the adhesion strength of the conductive adhesive (6 in FIG. 1). It is desirable. The material of the substrate 2 is not particularly limited, and may be a build-up substrate or a ceramic substrate.

次に、電極パッド４を含む基板２上に第１絶縁層８を形成する（ステップＡ２；図５（Ｂ）参照）。   Next, the first insulating layer 8 is formed on the substrate 2 including the electrode pads 4 (step A2; see FIG. 5B).

次に、第１絶縁層８上に応力緩和層９を形成する（ステップＡ３；図５（Ｃ）参照）。応力緩和層９の形成範囲は、第１絶縁層８上を全て覆う必要はないが、少なくとも半導体素子（図１の１）が搭載される領域以上とすることが望ましい。   Next, the stress relaxation layer 9 is formed on the first insulating layer 8 (step A3; see FIG. 5C). The formation range of the stress relaxation layer 9 does not have to cover the entire first insulating layer 8, but is preferably at least the region where the semiconductor element (1 in FIG. 1) is mounted.

次に、電極パッド４上の第１絶縁層８及び応力緩和層９を所定の寸法にて選択的に除去し、電極パッド４に通ずる開口部を形成する（ステップＡ４；図５（Ｄ）参照）。第１絶縁層８及び応力緩和層９の除去方法は、基板のビア加工時にも広く利用されているレーザを用いた穴あけ加工法が適している。   Next, the first insulating layer 8 and the stress relaxation layer 9 on the electrode pad 4 are selectively removed with predetermined dimensions to form an opening that leads to the electrode pad 4 (step A4; see FIG. 5D). ). As a method for removing the first insulating layer 8 and the stress relieving layer 9, a drilling method using a laser that is widely used also when processing a via of a substrate is suitable.

次に、応力緩和層９の開口部に合わせて設計された印刷用マスク１４を準備し、印刷用マスク１４を基板２と位置合わせする（ステップＡ５；図６（Ａ）参照）。印刷用マスク１４の一例として、基板２の開口に合わせて穴あけ加工されているメタルマスクが挙げられる。   Next, a printing mask 14 designed in accordance with the opening of the stress relaxation layer 9 is prepared, and the printing mask 14 is aligned with the substrate 2 (step A5; see FIG. 6A). As an example of the printing mask 14, a metal mask that has been drilled in accordance with the opening of the substrate 2 can be cited.

次に、印刷用マスク１４を基板２に位置合わせした状態で、未硬化（ペースト状）の導電性接着剤６を基板２の電極パッド４上の開口部に充填し、導電性接着剤６が硬化した後、印刷用マスク１４を除去する（ステップＡ６；図６（Ｂ）参照）。この時、導電性接着剤６の上端部を応力緩和層９の開口部より大きくしたい場合は、使用する印刷用マスク１４の開口径を応力緩和層９の開口径よりも大きく設計しておくことで、印刷後に形成された導電性接着剤６の上端部を応力緩和層９の開口径よりも大きくすることができる。この際に使用する印刷機は、一般的なものでも良いが、導電性接着剤６の充填時にボイド等の充填不良を未然に防ぐ目的で、真空中で印刷充填したり、導電性接着剤６ペースト充填時に加圧しながら印刷する方法等を用いることができる。また、導電性接着剤６を充填後、導電性接着剤６を硬化する前に真空脱泡する方法、あるいは加圧硬化する方法などにより、充填時に発生したボイドを低減することができる。導電性接着剤６は、使用する樹脂（図４の１２）に適した硬化条件に従い、導電性接着剤６の硬化を行う。硬化に際してはオーブンやホットプレート等を用いることができる。   Next, in a state where the printing mask 14 is aligned with the substrate 2, an uncured (paste-like) conductive adhesive 6 is filled in the opening on the electrode pad 4 of the substrate 2, and the conductive adhesive 6 After curing, the printing mask 14 is removed (step A6; see FIG. 6B). At this time, when the upper end portion of the conductive adhesive 6 is desired to be larger than the opening portion of the stress relaxation layer 9, the opening diameter of the printing mask 14 to be used is designed to be larger than the opening diameter of the stress relaxation layer 9. Thus, the upper end portion of the conductive adhesive 6 formed after printing can be made larger than the opening diameter of the stress relaxation layer 9. The printing machine used at this time may be a general one, but for the purpose of preventing filling defects such as voids when the conductive adhesive 6 is filled, printing and filling in a vacuum or the conductive adhesive 6 is performed. A method of printing while applying pressure when filling the paste can be used. Moreover, after filling with the conductive adhesive 6, voids generated during filling can be reduced by a method of vacuum degassing before the conductive adhesive 6 is cured or a method of pressure curing. The conductive adhesive 6 cures the conductive adhesive 6 according to curing conditions suitable for the resin to be used (12 in FIG. 4). An oven or a hot plate can be used for curing.

次に、導電性接着剤６の表面に金属層７を無電解メッキにより形成する（ステップＡ７；図６（Ｃ）参照）。なお、金属層７を形成する前に、導電性接着剤６の導電粒子１１の表面の樹脂１２を除去することで導電粒子１１を露出させ、導電性接着剤６の表面への無電解メッキ形成性を向上させることが望ましい（図４参照）。一例として、導電性接着剤６の表面にプラズマ処理を施したり、酸やアルカリの薬液に浸漬させることで、導電性接着剤６の表面の導電粒子１１を露出させることができる。このメッキの前処理条件は、使用する導電性接着剤６によって適正条件に差があるため、使用する導電性接着剤６に合わせた前処理条件の調整が必要となるが、メッキ形成性が確保できれば、前処理時間はなるべく短い方がよい。この後、Ｎｉメッキ、Ａｕメッキの順に金属層７を形成するが、通常の無電解メッキプロセスを使用することで、金属層７を形成することが可能である。   Next, a metal layer 7 is formed on the surface of the conductive adhesive 6 by electroless plating (step A7; see FIG. 6C). Before forming the metal layer 7, the conductive particles 11 are exposed by removing the resin 12 on the surface of the conductive particles 11 of the conductive adhesive 6, thereby forming electroless plating on the surface of the conductive adhesive 6. It is desirable to improve the property (see FIG. 4). As an example, the conductive particles 11 on the surface of the conductive adhesive 6 can be exposed by performing plasma treatment on the surface of the conductive adhesive 6 or immersing the surface in the chemical solution of acid or alkali. The plating pretreatment conditions vary depending on the conductive adhesive 6 to be used. Therefore, it is necessary to adjust the pretreatment conditions according to the conductive adhesive 6 to be used, but the plating formability is ensured. If possible, the preprocessing time should be as short as possible. Thereafter, the metal layer 7 is formed in the order of Ni plating and Au plating. However, the metal layer 7 can be formed by using a normal electroless plating process.

次に、基板２の金属層７表面にはんだバンプ５ａを形成する（ステップＡ８；図６（Ｄ）参照）。なお、図６（Ｃ）に示した状態で、半導体素子（図７（Ａ）の１）側に形成したはんだバンプ（図７（Ａ）の５ｂ）と金属層７を接続することは可能であるが、実装後の半導体素子１と基板２の隙間をなるべく広く保ちたい場合は、基板２の金属層７表面にはんだバンプ５ａを形成することが効果的である。実装後の半導体素子１と基板２の隙間を保つ理由は、半導体素子１のはんだバンプ接合後のフラックス（図７（Ｂ）の１５）の洗浄工程、第２絶縁層（図７（Ｄ）の１０）の充填工程において、隙間が狭いとフラックス洗浄不良や第２絶縁層１０の充填時の不良を防ぐほか、はんだバンプの高さを保つことで、接合時の不良防止、さらには構造的に応力を低減するためである。はんだバンプ５ａの形成方法は、例えば、メタルマスク印刷法によりはんだペーストを金属層７上に選択的に印刷した後、リフローして、基板２側の金属層７にはんだを濡れ広げることではんだバンプ５ａを形成し、最後にはんだペーストに含まれているフラックスを洗浄することで、図６（Ｄ）に示した基板２が完成する。   Next, solder bumps 5a are formed on the surface of the metal layer 7 of the substrate 2 (step A8; see FIG. 6D). In the state shown in FIG. 6C, the solder bump (5b in FIG. 7A) formed on the semiconductor element (1 in FIG. 7A) side and the metal layer 7 can be connected. However, when it is desired to keep the gap between the semiconductor element 1 and the substrate 2 after mounting as wide as possible, it is effective to form solder bumps 5 a on the surface of the metal layer 7 of the substrate 2. The reason why the gap between the semiconductor element 1 and the substrate 2 after mounting is maintained is that the flux (15 in FIG. 7B) after the solder bump bonding of the semiconductor element 1 is washed, the second insulating layer (FIG. 7D) 10) In the filling process, if the gap is narrow, in addition to preventing flux cleaning failure and failure during filling of the second insulating layer 10, the solder bump height is maintained to prevent failure during bonding, and structurally This is to reduce the stress. The solder bump 5a is formed by, for example, selectively printing a solder paste on the metal layer 7 by a metal mask printing method, reflowing, and spreading the solder on the metal layer 7 on the substrate 2 side. The substrate 2 shown in FIG. 6D is completed by forming 5a and finally cleaning the flux contained in the solder paste.

次に、予めはんだバンプ５ｂが形成された半導体素子１を準備し、はんだバンプ５ｂにフラックス１５を塗布する（ステップＡ９；図７（Ａ）参照）。はんだバンプ５ｂの形成方法として、例えば、メタルマスクを用いてはんだペーストを電極パッド３上に印刷し、リフロー後にフラックス洗浄する方法でも良いし、他の方法としてはスクリーンマスク等によってフラックス供給した半導体素子１の電極パッド３上に所定のサイズのはんだボールを転写した後、リフローし、フラックス洗浄する方法でもよい。フラックス１５の塗布方法として、スキージ等を用いて所定の厚さに形成したフラックス１５にはんだバンプ５ｂを転写する方法が一般的であるが、特にこの方法に限定されない。また、ここでは、半導体素子１のはんだバンプ５ｂにフラックス１５を塗布した例を示しているが、基板２側にフラックスを転写してもよい。   Next, the semiconductor element 1 on which the solder bumps 5b are formed in advance is prepared, and the flux 15 is applied to the solder bumps 5b (Step A9; see FIG. 7A). As a method for forming the solder bump 5b, for example, a solder paste may be printed on the electrode pad 3 using a metal mask, and flux cleaning may be performed after reflow. Alternatively, a semiconductor element supplied with flux by a screen mask or the like may be used. Alternatively, a method may be used in which a solder ball having a predetermined size is transferred onto one electrode pad 3 and then reflowed and flux cleaned. As a method of applying the flux 15, a method of transferring the solder bumps 5b to the flux 15 formed to a predetermined thickness using a squeegee or the like is common, but is not particularly limited to this method. In this example, the flux 15 is applied to the solder bumps 5b of the semiconductor element 1, but the flux may be transferred to the substrate 2 side.

次に、半導体素子１を基板２（ステップＡ１〜Ａ８で製造したもの）と位置合わせした後、半導体素子１を基板２上に搭載し、半導体素子１側のはんだバンプ５ｂまたは基板２側のはんだバンプ５ａの少なくとも一方を溶融させて半導体素子１の電極パッド３と基板２の電極パッド４とを電気的に接続する（ステップＡ１０；図７（Ｂ）参照）。ここで、はんだバンプ５をリフローする方法としては、リフロー炉等を用いた全体加熱でも可能であるが、半導体素子１側のみからの部分加熱により、基板２の温度がなるべく上がらないようにする方法が望ましい。その理由は、熱膨張係数の大きい基板２側の温度上昇を抑えることにより、実装時の熱応力を低減し、実装後の反りが小さく接続信頼性の高い実装品を得ることができるからである。具体的には、半導体素子１を基板２上に搭載する際に半導体素子実装用マウンタに備え付けられているパルスヒータを利用することで半導体素子１を加熱し、基板２を設置するマウンタステージは少なくとも半導体素子１側より低い温度設定にしておく方法が一例として挙げられる。なお、全体加熱、部分加熱にかかわらず、リフローは窒素のような不活性雰囲気で実施する方がはんだバンプの濡れ性がよい。   Next, after aligning the semiconductor element 1 with the substrate 2 (manufactured in steps A1 to A8), the semiconductor element 1 is mounted on the substrate 2, and the solder bump 5b on the semiconductor element 1 side or the solder on the substrate 2 side is mounted. At least one of the bumps 5a is melted to electrically connect the electrode pad 3 of the semiconductor element 1 and the electrode pad 4 of the substrate 2 (step A10; see FIG. 7B). Here, as a method of reflowing the solder bumps 5, it is possible to perform overall heating using a reflow furnace or the like, but a method of preventing the temperature of the substrate 2 from rising as much as possible by partial heating only from the semiconductor element 1 side. Is desirable. The reason is that by suppressing the temperature rise on the side of the substrate 2 having a large thermal expansion coefficient, the thermal stress at the time of mounting can be reduced, and a mounted product with low warpage after mounting and high connection reliability can be obtained. . Specifically, when the semiconductor element 1 is mounted on the substrate 2, the mounter stage that heats the semiconductor element 1 by using a pulse heater provided in the mounter for mounting the semiconductor element and installs the substrate 2 is at least An example is a method of setting a temperature lower than that of the semiconductor element 1 side. Regardless of the overall heating or partial heating, the reflow is better performed in an inert atmosphere such as nitrogen so that the wettability of the solder bumps is better.

次に、半導体素子１と基板２の隙間に残ったフラックスを洗浄する（ステップＡ１１；図７（Ｃ）参照）。フラックスの洗浄に関しては、一般的なはんだ接続後の洗浄に用いるフラックス洗浄液（例えば、パインアルファ 荒川化学工業株式会社製 など）を用いることができる。これにより、図１と同様な実装基板ができる。   Next, the flux remaining in the gap between the semiconductor element 1 and the substrate 2 is cleaned (step A11; see FIG. 7C). As for flux cleaning, a flux cleaning liquid (for example, Pine Alpha manufactured by Arakawa Chemical Industries, Ltd.) used for cleaning after soldering can be used. As a result, a mounting board similar to that shown in FIG. 1 can be obtained.

最後に、基板２をベーク等により、十分に乾燥させた後、毛細管現象を利用し第２絶縁層１０を半導体素子１と基板２の隙間に充填し、その後、第２絶縁層１０を硬化させる（ステップＡ１２；図７（Ｄ）参照）。このとき、使用する第２絶縁層１０の粘度特性や硬化特性に合わせて６０〜１００℃程度に加熱することで、ボイドの無いスムーズな充填を行うことができる。第２絶縁層１０を充填後、オーブン等を用いて第２絶縁層１０を硬化させることで、図３と同様な実装基板が完成する。   Finally, after the substrate 2 is sufficiently dried by baking or the like, the second insulating layer 10 is filled in the gap between the semiconductor element 1 and the substrate 2 by utilizing a capillary phenomenon, and then the second insulating layer 10 is cured. (Step A12; see FIG. 7D). At this time, smooth filling without voids can be performed by heating to about 60 to 100 ° C. in accordance with the viscosity characteristics and curing characteristics of the second insulating layer 10 to be used. After filling the second insulating layer 10, the second insulating layer 10 is cured using an oven or the like, thereby completing a mounting substrate similar to that shown in FIG.

実施例１によれば、電極の一部に低弾性な導電性接着剤６を使用しているため、はんだバンプ接合部の応力を緩和した信頼性の高い接続構造を実現できる。   According to the first embodiment, since the low-elastic conductive adhesive 6 is used for a part of the electrode, a highly reliable connection structure in which the stress of the solder bump joint is relaxed can be realized.

また、基板２の表層の構造として、第１絶縁層８と応力緩和層９の２層構造にするとともに第１絶縁層８よりも応力緩和層９の弾性率を低くしておくことで、導電性接着剤６に対しては第１絶縁層８と応力緩和層９の界面近傍付近に意図的に応力を発生させている。この効果により、基板２側の電極パッド４と導電性接着剤６の接着界面にかかる応力は小さくなるため、実装後の応力による導電性接着剤６と電極パッド４の界面における剥離を抑制し、高い接続信頼性を確保することが可能となる。   Further, the structure of the surface layer of the substrate 2 is a two-layer structure of the first insulating layer 8 and the stress relaxation layer 9 and the elastic modulus of the stress relaxation layer 9 is lower than that of the first insulating layer 8, so that For the adhesive 6, stress is intentionally generated near the interface between the first insulating layer 8 and the stress relaxation layer 9. Due to this effect, since the stress applied to the bonding interface between the electrode pad 4 and the conductive adhesive 6 on the substrate 2 side is reduced, the peeling at the interface between the conductive adhesive 6 and the electrode pad 4 due to the stress after mounting is suppressed, It becomes possible to ensure high connection reliability.

また、応力緩和層９と導電性接着剤６の弾性率、伸びといった機械的特性を近い値に設定することで、導電性接着剤６を含めた応力緩和層９は、導電層、絶縁層を問わず一様で、局部的な応力集中が発生しないため、半導体素子１や基板２の寿命が延び、高信頼な接続を実現できる。   In addition, by setting the mechanical properties such as the elastic modulus and elongation of the stress relaxation layer 9 and the conductive adhesive 6 to values close to each other, the stress relaxation layer 9 including the conductive adhesive 6 has a conductive layer and an insulating layer. Regardless, since it is uniform and local stress concentration does not occur, the life of the semiconductor element 1 and the substrate 2 is extended, and a highly reliable connection can be realized.

また、はんだバンプ５を保護する目的で、半導体素子１と基板２の隙間に第２絶縁層１０を形成した場合において、はんだバンプ５の保護に効果的な高弾性な樹脂にて第２絶縁層１０を形成した場合でも、応力緩和層９の効果により実装後の反りを低減することができ、高信頼性で、かつ低応力な実装構造を実現できる。   Further, when the second insulating layer 10 is formed in the gap between the semiconductor element 1 and the substrate 2 for the purpose of protecting the solder bump 5, the second insulating layer is made of a highly elastic resin effective for protecting the solder bump 5. Even when 10 is formed, warping after mounting can be reduced by the effect of the stress relaxation layer 9, and a highly reliable and low stress mounting structure can be realized.

本発明の実施例２に係る実装基板の製造方法について図面を用いて説明する。図８は、本発明の実施例２に係る実装基板の製造方法を模式的に示した工程断面図である。   A mounting substrate manufacturing method according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 8 is a process cross-sectional view schematically showing a method for manufacturing a mounting board according to the second embodiment of the present invention.

実施例２に係る実装基板の製造方法は、実施例１に係る実装基板の製造方法と大きく異なるところは、半導体素子１と基板２を準備した後、基板２側に第２絶縁層１０となる絶縁樹脂１０ａを供給するようにした点である。   The mounting substrate manufacturing method according to the second embodiment is greatly different from the mounting substrate manufacturing method according to the first embodiment. After the semiconductor element 1 and the substrate 2 are prepared, the second insulating layer 10 is formed on the substrate 2 side. This is the point that the insulating resin 10a is supplied.

まず、実施例１のステップＡ１〜Ａ８と同様にして、電極パッド４、第１絶縁層８、応力緩和層９、導電性接着剤６、金属層７、及びはんだバンプ５ａが形成されている基板２と、電極パッド３上にはんだバンプ５ｂを形成した半導体素子１とを準備し、続いて基板２側に絶縁樹脂１０ａを供給する（ステップＢ１；図８（Ａ）参照）。   First, the substrate on which the electrode pad 4, the first insulating layer 8, the stress relaxation layer 9, the conductive adhesive 6, the metal layer 7, and the solder bump 5a are formed in the same manner as in Steps A1 to A8 of Example 1. 2 and the semiconductor element 1 in which the solder bumps 5b are formed on the electrode pads 3, and then the insulating resin 10a is supplied to the substrate 2 side (step B1; see FIG. 8A).

ここで、絶縁樹脂１０ａは、酸化膜除去作用を有することが望ましい。その理由は、半導体素子１側のはんだバンプ５ｂと基板２側のはんだバンプ５ａの接合時において、それぞれのはんだバンプ５ａ、５ｂの表面の酸化膜を除去し、接合性を向上させることができるからである。絶縁樹脂１０ａに酸化膜除去作用を与えるには、（メタ）アクリル酸、マレイン酸などの不飽和酸、蓚酸、マロン酸などの有機二酸、クエン酸などの有機酸をはじめ、炭化水素の側鎖に、ハロゲン基、水酸基、ニトリル基、ベンジル基、カルボキシル基等を少なくとも１つ以上を添加することにより可能である。これらの添加剤を３〜１０ｗｔ％（重量％）加えてもよいし、他の方法としては、エポキシ樹脂の硬化剤と主剤の反応時に生成される前記物質を利用して、酸化膜除去を行なうことも可能である。エポキシ樹脂の主剤と硬化剤の混合比は、主剤６０〜９０ｗｔ％（重量％）に対して、硬化剤１０〜４０ｗｔ％（重量％）が望ましい。   Here, the insulating resin 10a desirably has an oxide film removing action. The reason is that when the solder bumps 5b on the semiconductor element 1 side and the solder bumps 5a on the substrate 2 side are joined, the oxide films on the surfaces of the respective solder bumps 5a and 5b can be removed to improve the bondability. It is. In order to give the insulating resin 10a an action of removing an oxide film, unsaturated acids such as (meth) acrylic acid and maleic acid, organic diacids such as oxalic acid and malonic acid, organic acids such as citric acid, and the hydrocarbon side It is possible by adding at least one halogen group, hydroxyl group, nitrile group, benzyl group, carboxyl group or the like to the chain. These additives may be added in an amount of 3 to 10 wt% (weight%). As another method, the oxide film is removed by using the substance generated during the reaction between the curing agent of the epoxy resin and the main agent. It is also possible. The mixing ratio of the epoxy resin main agent and the curing agent is preferably 10 to 40 wt% (wt%) with respect to 60 to 90 wt% (wt%) of the main agent.

次に、半導体素子１と基板２を位置合わせした後、半導体素子１を基板２上に搭載し、その後、加熱を行ない、はんだバンプ５ａ、はんだバンプ５ｂのうち、少なくとも一方を溶融させ、半導体素子１の電極パッド３と基板２の電極パッド４とを電気的に接続する（ステップＢ２；図８（Ｂ）参照）。この時、ステップＡ１２（図７（Ｄ）参照）にて説明したプロセスと同様に、半導体素子１側のみからの部分加熱により、基板２の温度がなるべく上がらないようにする方法が望ましい。その理由は、前記した理由と同様である。   Next, after aligning the semiconductor element 1 and the substrate 2, the semiconductor element 1 is mounted on the substrate 2, and then heating is performed to melt at least one of the solder bump 5a and the solder bump 5b. 1 electrode pad 3 and electrode pad 4 of substrate 2 are electrically connected (step B2; see FIG. 8B). At this time, similarly to the process described in step A12 (see FIG. 7D), a method of preventing the temperature of the substrate 2 from rising as much as possible by partial heating only from the semiconductor element 1 side is desirable. The reason is the same as described above.

最後に、絶縁樹脂１０ａを硬化して、第２絶縁層１０を形成する（ステップＢ３；図８（Ｂ）参照）。絶縁樹脂１０ａの硬化は、半導体素子１を搭載した際の加熱をはんだバンプ接合後も継続して実施し、絶縁樹脂１０ａの硬化を進めてもよいし、はんだバンプ接合後は、所定の温度に管理されたオーブン等に投入して、絶縁樹脂１０ａを硬化してもよい。以上により、図３と同様な実装基板が完成する。   Finally, the insulating resin 10a is cured to form the second insulating layer 10 (step B3; see FIG. 8B). The insulating resin 10a may be cured by continuously heating the semiconductor element 1 after the solder bump bonding, and may proceed with the curing of the insulating resin 10a. The insulating resin 10a may be cured by putting it in a controlled oven or the like. As described above, a mounting board similar to that shown in FIG. 3 is completed.

実施例２によれば、実施例１と同様な効果を奏する。   According to the second embodiment, the same effect as the first embodiment is obtained.

以上、本発明の実施例を図面を用いて詳述してきたが、具体的な構成はこの実施例に限られるものではなく、本発明の要旨を逸脱しない範囲の設計の変更などがあってもこの発明に含まれる。例えば、実施例では電子部品として半導体素子を用いた例で説明したが、電子部品としてはこれに限らずキャパシタ、インダクタなどの受動素子も含めた他の素子に対しても同様に適用することができる。また、電子部品側の電極パッド、及び基板側の電極パッドの形状は、ともに平面形状が略円形状に形成された例で説明したが、これらの例に限らずに楕円形状などの他の任意の形状を選ぶこともできる。
本発明の全開示（請求の範囲を含む）の枠内において、さらにその基本的技術思想に基づいて、実施例ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and even if there is a design change or the like without departing from the gist of the present invention. It is included in this invention. For example, in the embodiment, the example in which the semiconductor element is used as the electronic component has been described. However, the electronic component is not limited to this, and can be similarly applied to other elements including a passive element such as a capacitor and an inductor. it can. In addition, the shape of the electrode pad on the electronic component side and the electrode pad on the substrate side has been described as an example in which the planar shape is formed in a substantially circular shape. You can also choose the shape.
Within the scope of the entire disclosure (including claims) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (17)

電極パッドが形成された基板と、
前記電極パッドを含む前記基板上に形成された第１絶縁層と、
前記第１絶縁層上に形成されるとともに、前記第１絶縁層よりも弾性率が低い応力緩和層と、
前記第１絶縁層及び前記応力緩和層に形成されるとともに前記電極パッドに通ずる開口部と、
前記開口部に充填されるとともに導電粒子及び樹脂を含んだ導電性接着剤と、
前記導電性接着剤の表面に形成された金属層と、
を備え、
前記第１絶縁層と前記応力緩和層の界面は、前記開口部において前記導電性接着剤と接することを特徴とする基板。A substrate on which electrode pads are formed;
A first insulating layer formed on the substrate including the electrode pad;
A stress relaxation layer formed on the first insulating layer and having a lower elastic modulus than the first insulating layer;
An opening formed in the first insulating layer and the stress relaxation layer and communicating with the electrode pad;
A conductive adhesive filled with the opening and containing conductive particles and resin;
A metal layer formed on the surface of the conductive adhesive;
With
The board | substrate characterized by the interface of a said 1st insulating layer and the said stress relaxation layer being in contact with the said conductive adhesive in the said opening part. 前記導電性接着剤は、前記金属層と接している前記導電性接着剤の表層部において、少なくとも前記導電粒子が前記樹脂の最外層よりも突出しており、
前記金属層は、前記樹脂を介することなく前記導電粒子と直接密着していることを特徴とする請求項１記載の基板。In the surface layer portion of the conductive adhesive that is in contact with the metal layer, the conductive adhesive protrudes at least from the outermost layer of the resin,
The substrate according to claim 1, wherein the metal layer is in direct contact with the conductive particles without using the resin. 前記金属層は、少なくともＮｉ層を含んでいることを特徴とする請求項１又は２記載の基板。  The substrate according to claim 1, wherein the metal layer includes at least a Ni layer. 前記金属層は、前記Ｎｉ層の表面にＡｕ層が形成されていることを特徴とする請求項３記載の基板。  The substrate according to claim 3, wherein the metal layer has an Au layer formed on a surface of the Ni layer. 前記応力緩和層上に形成されるとともに、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を備え、
前記金属層の表面は、前記第３絶縁層の表面よりも低いことを特徴とする請求項１乃至４のいずれか一に記載の基板。A third insulating layer formed on the stress relaxation layer and opened so that the metal layer is exposed at a position corresponding to the opening;
The substrate according to claim 1, wherein a surface of the metal layer is lower than a surface of the third insulating layer. 前記金属層の表面を覆うように形成されたはんだバンプを備えることを特徴とする請求項１乃至５のいずれか一に記載の基板。  6. The substrate according to claim 1, further comprising solder bumps formed so as to cover a surface of the metal layer. 基板上に電子部品が実装された実装基板であって、
請求項１乃至５のいずれか一に記載の基板と、
電極パッドが形成された電子部品と、
前記金属層と、前記電子部品の前記電極パッドとを接合するはんだバンプと、
を備えることを特徴とする実装基板。A mounting board in which electronic components are mounted on a board,
A substrate according to any one of claims 1 to 5;
An electronic component having electrode pads formed thereon;
A solder bump that joins the metal layer and the electrode pad of the electronic component;
A mounting board comprising: 前記電子部品と前記基板の隙間を封止するとともに、前記応力緩和層よりも弾性率が高い第２絶縁層を備えることを特徴とする請求項７記載の実装基板。  The mounting substrate according to claim 7, further comprising a second insulating layer that seals a gap between the electronic component and the substrate and has a higher elastic modulus than the stress relaxation layer. 電極パッドが形成された基板上に第１絶縁層を形成する工程と、
前記第１絶縁層上に前記第１絶縁層よりも弾性率の低い応力緩和層を形成する工程と、
前記第１絶縁層及び応力緩和層に、前記電極パッドに通ずる開口部を形成する工程と、
前記開口部に樹脂及び導電粒子を含む導電性接着剤を充填する工程と、
前記導電性接着剤の表面に前記導電粒子を露出させる工程と、
前記導電性接着剤の表面に金属層を形成する工程と、
を含むことを特徴とする基板の製造方法。Forming a first insulating layer on the substrate on which the electrode pads are formed;
Forming a stress relaxation layer having a lower elastic modulus than the first insulating layer on the first insulating layer;
Forming an opening communicating with the electrode pad in the first insulating layer and the stress relaxation layer;
Filling the opening with a conductive adhesive containing resin and conductive particles;
Exposing the conductive particles on the surface of the conductive adhesive;
Forming a metal layer on the surface of the conductive adhesive;
A method for manufacturing a substrate, comprising: 前記導電粒子を露出させる工程の後であって前記金属層を形成する工程の前に、前記応力緩和層上に、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を形成する工程を含むことを特徴とする請求項９記載の基板の製造方法。  After the step of exposing the conductive particles and before the step of forming the metal layer, the metal layer was opened on the stress relaxation layer so as to be exposed at a position corresponding to the opening. The method for manufacturing a substrate according to claim 9, comprising a step of forming a third insulating layer. 前記金属層を形成する工程の後に、前記応力緩和層上に、前記開口部と対応する位置にて前記金属層が露出するように開口された第３絶縁層を形成する工程を含むことを特徴とする請求項９記載の基板の製造方法。  After the step of forming the metal layer, the method includes a step of forming a third insulating layer opened on the stress relaxation layer so as to expose the metal layer at a position corresponding to the opening. A method for manufacturing a substrate according to claim 9. 前記金属層上にはんだバンプを形成する工程を含むことを特徴とする請求項９乃至１１のいずれか一に記載の基板の製造方法。  The method for manufacturing a substrate according to claim 9, further comprising forming a solder bump on the metal layer. 電子部品の電極パッド上にはんだバンプを形成する工程と、
前記電子部品と、請求項１２記載の基板の製造方法によって製造された基板とを位置合わせして、前記基板上に前記電子部品を搭載する工程と、
前記はんだバンプを溶融させて、前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程と、
を含むことを特徴とする実装基板の製造方法。Forming solder bumps on electrode pads of electronic components;
Aligning the electronic component and the substrate manufactured by the substrate manufacturing method according to claim 12, and mounting the electronic component on the substrate;
Melting the solder bump and joining the metal layer of the substrate and the electrode pad of the electronic component;
The manufacturing method of the mounting board | substrate characterized by the above-mentioned. 前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程では、前記電子部品側の温度よりも前記基板側の温度を低く保ちながら接合することを特徴とする請求項１３記載の実装基板の製造方法。  14. The step of bonding the metal layer of the substrate and the electrode pad of the electronic component is performed while maintaining the temperature on the substrate side lower than the temperature on the electronic component side. Manufacturing method of the mounting board. 前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程の後に、前記電子部品と前記基板の隙間に第２絶縁層を封入する工程を含むことを特徴とする請求項１３又は１４記載の実装基板の製造方法。  14. A step of encapsulating a second insulating layer in a gap between the electronic component and the substrate after the step of bonding the metal layer of the substrate and the electrode pad of the electronic component is included. Or the manufacturing method of the mounting substrate of 14. 請求項１２記載の基板の製造方法によって製造された基板上に絶縁樹脂を供給する工程と、
電子部品の電極パッド上にはんだバンプを形成する工程と、
前記電子部品と前記基板を位置合わせして、前記基板上に前記電子部品を搭載する工程と、
前記はんだバンプを溶融させて、前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程と、
を含むことを特徴とする実装基板の製造方法。Supplying an insulating resin on the substrate manufactured by the substrate manufacturing method according to claim 12;
Forming solder bumps on electrode pads of electronic components;
Aligning the electronic component and the substrate and mounting the electronic component on the substrate;
Melting the solder bump and joining the metal layer of the substrate and the electrode pad of the electronic component;
The manufacturing method of the mounting board | substrate characterized by the above-mentioned. 前記基板の前記金属層と、前記電子部品の前記電極パッドとを接合する工程では、前記電子部品側の温度よりも前記基板側の温度を低く保ちながら接合し、その際、前記絶縁樹脂を硬化することを特徴とする請求項１６記載の実装基板の製造方法。  In the step of bonding the metal layer of the substrate and the electrode pad of the electronic component, bonding is performed while keeping the temperature on the substrate side lower than the temperature on the electronic component side, and at that time, the insulating resin is cured The method of manufacturing a mounting board according to claim 16, wherein:
JP2010516888A 2008-06-12 2009-06-12 Mounting substrate, substrate, and manufacturing method thereof Expired - Fee Related JP5541157B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010516888A JP5541157B2 (en) 2008-06-12 2009-06-12 Mounting substrate, substrate, and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008154175 2008-06-12
JP2008154175 2008-06-12
PCT/JP2009/060729 WO2009151108A1 (en) 2008-06-12 2009-06-12 Mounting substrate, substrate and methods for manufacturing mounting substrate and substrate
JP2010516888A JP5541157B2 (en) 2008-06-12 2009-06-12 Mounting substrate, substrate, and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPWO2009151108A1 JPWO2009151108A1 (en) 2011-11-17
JP5541157B2 true JP5541157B2 (en) 2014-07-09

Family

ID=41416811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010516888A Expired - Fee Related JP5541157B2 (en) 2008-06-12 2009-06-12 Mounting substrate, substrate, and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP5541157B2 (en)
WO (1) WO2009151108A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175492A (en) * 2010-06-14 2013-09-05 Panasonic Corp Semiconductor device and method of manufacturing the same
JP6024078B2 (en) * 2011-08-17 2016-11-09 大日本印刷株式会社 Suspension board
DE112012006875T5 (en) 2012-09-04 2015-06-03 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing a semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228423A (en) * 1999-02-05 2000-08-15 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JP2006066597A (en) * 2004-08-26 2006-03-09 Ibiden Co Ltd Printed wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228423A (en) * 1999-02-05 2000-08-15 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JP2006066597A (en) * 2004-08-26 2006-03-09 Ibiden Co Ltd Printed wiring board

Also Published As

Publication number Publication date
WO2009151108A1 (en) 2009-12-17
JPWO2009151108A1 (en) 2011-11-17

Similar Documents

Publication Publication Date Title
JP5510795B2 (en) Electronic component mounting structure, electronic component mounting method, and electronic component mounting substrate
KR100545008B1 (en) Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same
JP4605155B2 (en) Semiconductor device and manufacturing method thereof
US7202569B2 (en) Semiconductor device and manufacturing method of the same
US6774497B1 (en) Flip-chip assembly with thin underfill and thick solder mask
JP5649805B2 (en) Manufacturing method of semiconductor device
JP2006279062A (en) Semiconductor element and semiconductor device
KR101521485B1 (en) Pga type wiring board and mehtod of manufacturing the same
TW201030869A (en) Electronic device and manufacturing method for electronic device
JP2009099669A (en) Mounting structure of electronic component, and mounting method thereof
JP2009200067A (en) Semiconductor chip and semiconductor device
JP5541157B2 (en) Mounting substrate, substrate, and manufacturing method thereof
JP2012182350A (en) Module component and manufacturing method of the same
JP5245270B2 (en) Semiconductor device and manufacturing method thereof
JP4065264B2 (en) Substrate with relay substrate and method for manufacturing the same
JP5311656B2 (en) Wiring board
JP2000151086A (en) Printed circuit unit and its manufacture
JP2004207534A (en) Wiring board and electronic device using it
JP2005244163A (en) Substrate with extension board and its manufacturing method
JPWO2009028239A1 (en) Semiconductor device mounting structure and semiconductor device mounting method
JP3204142B2 (en) Semiconductor device manufacturing method and lead frame
JP2024061960A (en) Wiring board and manufacturing method thereof, and semiconductor device
TWI473181B (en) Package substrate having electrical connecting structure and method of forming the same
JP2007027337A (en) Substrate with extension board and its manufacturing method
JP2008034775A (en) Circuit device with mounted semiconductor device, and packaging method of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120511

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140408

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140421

R150 Certificate of patent or registration of utility model

Ref document number: 5541157

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees