JP2006066597A - Printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board capable of preventing a connection with an electronic component from being broken owing to heat expansion or heat shrinkage and stably supplying electric power to the electronic component. <P>SOLUTION: On the printed wiring board 10, a conductor post 34 has a solder core body 37 differently from a conventional conductor post made of copper nearly entirely. In general, solder is lower in coefficient of elasticity (e.g. Young's modulus) than copper, so the conductor post 34 never greatly hinders elastic deformation of a stress relaxation layer 30. Further, a barrier layer 36 brings the solder core body 37 and stress relaxing layer 30 into contact with each other, so when the stress relaxation layer 30 elastically deforms, the solder core body 37 and stress relaxation layer 30 never peels off each other. Therefore, even if stress is generated due to a difference in thermal expansion between a core substrate 12 and an IC chip 50, the stress is securely relaxed by the stress relaxation layer 30, and peeling from which cracking easily originates is not caused. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a printed wiring board, and more specifically, via a through-hole conductor or via hole in which a conductor circuit layer and an insulating layer are alternately formed on at least one surface of a core substrate, and each conductor circuit layer passes through the insulating layer. The present invention relates to a printed wiring board which is electrically connected and electronic components mounted on a mounting surface are electrically connected to the conductor circuit layer.

  In recent years, electronic devices typified by portable information terminals and communication terminals have been remarkably improved in function and size. As a form in which a semiconductor chip used in these electronic devices is mounted on a multilayer printed wiring board at a high density, a flip chip system in which the semiconductor chip is directly mounted on the multilayer printed wiring board is employed. As such a multilayer printed wiring board, a core substrate, a buildup layer formed on the core substrate, and a mounting electrode on which a semiconductor chip is mounted on the upper surface of the buildup layer via a solder bump are provided. What you have is known. Here, as the core substrate, epoxy resin, BT (bismaleimide / triazine) resin, polyimide resin, polybutadiene resin, phenol resin or the like molded with a reinforcing material such as glass fiber is used. The thermal expansion coefficient is about 12 to 20 ppm / ° C. (30 to 200 ° C.), which is about 4 times or more larger than the thermal expansion coefficient of silicon of the semiconductor chip (about 3.5 ppm / ° C.). Therefore, in the above-described flip chip method, when the temperature change accompanying the heat generation of the semiconductor chip repeatedly occurs, the solder bump may be destroyed due to the difference in thermal expansion amount and thermal contraction amount between the semiconductor chip and the core substrate. It was.

In order to solve this problem, a stress relaxation layer having a low elastic modulus is provided on the buildup layer, a mounting electrode is provided on the upper surface of the stress relaxation layer, and the conductor circuit layer and the mounting electrode on the buildup layer are provided. Multilayer printed wiring boards connected by conductor posts have been proposed (see Patent Documents 1 and 2). For example, in Patent Document 2, as shown in FIG. 11, a low elastic modulus layer 140 is laminated on the upper surface of the buildup layer 130, and the conductive circuit layer 132 on the upper surface of the buildup layer 130 and the upper surface of the low elastic modulus layer 140. A multilayer printed wiring board 100 in which formed mounting electrodes 152 are connected by via holes 150 is disclosed.
JP 58-28848 A JP 2001-36253 A

  However, in this multilayer printed wiring board 100, since the material forming the via hole 150 is mainly copper, the electrical resistance may change greatly when repeated heating and cooling. There was a risk of insufficient supply.

  The present invention has been made in order to solve the above-described problems, and prevents the breakage of connection with an electronic component due to thermal expansion and contraction, and can provide a stable power supply to the electronic component. The purpose is to provide a board.

  The present invention employs the following means in order to achieve at least a part of the above-described object.

In the printed wiring board of the present invention, conductor circuit layers and insulating layers are alternately formed on at least one surface of the core substrate, and each conductor circuit layer is electrically connected through a through-hole conductor or via hole penetrating the insulating layer. And a printed wiring board in which an electronic component mounted on the mounting surface is electrically connected to the conductor circuit layer,
A stress relaxation layer made of a material having a lower elastic modulus than the insulating resin, which is formed so as to cover the outer layer conductor circuit layer closest to the outer layer among the plurality of conductor circuit layers;
A through hole penetrating the stress relaxation layer;
A conductor post comprising a barrier layer formed on the inner wall of the through-hole and a solder core formed inside the barrier layer, and electrically connecting the outer conductor circuit layer and the electronic component;
It is equipped with.

  In this printed wiring board, the conductor post has a core made of solder, unlike the conventional one that is mostly made of copper. Here, since the solder generally has a lower elastic modulus (for example, Young's modulus) than copper, this conductor post does not greatly hinder the elastic deformation of the stress relaxation layer. In addition, since the barrier layer causes the core made of solder and the stress relaxation layer to adhere to each other, peeling does not occur between the core and the stress relaxation layer when the stress relaxation layer is elastically deformed. Therefore, even if a stress due to a difference in thermal expansion between the core substrate and the electronic component occurs, the stress is surely relieved by the stress relaxation layer, and peeling that tends to become a starting point of a crack does not occur. As a result, it is possible to prevent breakage of the connection between the outer layer wiring pattern and the electronic component, and it is possible to stably supply power to the electronic component while suppressing the rate of change in electrical resistance when heating and cooling are repeated. .

  In the printed wiring board of the present invention, the conductor post preferably has an aspect ratio (height / diameter) of 1.5 or more. By doing so, the flexibility of the conductor post is increased and the conductor post is easily deformed, so that the conductor post does not hinder the elastic deformation of the stress relaxation layer.

  In the printed wiring board of the present invention, it is preferable that the core body is made of solder having a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method. When the Young's modulus of the core is less than 40 GPa, the conductor post cannot regulate the deformation of the stress relaxation layer, and the amount of deformation becomes too large, which may cause a problem. When the Young's modulus of the core is 70 GPa or more, the conductor This is because the post may prevent deformation of the stress relaxation layer and may cause a problem.

Here, the Young's modulus E by the ultrasonic flaw detection method is determined by measuring the propagation time of the longitudinal wave and the propagation time of the transverse wave at room temperature, and obtaining the longitudinal wave velocity (V _L ) and the transverse wave velocity (V _S ) based on them. For example, it can be calculated by the following formula. Here, σ is a density. In addition, as an ultrasonic flaw detector, for example, the SONIC series of Eisin Chemical Co., Ltd. can be used.
E = {σV _S ² (3V _L ² −4V _S ² )} / (V _L ² −V _S ² )

  In the printed wiring board of the present invention, the core is preferably made of lead-free solder made of at least two metals selected from the group consisting of Sn, Ag, Cu, In, Bi, and Zn. This is because such lead-free solder often has a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method.

  In the printed wiring board of the present invention, the barrier layer preferably has a thickness of 0.03 to 5 μm. If the thickness of the barrier layer is less than 0.03 μm, solder wettability may be deteriorated, and voids may be generated between the barrier layer and the core when the core is provided. The thickness of the barrier layer exceeds 5 μm. This is because the conductor post becomes hard, so that deformation of the stress relaxation layer is prevented so that a problem may occur.

  In the printed wiring board of the present invention, it is preferable that the barrier layer is made of a metal selected from the group consisting of Cu, Au, Pd, Ni—Au, Ni—Pd—Au, and Ni—Pd. This is because these metals have good solder wettability, so that voids are not easily generated between the barrier layer and the core when the core is provided.

  In the printed wiring board of the present invention, the stress relaxation layer preferably has a Young's modulus in accordance with JIS K7113 of 10 MPa to 1 GPa. This Young's modulus is a value at room temperature. If it carries out like this, the stress relaxation layer can relieve | moderate the stress resulting from a thermal expansion difference reliably. The stress relaxation layer has a Young's modulus of more preferably 10 MPa to 500 MPa, and most preferably 10 MPa to 100 MPa. Examples thereof include polyolefin resins and polyimide resins that are thermoplastic resins, silicone resins that are thermosetting resins, and modified epoxy resins containing NBR and the like.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a use state of a printed wiring board according to an embodiment of the present invention. In this specification, it may be expressed as “upper” or “lower”, but this is merely a representation of the relative positional relationship for convenience. Or you may.

  In the printed wiring board 10 of the present embodiment, an IC chip 50 that is a semiconductor element is mounted on a mounting surface 40. In the present embodiment, the IC chip 50 operates at a clock frequency of 3 GHz or more, and a large number of pads 52 are arranged on the lower surface in a grid pattern or a staggered pattern. The IC chip 50 has a thermal expansion coefficient of about 3.5 ppm / ° C.

  The printed wiring board 10 includes a core substrate 12 serving as a base for forming each layer, a buildup layer 20 laminated on both upper and lower surfaces of the core substrate 12, and a low elastic modulus material laminated on the buildup layer 20. And a mounting surface 40 formed on the upper surface of the stress relaxation layer 30.

  The core substrate 12 includes wiring patterns 16 and 16 made of copper on the upper and lower surfaces of the core substrate body 14 made of BT (bismaleimide-triazine) resin, glass epoxy resin, and the like, and an inner periphery of a through hole that penetrates the core substrate body 14 A through-hole conductor 18 made of copper is formed on the surface, and both wiring patterns 16 and 16 are electrically connected via the through-hole conductor 18.

  The buildup layer 20 is formed by alternately laminating insulating layers 22 and conductor circuit layers 24 on both upper and lower surfaces of the core substrate 12, and the wiring pattern 16 of the core substrate 12 and the conductor circuit layers 24 of the buildup layer 20 are formed. Electrical connection and electrical connection between the conductor circuit layers 24 and 24 in the build-up layer 20 are ensured by a filled via 26 penetrating the insulating layer 22. Here, the insulating layer 22 is made of an insulating resin having a Young's modulus of 3 to 7 GPa at room temperature in accordance with JIS K7113. The buildup layer 20 is formed by using a well-known subtractive method or additive method (including a semi-additive method or a full additive method). Specifically, for example, it is formed as follows. That is, first, resin sheets to be the insulating layers 22 are attached to the upper and lower surfaces of the core substrate 12. This resin sheet is formed of a modified epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide resin sheet, a cyanoester resin sheet, or the like, and has a thickness of approximately 20 to 80 μm. Next, the bonded resin sheet is punched with a carbon dioxide laser, UV laser, YAG laser, excimer laser, or the like. Subsequently, electroless copper plating is applied to the surface (including the inner wall and bottom surface of the hole) of the resin sheet, a photoresist is formed on the electroless copper plating layer, and patterning is performed by exposure and development through a pattern mask. Next, after electrolytic copper plating is performed on a portion where the photoresist is not formed, the photoresist is peeled off, and the portion of the electroless copper plating where the photoresist was present is removed by etching. Thereby, the conductor circuit layer 24 is formed on the surface layer of the insulating layer 22, and the filled via 26 filled with copper plating is formed in the hole formed in the insulating layer 22. After that, the build-up layer 20 is formed by repeating this procedure. This method is called a build-up method, and is described in, for example, “Build-Up Multilayer Printed Wiring Board Technology” (Nikkan Kogyo Shimbun, issued June 20, 2000). A structure in which the build-up layers 20 are formed on the upper and lower surfaces of the core substrate 12 is referred to as a multilayer printed wiring board A.

  The stress relaxation layer 30 is an elastic material having an elastic modulus lower than that of the insulating layer 22 of the buildup layer 20, specifically, a Young's modulus at room temperature in accordance with JIS K7113 is preferably 10 to 1000 MPa (preferably 10 to 300 MPa, more preferably Is formed of an elastic material of 10 to 100 MPa). When the Young's modulus of the stress relaxation layer 30 is within this range, the stress caused by the difference in thermal expansion between the IC chip 50 mounted on the mounting surface 40 and the multilayer printed wiring board A (mainly the core substrate 12) is present. Even if it occurs, the stress relaxation layer 30 can be elastically deformed to relieve the stress. Examples of the elastic material used for the stress relaxation layer 30 include thermosetting resins such as epoxy resins, imide resins, phenol resins, and silicone resins, and thermoplastic resins such as polyolefin resins, vinyl resins, and imide resins. Examples of the resin include those that meet the above-mentioned Young's modulus among resins in which rubber components such as polybutadiene, silicone rubber, urethane, SBR, and NBR, and inorganic components such as silica, alumina, and zirconia are dispersed. The component dispersed in the resin may be one type or two or more types, and both the rubber component and the inorganic component may be dispersed.

  The stress relaxation layer 30 includes a plurality of through holes 32 and a conductor post 34 formed in each through hole 32. The plurality of through holes 32 are formed in a lattice shape or a zigzag shape so as to correspond to each pad 52 of the IC chip 50. The conductor post 34 includes a barrier layer 36 formed so as to cover the inner wall and the bottom surface of the through hole 32, and a solder core body 37 formed in a space surrounded by the barrier layer 36. . The conductor post 34 is formed so that the diameter D is 30 to 50 μm and the aspect ratio (height h / diameter D) is 1.5 or more. Among these, the barrier layer 36 is a metal selected from the group consisting of metals having good solder wettability such as Cu, Au, Pd, Ni—Au, Ni—Pd—Au, and Ni—Pd, and has a thickness of 0.03. It is formed to be ˜5 μm. Since the barrier layer 36 is formed in a state in which the inner wall surface of the through hole 32 of the stress relaxation layer 30 is roughened, the barrier layer 36 is excellent in adhesion to the through hole 32 or has good wettability, so that the solder core body. Excellent adhesion to 37. That is, the adhesion between the stress relaxation layer 30 and the solder core 37 is ensured by the barrier layer 36. The barrier layer 36 is also formed around the opening of the through hole 32, and a hook-shaped portion around the opening is a land portion 36a. On the other hand, the solder core 37 is made of lead-free solder having a Young's modulus measured by an ultrasonic flaw detection method of 40 GPa or more and less than 70 GPa, for example, at least two metals selected from the group consisting of Sn, Ag, Cu, In, Bi and Zn. It is made of lead-free solder. A solder bump portion 38 formed so as to protrude above the upper surface of the stress relaxation layer 30 is formed on the solder core 37. The solder bump portion 38 is electrically connected to the IC chip 50.

  Note that a large number of solder bumps 48 are formed on the lower surface of the printed wiring board 10 for electrical connection to a mother board (not shown).

  Next, a usage example of the printed wiring board 10 configured as described above will be described. First, the plurality of pads 52 disposed on the lower surface of the IC chip 50 are placed in contact with the solder bump portions 38 of the printed wiring board 10 and reflowed. Next, a plurality of solder bumps 48 formed on the lower surface of the printed wiring board 10 are placed on a motherboard pad (not shown) and reflowed. As a result, the IC chip 50 and the printed wiring board 10 are joined via the solder bump portions 38, and the printed wiring board 10 and the mother board are joined via the solder bumps 48. Thereby, since the IC chip 50 is electrically connected to the mother board via the printed wiring board 10, power is supplied, grounded, and signals are exchanged. In addition, the connection between the printed wiring board 10 and the mother board may be made via a pin erected on the printed wiring board 10 or a needle terminal provided on the mother board side. .

  Next, a method for manufacturing the printed wiring board 10 will be described with reference to FIGS. Here, it is assumed that the build-up layer 20 has been formed, and the manufacturing procedure of the stress relaxation layer 30 will be mainly described. First, the low elastic modulus material sheet 300 was affixed on the upper surface of the outer conductor circuit layer 24a (see FIG. 2) of the buildup layer 20 (see FIG. 3). Here, as a low elastic modulus material, naphthalene type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., trade name: NC-7000L), 100 parts by weight, phenol-xylylene glycol condensation resin (made by Mitsui Chemicals, trade name: XLC) -LL) 20 parts by weight, carboxylic acid-modified NBR having a Tg of -50 ° C. (trade name: XER-91) as crosslinked rubber particles, 90 parts by weight, 1-cyanoethyl-2-ethyl-4-methyl A material composed of a resin composition in which 4 parts by weight of imidazole was dissolved in 300 parts by weight of ethyl lactate was used. This low elastic modulus material has a Young's modulus at 30 ° C. in accordance with JIS K7113 of 500 MPa.

  Subsequently, through holes 32 were formed at positions corresponding to the pads 52 of the IC chip 50 in the low elastic modulus material sheet 300 by a carbon dioxide laser, UV laser, YAG laser, excimer laser, or the like (see FIG. 4). Then, while removing the smear of the copper surface in the through-hole 32 using a potassium permanganate solution, the exposed surface (including the inner wall of the through-hole 32) exposed to the outside of the low elastic modulus material sheet 300 is removed. After roughening, an electroless plating catalyst was applied to the exposed surface, and then immersed in an electroless copper plating aqueous solution to form an electroless copper plating film 360 having a thickness of 0.03 to 5.0 μm. (See FIG. 5). Here, since the exposed surface was roughened earlier, the electroless copper plating film 360 adhered well due to the so-called anchor effect. Note that physical vapor deposition such as sputtering may be employed instead of electroless copper plating.

  Next, a dry film as a photoresist was laminated so as to cover the entire surface of the substrate being fabricated, and then exposed and developed through a pattern mask to form a patterned resist 362 (see FIG. 6). The resist 362 was patterned so as to close the opening of the through hole 32. Then, after removing a portion not covered with the resist 362, that is, a portion exposed on the surface of the electroless copper plating film 360, by a chemical method such as etching or a physical method such as reverse sputtering or blasting, the resist 362 is removed. Was peeled off (see FIG. 7). Thereby, a barrier layer 36 was formed on the inner wall of the through hole 32. Here, the barrier layer 36 is formed so as to extend to the periphery of the opening of the through hole 32, and the land portion 36 a is formed in the shape of a flange around the opening. Further, the low elastic modulus material sheet 300 became the stress relaxation layer 30.

  Finally, the squeegee printing method using a mask is used to fill the inside of the through-hole 32 (that is, the region surrounded by the barrier layer 36) with solder and to stack the solder on the land 36a, and then reflow the solder. After being melted, it was cooled to form a solder core 37 in the through hole 32 (see FIG. 8). Here, Sn—Ag lead-free solder having a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method was used as the solder. Further, since the barrier layer 36 is made of copper having good solder wettability, the solder was filled in the through holes 32 without causing voids. In addition, the solder bump portion 38 is formed integrally with the solder core 37. The solder bump portion 38 is obtained by once the solder above the land portion 36a is melted and then cooled and solidified.

  In the printed wiring board 10 of the present embodiment described in detail above, the conductor post 34 has the solder core body 37 having a Young's modulus lower than that of conventionally used copper. It does not hinder elastic deformation. In addition, since the barrier layer 36 causes the solder core 37 and the stress relaxation layer 30 to adhere to each other, no peeling occurs between the conductor post 34 and the stress relaxation layer 30 when the stress relaxation layer 30 is elastically deformed. Therefore, even if a stress due to the difference in thermal expansion between the IC chip 50 and the core substrate 12 is generated, the stress is surely relieved by the stress relaxation layer 30, and peeling that tends to be a starting point of a crack does not occur. As a result, it is possible to prevent the connection breakage between the outer conductor circuit layer 24a and the IC chip 50, and the power supply can be stably supplied to the IC chip 50 while suppressing the rate of change in electrical resistance when heating and cooling are repeated. can do.

  Further, since the conductor post 34 has an aspect ratio (height / diameter) of 1.5 or more and becomes flexible and easily deforms, the conductor post 34 also prevents elastic deformation of the stress relaxation layer 30 in this respect. Absent.

  Furthermore, since the solder core 37 is made of a solder having a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method, the conductor post 34 can appropriately regulate the deformation of the stress relaxation layer 30. That is, the conductor post 34 cannot regulate the deformation of the stress relaxation layer 30 and the deformation amount is too large to cause a problem, and the conductor post 34 prevents the deformation of the stress relaxation layer 30 and causes a problem. Nor.

  Furthermore, since the barrier layer 36 has a thickness of 0.03 to 5 μm, the adhesion between the barrier layer 36 and the solder core 37 is good, and the conductor post 34 becomes too hard to prevent deformation of the stress relaxation layer 30. Never too much.

  Moreover, since the stress relaxation layer 30 is made of a low elastic modulus material having a Young's modulus of 10 to 1000 MPa, the stress due to the difference in thermal expansion can be reliably relaxed.

  It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the above-described embodiment, the land portion 36a is provided in the barrier layer 36 of the conductor post 34, but the land portion 36a may not be provided. Further, although the solder bump portion 38 is provided on the upper portion of the solder core body 37, the solder core body 37 may be limited only to the region surrounded by the barrier layer 36 without providing the solder bump portion 38. In this case, solder bumps may be formed later on the upper surface of the conductor post 34, or solder bumps may be formed on the pads 52 of the IC chip 50. Further, although the interlayer connection between the conductor circuit layers 24 and 24 of the buildup layer 20 is performed by the filled via 26, it may be performed by a via hole not filled with a conductor.

  Moreover, you may form the stress relaxation layer 30 in the procedure of FIG. 9 instead of the preparation procedure of embodiment mentioned above. First, as shown in FIG. 5, after the through holes 32 are opened in the low elastic modulus material sheet 300 and the electroless copper plating film 360 is formed on the entire surface, the same procedure as in the above-described embodiment is performed. After laminating a dry film as a photoresist, exposure and development were performed through a pattern mask to form a patterned resist 364 (see FIG. 9A). The resist 364 was patterned so as to cover the opening of the through hole 32 and the region excluding the periphery of the opening. Then, solder plating is performed on a portion that is not covered with the resist 364, that is, a portion exposed on the surface of the electroless copper plating film 360, and a region surrounded by the barrier layer 36 and a space above the region are exposed to the resist. The region surrounded by 364 was filled with solder 380 (see FIG. 9B). Subsequently, the resist 364 was peeled off, and the electroless copper plating film 360 exposed on the upper surface of the low elastic modulus material sheet 300 was removed by alkali etching (see FIG. 9C). Thereafter, the solder was melted by reflow and then cooled to form a conductor post 34 including a solder core 37 and a barrier layer 36 in the through hole 32 (see FIG. 9D). As a result, the low elastic modulus material sheet 300 became the stress relaxation layer 30. In this case as well, a Sn-Ag lead-free solder having a Young's modulus by an ultrasonic flaw detection method of 40 GPa or more and less than 70 GPa was used.

  Or you may form the stress relaxation layer 30 in the preparation procedure of FIG. First, as shown in FIG. 4, until the through-hole 32 is opened in the low elastic modulus material sheet 300, after performing the same as the manufacturing procedure of the above-described embodiment, the inside of the through-hole 32 using the potassium permanganate solution. After removing the smear on the copper surface and roughening the exposed surface (including the inner wall of the through hole 32) of the low elastic modulus material sheet 300, a dry film as a photoresist is laminated, and then exposed through a pattern mask. Then, a patterned resist 366 was formed by development (see FIG. 10A). The resist 366 was patterned so as to cover the opening of the through hole 32 and the region excluding the periphery of the opening. Subsequently, after a Ni / Au metal film 368 is formed by sputtering on the entire surface (including the resist 366) of the substrate being fabricated (see FIG. 10B), the resist 366 is removed to remove unnecessary portions. The metal film 368 was removed together with the resist 366 (see FIG. 10C). As a result, the remaining metal coating 368 became the barrier layer 36. This method is widely known as a lift-off method. Thereafter, as in the above-described embodiment, the inside of the through-hole 32 (that is, the region surrounded by the barrier layer 36) is filled with solder by a printing method, and the solder is laminated on the land portion 36a, and then soldered by reflow. After being melted, it was cooled to form a solder core 37 in the through hole 32 (see FIG. 10D). As a result, the low elastic modulus material sheet 300 became the stress relaxation layer 30. Also here, Sn-Ag lead-free solder having a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method was used. Further, since the barrier layer 36 is made of nickel-gold having good solder wettability, the inside of the through hole 32 was filled with solder without causing voids. In addition, the solder bump portion 38 is formed integrally with the solder core 37. The solder bump portion 38 is obtained by once the solder above the land portion 36a is melted and then cooled and solidified.

  Below, the experiment example for demonstrating the effect of the printed wiring board of this invention is demonstrated. First, for the printed wiring boards of Experimental Examples 1 to 15 manufactured according to the manufacturing procedure of the above-described embodiment, the barrier layer material, barrier layer thickness, solder composition (with flux), post diameter, and aspect ratio shown in Table 1 Was made. Subsequently, an IC chip was mounted on each printed wiring board, and then a sealing resin was filled between the IC chip and the printed wiring board. Then, the electrical resistance of the specific circuit (the electrical resistance between the pair of electrodes exposed to the surface opposite to the IC chip mounting surface of the printed wiring board and conducting to the IC chip) is measured via the IC chip, The value was taken as the initial value. Thereafter, a heat cycle test was performed on the printed wiring board on which the IC chip was mounted, with −55 ° C. × 30 minutes and 125 ° C. × 30 minutes as one cycle and repeating this 1000 cycles. When the 1000th cycle was completed, the electrical resistance was measured in the same manner as described above, and the rate of change from the initial value (100 × (measured value−initial value) / initial value (%)) was obtained. The change rate of electrical resistance was within ± 5%, “◯”, over ± 5 but within ± 10%, “Δ”, and over ± 10%, “×”. The results are shown in Table 1 as resistance change after 1000 cycles (hereinafter simply referred to as resistance change).

  As is clear from Table 1, the resistance change was remarkably large in the case of the conductor post formed only by solder without providing the barrier layer (Experimental Example 15), whereas in the case of the conductor post provided with the barrier layer. Was able to suppress the resistance change small (Experimental Examples 1 to 14). This is presumably because if there is no barrier layer, peeling occurs between the stress relaxation layer and the conductor post (solder only), and the IC chip or build-up layer cracks starting from this peeling portion. . Further, when the aspect ratio was 1, the resistance change suppressing effect was small (Experimental Example 1), whereas when the aspect ratio was 1.5 or more, the resistance change suppressing effect was large (Experimental Examples 2-8, 10-14). Further, when the diameter of the conductor post was 25 μm and the aspect ratio was 9.6, the effect of suppressing the resistance change was small (Experimental Example 9), whereas the diameter of the conductor post was 30 to 50 μm and the aspect ratio was 1. In the case of 5-8, the resistance change suppression effect was large (Experimental Examples 2-8, 10-14). As for the material of the barrier layer, any of copper, Ni / Au, Pd / Au, Au, and Ni / Pd can be used without any problem, and the thickness of the barrier layer is 0.03 to 0.5 μm. It was. As for the solder composition, it was found that any of a two-component system of Sn-Ag, a three-component system of Sn-Ag-Bi, and a two-component system of Sn-Cu can be used without any problem.

  Similarly, the printed wiring boards of Experimental Examples 16 to 26 manufactured according to the manufacturing method of the above-described embodiment are manufactured with the solder composition, solder composition (with flux), solder Young's modulus, post diameter, and aspect ratio shown in Table 2. did. In Experimental Examples 16 to 26, the thicknesses of the stress relaxation layers were all 75 μm, the post diameters of the conductor posts were all 50 μm, and the barrier layers were all copper layers having a thickness of 0.3 μm. Further, the solder Young's modulus was obtained by an ultrasonic flaw detection method. An IC chip was mounted on each printed wiring board, and then a sealing resin was filled between the IC chip, the pudding, and the wiring board. Then, the same heat cycle test as before was performed, and the resistance change after 1000 cycles was measured. The results are shown in Table 2.

  As apparent from Table 2, when the solder Young's modulus was 37 GPa (Experimental Example 16) or 70 GPa (Experimental Example 26), the resistance change suppressing effect was small, but the solder Young's modulus was 40, 62.3. In the case of 63.7, 67, 68 GPa, the resistance change suppression effect was large (Experimental Examples 17, 18, 20, 24, 25). With respect to this point, when the solder Young's modulus is 37 GPa, the stress relaxation layer and the conductor post move together with the printed wiring board to increase the amount of deformation, and the resistance change due to the fact that the stress relaxation layer cannot absorb much stress. It is inferred that the inhibitory effect was small. Further, when the solder Young's modulus is 70 GPa, it is presumed that the effect of suppressing the resistance change was small because the conductor post prevented the deformation of the stress relaxation layer too much.

It is sectional drawing showing the use condition of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of a printed wiring board. It is sectional drawing showing the preparation procedure of another printed wiring board. It is sectional drawing showing the other printed wiring board preparation procedure. It is sectional drawing showing the use condition of the conventional printed wiring board.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Printed wiring board, 12 core board | substrate, 14 core board | substrate body, 16 wiring pattern, 18 through-hole conductor, 20 buildup layer, 22 insulating layer, 24 conductor circuit layer, 24a outer layer conductor circuit layer, 26 filled via, 30 stress relaxation layer , 32 Through-hole, 34 Conductor post, 36 Barrier layer, 36a Land part, 37 Solder core, 38 Solder bump part, 40 Mounting surface, 48 Solder bump, 50 IC chip, 52 pad, 300 Low elastic material sheet 360 Electroless copper plating film, 362 resist, 364 resist, 366 resist, 368 metal coating, 380 solder.

Claims (7)

Conductor circuit layers and insulating layers are alternately formed on at least one surface of the core substrate, and each conductor circuit layer is electrically connected through a through-hole conductor or via hole penetrating the insulating layer and mounted on the mounting surface. A printed wiring board in which the electronic component is electrically connected to the conductor circuit layer,
A stress relaxation layer made of a material having a lower elastic modulus than the insulating resin, which is formed so as to cover the outer layer conductor circuit layer closest to the outer layer among the plurality of conductor circuit layers;
A through hole penetrating the stress relaxation layer;
A conductor post comprising a barrier layer formed on the inner wall of the through-hole and a solder core formed inside the barrier layer, and electrically connecting the outer conductor circuit layer and the electronic component;
Printed wiring board with   The printed wiring board according to claim 1, wherein the conductor post has an aspect ratio of 1.5 or more.   The printed wiring board according to claim 1, wherein the core is made of a solder having a Young's modulus of 40 GPa or more and less than 70 GPa by an ultrasonic flaw detection method.   The printed wiring board according to claim 1, wherein the core is made of lead-free solder made of at least two kinds of metals selected from the group consisting of Sn, Ag, Cu, In, Bi, and Zn.   The printed wiring board according to claim 1, wherein the barrier layer has a thickness of 0.03 to 5 μm.   The printed wiring board according to claim 1, wherein the barrier layer is made of a metal selected from the group consisting of Cu, Au, Pd, Ni—Au, Ni—Pd—Au, and Ni—Pd.   The said stress relaxation layer is a printed wiring board in any one of Claims 1-6 whose Young's modulus measured based on JISK7113 is 10MPa-1GPa.

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