WO2021081943A1 - 芯片堆叠封装结构及其封装方法、电子设备 - Google Patents

芯片堆叠封装结构及其封装方法、电子设备 Download PDF

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Publication number
WO2021081943A1
WO2021081943A1 PCT/CN2019/114866 CN2019114866W WO2021081943A1 WO 2021081943 A1 WO2021081943 A1 WO 2021081943A1 CN 2019114866 W CN2019114866 W CN 2019114866W WO 2021081943 A1 WO2021081943 A1 WO 2021081943A1
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WIPO (PCT)
Prior art keywords
redistribution layer
bare
chip
layer
barrier wall
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Application number
PCT/CN2019/114866
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English (en)
French (fr)
Inventor
蔡崇宣
张弛
陶军磊
赵南
蒋尚轩
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980101842.7A priority Critical patent/CN114631179B/zh
Priority to PCT/CN2019/114866 priority patent/WO2021081943A1/zh
Publication of WO2021081943A1 publication Critical patent/WO2021081943A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • This application relates to the field of electronic technology, and in particular to a chip stack packaging structure and its packaging method, and electronic equipment.
  • FCBGA flip chip ball grid array
  • the components in the package structure differ in degree of thermal deformation due to different materials.
  • relative deformation forces will be formed between the components, and problems such as delamination will occur under the action of the deformation forces, and the problem of low board level reliability (BLR) of the package structure occurs.
  • BLR board level reliability
  • the embodiments of the present application provide a chip stack packaging structure, a packaging method thereof, and electronic equipment, which are used to solve the problem of component delamination in a large-size packaging structure.
  • a chip stack package structure including: a redistribution layer; a plurality of bare chips arranged at intervals, with a first gap between adjacent bare chips; a soldering assembly located between the redistribution layer and the bare chip, It is used to support the bare chip and realize the electrical connection between the bare chip and the redistribution layer; the barrier wall is arranged on the side of the redistribution layer facing the bare chip and corresponds to the position of the first gap; the first underfill layer is filled in the redistribution layer.
  • the wiring layer, the bare chip, and the area enclosed by the barrier wall, and wrap the soldering components; the plastic encapsulation layer covers the bare chip, and fills the first gap.
  • the first underfill layer is only located in the area enclosed by the bare chip, barrier wall and redistribution layer, and is not filled in adjacent areas.
  • the plastic encapsulation layer is filled in the first gap, and the plastic encapsulation layer covers the sides of the bare chips. Since the elastic modulus of the material constituting the plastic encapsulation layer is greater than the elastic modulus of the material constituting the first underfill layer, the strain of the plastic encapsulation layer relative to the first underfill rubber layer is small, that is, the plastic encapsulation layer is relative to the first underfill layer. The degree of deformation of the adhesive layer is small.
  • the chip stack package structure provided by the embodiments of the present application can not only improve the performance of high-speed transmission, but also enhance the board-level reliability and package-level reliability of the chip stack package structure.
  • the second gap is smaller than the minimum space for capillary flow of the filler that constitutes the first underfill layer.
  • the width of the barrier wall is greater than the width of the first gap corresponding to its position, and along the first direction, there is a second gap between the barrier wall and the surface of the bare chip facing the redistribution layer; wherein, the first direction is perpendicular to The direction of the redistribution layer.
  • the thickness of the barrier wall is greater than the distance from the surface of the bare chip facing the redistribution layer to the redistribution layer, and there is a second gap between the barrier wall and the surface of the bare chip facing the adjacent bare chip; wherein ,
  • the first direction is the direction perpendicular to the redistribution layer.
  • the angle between the surface of the barrier wall that intersects the redistribution layer and the redistribution layer is an acute angle. In this way, the crack propagation between the first underfill adhesive layer and the surface of the barrier wall is relatively slow, and the probability of delamination between the first underfill adhesive layer and the barrier wall is reduced.
  • a plurality of bare chips are arranged in at least one row, and the bare chips located in the same row are arranged side by side.
  • Simple structure
  • At least one row has multiple rows, and barrier walls located between adjacent bare chips in the same row are connected to barrier walls located between adjacent rows.
  • the filling glue can be prevented from overflowing from the gap between adjacent barrier walls and flowing to the first gap between adjacent bare chips.
  • the soldering assembly includes a first bump, a second bump, and a first solder ball; the first bump is electrically connected to the redistribution layer, the second bump is electrically connected to the bare chip, and the first solder ball is used for Weld the first bump and the second bump.
  • the chip stack package structure further includes: a substrate located on the side of the redistribution layer away from the bare chip and electrically connected to the redistribution layer; the heat dissipation cover has a groove; the heat dissipation cover is aligned with the substrate, and the groove is formed with the substrate
  • the accommodating cavity; the bare chip and the redistribution layer are both located in the accommodating cavity.
  • a packaging method of a chip stack packaging structure which includes: forming a barrier wall on a redistribution layer; electrically connecting a plurality of bare chips to the redistribution layer through soldering components; wherein the barrier wall is adjacent to the redistribution layer.
  • the position of the first gap between the bare chips corresponds; the area enclosed by the bare chip, the redistribution layer and the barrier wall is filled with underfill and cured to form a first underfill layer; a plastic encapsulation layer covering the bare chip is formed; , The plastic encapsulation layer fills the first gap.
  • an electronic device including the chip stack package structure of any one of the first aspects.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of this application.
  • 2a is a schematic diagram of an arrangement of multiple bare chips according to an embodiment of the application.
  • 2b is a schematic diagram of another arrangement of multiple bare chips provided by an embodiment of the application.
  • FIG. 2c is a schematic diagram of yet another arrangement of multiple bare chips according to an embodiment of the application.
  • 2d is a schematic diagram of yet another arrangement of multiple bare chips provided by an embodiment of the application.
  • Fig. 2e is a cross-sectional view along the A1-A2 direction in Fig. 2a provided by an embodiment of the application;
  • Fig. 2f is another cross-sectional view along the A1-A2 direction in Fig. 2a provided by an embodiment of the application;
  • FIG. 2g is another cross-sectional view along the A1-A2 direction in FIG. 2a according to an embodiment of the application;
  • FIG. 2h is another cross-sectional view along the A1-A2 direction in FIG. 2a according to an embodiment of the application;
  • 3a is a cross-sectional view of a chip stack package structure provided by an embodiment of the application.
  • 3b is a schematic structural diagram of another chip stack package structure provided by an embodiment of the application.
  • 3c is a schematic structural diagram of yet another chip stack package structure provided by an embodiment of the application.
  • 3d is a schematic structural diagram of yet another chip stack package structure provided by an embodiment of the application.
  • 3e is a schematic structural diagram of yet another chip stack package structure provided by an embodiment of the application.
  • 4a is a schematic diagram of the distribution of bare chips and barrier walls provided by an embodiment of the application.
  • 4b is a schematic diagram of another bare chip and barrier wall distribution provided by an embodiment of the application.
  • 4c is another schematic diagram of the distribution of bare chips and barrier walls according to an embodiment of the application.
  • FIG. 5 is a cross-sectional view of another chip stack package structure provided by an embodiment of the application.
  • 6a is a cross-sectional view of another chip stack package structure provided by an embodiment of the application.
  • 6b is a cross-sectional view of another chip stack package structure provided by an embodiment of the application.
  • 6c is a cross-sectional view of another chip stack package structure provided by an embodiment of the application.
  • FIGS. 7a-7k are schematic diagrams of the packaging process of a chip stack package structure provided by an embodiment of the application.
  • FIGS. 8a-8d are cross-sectional views of a chip stack package structure provided by related technologies.
  • 1-electronic equipment 2-display module; 3-middle frame; 4-shell; 5-cover plate; 100-chip stack package structure; 10-rewiring layer; 20-bare chip; 30-welded components; 31 -First bump; 32- second bump; 33- first solder ball; 40- first underfill layer; 45- non-conductive filling material; 50- plastic encapsulation layer; 60- substrate; 70- heat dissipation cover; 81-second solder ball; 82-second underfill adhesive layer; 85-barrier wall; 90-thermal conductive adhesive layer.
  • the embodiment of the application provides an electronic device, which can be a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, a car computer, etc., or a smart display wearable device such as a smart watch, a smart bracelet, or Communication equipment such as servers, storages, base stations, or smart cars, etc.
  • a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, a car computer, etc.
  • a smart display wearable device such as a smart watch, a smart bracelet, or Communication equipment such as servers, storages, base stations, or smart cars, etc.
  • Communication equipment such as servers, storages, base stations, or smart cars, etc.
  • the electronic device 1 mainly includes a display module 2, a middle frame 3, a casing (also called a battery cover, a rear casing) 4 and a cover 5.
  • the display module 2 has a light-emitting side where the display screen can be seen and a back surface disposed opposite to the above-mentioned light-emitting side.
  • the back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.
  • the above-mentioned display module 2 includes a display panel (DP).
  • the display module 2 is a liquid crystal display module.
  • the above-mentioned display screen is a liquid crystal display (LCD).
  • the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display (a side away from the side of the LCD for displaying images).
  • BLU backlight unit
  • the backlight module can provide a light source to the liquid crystal display, so that each sub-pixel in the liquid crystal display can emit light to realize image display.
  • the display module 2 is an organic light emitting diode display module.
  • the above-mentioned display screen is an organic light emitting diode (OLED) display screen. Since each sub-pixel in the OLED display screen is provided with an electroluminescent layer, the OLED display screen can realize self-luminescence after receiving the working voltage. In this case, there is no need to provide the above-mentioned backlight module in the display module 2 with the OLED display screen.
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3, and the cover plate 5 may be, for example, cover glass (CG), which may have certain toughness.
  • CG cover glass
  • the middle frame 3 is located between the display module 2 and the housing 4, and the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. . After the casing 4 and the middle frame 3 are closed, the above-mentioned internal elements are located between the casing 4 and the middle frame 3.
  • internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc.
  • the above-mentioned electronic device 1 also includes electronic devices such as a motherboard, a system-on-chip (SOC), and a chip stack package structure arranged on a PCB.
  • the PCB is used to carry the above-mentioned electronic devices and complete signal interaction with the above-mentioned electronic devices.
  • the chip stack package structure As an example, if the chip stack package structure has problems such as cracks and film breakage, the performance of the chip stack package structure will be affected.
  • the chip stack package structure 100 includes a redistribution layer 10 and a plurality of die 20 arranged at intervals.
  • the arrangement of the multiple bare chips 20 is not limited. In a possible embodiment, the multiple bare chips 20 are randomly arranged in an irregular manner.
  • a plurality of bare chips 20 are arranged regularly. As shown in FIG. 2a, a plurality of bare chips 20 are arranged in at least one row, and the bare chips 20 located in the same row are arranged side by side.
  • a plurality of bare chips 20 are arranged in a row, and the plurality of bare chips 20 are arranged side by side.
  • a plurality of bare chips 20 are arranged in multiple rows, and the bare chips 20 located in the same row are arranged side by side, and the long sides of the plurality of bare chips 20 extend in the same direction.
  • a plurality of bare chips 20 are arranged in multiple rows, and the bare chips 20 located in the same row are arranged side by side.
  • the multiple rows of bare chips 20 include at least one row of bare chips 20 whose long sides extend in the second direction and at least one row of bare chips 20 whose long sides extend in a third direction. Among them, the second direction is perpendicular to the third direction.
  • a plurality of bare chips 20 are arranged in multiple rows, and the bare chips 20 located in the same row are arranged side by side, and the cross-sectional shapes of the bare chips 20 are the same.
  • the plurality of bare chips 20 are arranged at intervals, and there is a first gap between any adjacent bare chips 20. N1.
  • the values of the multiple first gaps N1 may be different.
  • 2a takes the chip stack package structure 100 including four bare chips 20 as an example.
  • the values of N1-1, N1-2, and N1-3 can be different.
  • the values of the multiple first gaps N1 may also be the same.
  • the size of the cross-sectional area of the multiple bare chips 20 may be different. As shown in FIG. 2b, the size of the cross-sectional area of a plurality of bare chips 20 may also be the same.
  • the cross-sectional area of the bare chip 20 in the embodiments of the present application refers to the area of the cross-section of the bare chip 20 parallel to the redistribution layer 10, or understood as the area of the orthographic projection of the bare chip 20 on the redistribution layer 10.
  • the thickness S1 of the plurality of bare chips 20 included in the chip stack package structure 100 along the first direction X is The thickness S1 may be the same. As shown in FIG. 2f (a cross-sectional view along the line A1-A2 in FIG. 2a), the thickness S1 of the plurality of bare chips 20 may also be different.
  • the first direction X in the embodiment of the present application refers to a direction perpendicular to the redistribution layer 10.
  • the bare chip 20 closest to the redistribution layer 10 may be laminated and electrically connected with other bare chips on the side away from the redistribution layer 10 20.
  • the bare chip 20 closest to the redistribution layer 10 is electrically connected to the redistribution layer 10.
  • the redistribution layer 10 has opposite first and second surfaces a1 and a2, and the first surface a1 of the redistribution layer 10 faces the bare chip 20.
  • the bare chip 20 has a first surface b1 and a second surface b2 opposite to each other, and the second surface b2 of the bare chip 20 faces the first surface a1 of the redistribution layer 10.
  • the bare chip 20 may be an active chip, and of course, the bare chip 20 may also be a non-active chip.
  • the second surface b2 of the bare chip 20 may be an active surface of the bare chip 20 or a non-active surface of the bare chip 20.
  • the bare chip 20 is an active chip.
  • the bare chip 20 includes a wafer layer composed of silicon and a wiring layer composed of alternating dielectric layers and metal wiring.
  • the wiring layer is provided on the wafer layer, and the wiring layer is far away from the crystal.
  • the surface of the circular layer serves as the active surface of the bare chip 20.
  • the chip stack package structure 100 further includes a plurality of welding components 30, which are located between the redistribution layer 10 and the bare chip 20, and are used to support the bare chip 20 and realize the bare chip 20 and the redistribution layer. 10's electrical connection.
  • any two welding assemblies 30 are insulated.
  • the welding assembly 30 has a columnar structure, and both ends are electrically connected to the redistribution layer 10 and the bare chip 20, respectively.
  • the soldering assembly 30 includes a first bump 31, a second bump 32, and a first solder ball 33 .
  • the first bump 31 is electrically connected to the redistribution layer 10.
  • the first bump 31 may be directly formed when the redistribution layer 10 is formed, or may be formed when the bare chip 20 and the redistribution layer 10 are packaged.
  • the second bump 32 is electrically connected to the bare chip 20.
  • the second bump 32 is, for example, electrically connected to a pad on the active surface of the bare chip 20.
  • the first bump 31 and the second bump 32 may be, for example, under-bump metallization pads (UBM pads) or copper pillars.
  • UBM pads under-bump metallization pads
  • copper pillars copper pillars
  • the first solder ball 33 is located between the first bump 31 and the second bump 32 and is used for soldering the first bump 31 and the second bump 32.
  • the chip stack packaging structure 100 as shown in FIG. 2e, further includes a dam 85 and a first underfill layer 40.
  • the barrier wall 85 is disposed on the side of the redistribution layer 10 facing the bare chip 20 and corresponds to the position of the first gap N1, and is used to block the first gap N1 between adjacent bare chips 20 and prevent the first underfill layer 40 from entering The first gap N1.
  • the first underfill layer 40 is filled in the area enclosed by the redistribution layer 10, the bare chip 20 and the barrier wall 85, and the first underfill layer 40 wraps the soldering assembly 30.
  • the first underfill layer 40 has a whole layer structure and is filled between the multiple bare chips 20 and the redistribution layer 10.
  • the material constituting the first underfill layer 40 may be thermosetting adhesive, for example.
  • the barrier wall 85 blocks the first gap N1 between the adjacent bare chips 20, it prevents the first underfill layer 40 from filling the first gap N1 between the adjacent bare chips 20, and the first underfill The glue layer 40 does not fill the first gap N1 between adjacent bare chips 20.
  • the size of the barrier wall 85 can be adapted to the amount of underfill, the dispensing method, the minimum space for the capillary flow of the underfill, and the stand-off height (SOH) (ie, the second surface b2 of the bare chip 20).
  • the distance to the first surface a1 of the redistribution layer 10), the arrangement of the bare chips 20, and the size of the first gap N1 are changed in design to prevent the underfill from entering the first between adjacent bare chips 20.
  • the gap N1 is sufficient.
  • the barrier wall 85 is seamlessly connected to the second surface b2 of the bare chip 20. In this way, the underfill can be better prevented from entering the first gap N1 between adjacent bare chips 20.
  • barrier wall 85 and the bare chip 20 adjacent to the barrier wall 85 are not connected.
  • the underfill passes through the second gap N2 and flows into the first gap N1.
  • the second gap N2 between the barrier wall 85 and the bare chip 20 is smaller than the minimum capillary flow space of the underfill that constitutes the first underfill layer 40.
  • the size of the second gap N2 is less than 4um.
  • the thickness h1 of the barrier wall 85 is greater than the second surface b2 of the bare chip 20 to the redistribution layer 10.
  • the distance h2 between the first surface a1 and the barrier wall 85 and the side surface b3 of the bare chip 20 has the above-mentioned second gap N2.
  • the second gap N2 is smaller than that of the first underfill layer 40.
  • the underfill has the smallest space for capillary flow of glue. Therefore, it is difficult for the underfill glue to flow through the second gap N2 and hardly flow to the first gap N1.
  • the barrier wall 85 is only used to form a second gap N2 with the side b3 of the bare chip 20, thereby preventing the flow of the underfill. Therefore, in order to save costs, the thickness h1 of the barrier wall 85 does not need to be very large.
  • the width h3 of the barrier wall 85 is greater than the width h4 of the first gap N1 corresponding to its position (located above the barrier wall 85).
  • the width h3 of the barrier wall 85 is greater than the width h4 of the first gap N1 corresponding to its position (located above the barrier wall 85).
  • the first direction X there is the aforementioned second gap N2 between the barrier wall 85 and the second surface b2 of the bare chip 20.
  • the width direction Y of the barrier wall 85 is perpendicular to the extension direction of the barrier wall 85 and the first direction X.
  • the second gap N2 is smaller than the capillary of the underfill of the first underfill layer 40. Minimal space for flow. Therefore, it is difficult for the underfill glue to flow through the second gap N2 and hardly flow to the first gap N1.
  • the shape of the barrier wall 85 is not limited. In order to facilitate the preparation, in a possible embodiment, as shown in FIG. 3d, the shape of the barrier wall 85 is a rectangular strip.
  • the shape of the cross section of the barrier wall 85 in the width direction of the barrier wall 85 is rectangular.
  • the surface of the barrier wall 85 intersecting the redistribution layer 10 (the surface contacting the first underfill layer 40) is perpendicular to the redistribution layer 10.
  • the angle between the intersecting surface of the barrier wall 85 and the redistribution layer 10 and the redistribution layer 10 is an acute angle instead of a right angle.
  • the shape of the barrier wall 85 is a trapezoidal bar. That is, the shape of the cross-section of the barrier wall 85 in the width direction of the barrier wall 85 is a trapezoid.
  • the surface of the barrier wall 85 that is in contact with the first underfill layer 40 intersects but is not perpendicular to the redistribution layer 10, which can increase the difficulty of delamination between the first underfill layer 40 and the barrier wall 85.
  • the material of the barrier wall 85 is not limited.
  • the material constituting the barrier wall 85 is a polymer material (also referred to as a polymer material).
  • the material of the film layer in the redistribution layer 10 that is in contact with the barrier wall 85 is a dielectric material, it also belongs to a polymer material. Therefore, the barrier wall 85 made of a polymer material has a better bonding effect with the redistribution layer 10, which can reduce the probability of delamination between the barrier wall 85 and the redistribution layer 10.
  • the material constituting the barrier wall 85 is metal. Among them, it can be a simple metal or a metal alloy.
  • the material of the barrier wall 85 is metal
  • it can be prepared by mature processes such as electroplating, photolithography, etc.
  • the preparation method is simple and the cost is low.
  • the elastic modulus of the material constituting the barrier wall 85 is greater than the elastic modulus of the material constituting the first underfill layer 40.
  • the elastic modulus of the material constituting the barrier wall 85 is greater than the elastic modulus of the material constituting the first underfill layer 40, the amount of deformation of the barrier wall 85 is small. Compared with the contact between the first underfill layer 40 and the redistribution layer 10, the barrier rib 85 is in contact with the redistribution layer 10 to reduce the probability of delamination between the barrier rib 85 and the first underfill layer 40 and the redistribution layer 10.
  • multiple barrier walls 85 are provided on the first surface a1 of the redistribution layer 10
  • the multiple barrier walls 85 in a possible embodiment, as shown in FIG. 4a, multiple bare chips 20 are arranged in a row, a plurality of bare chips 20 are arranged in parallel, and a plurality of barrier walls 85 are arranged in parallel.
  • a plurality of bare chips 20 are arranged in multiple rows, in order to prevent the underfill from overflowing from the gap between adjacent barrier walls 85, it flows to the first gap N1 between adjacent bare chips 20.
  • a plurality of bare chips 20 are arranged in multiple rows, and the bare chips 20 located in the same row are arranged side by side.
  • the barrier walls 85 located between the adjacent bare chips 20 in the same row are connected to the barrier walls 85 located between the adjacent bare chips 20 in the row.
  • the chip stack package structure 100 as shown in FIG. 2e, further includes a plastic encapsulation layer 50.
  • the plastic encapsulation layer 50 covers the bare chip 20 and fills the first gap N1 between adjacent bare chips 20.
  • the material constituting the plastic encapsulation layer 50 is epoxy molding compound (EMC), which is prepared and formed by a film encapsulation process (molding).
  • EMC epoxy molding compound
  • the elastic modulus of the material constituting the plastic encapsulation layer 50 is greater than the elastic modulus of the material constituting the first underfill layer 40.
  • the plastic encapsulation layer 50 Due to the poor heat dissipation effect of the plastic encapsulation layer 50, in order to improve the heat dissipation effect of the bare chip 20, in a possible embodiment, as shown in FIG. 5, the plastic encapsulation layer 50 exposes the first surface b1 of the bare chip 20 and covers the bare chip 20. The side b3 of 20 that intersects the first surface b1.
  • the bare chip 20 can directly dissipate heat from the first surface b1 without being conducted through the plastic encapsulation layer 50, and the heat dissipation effect of the bare chip 20 can be improved.
  • the plastic encapsulation layer 50 exposes the first surface b1 of the bare chip 20 with the largest thickness S1.
  • the chip stack package structure 100 further includes a substrate 60.
  • the substrate 60 is located on the side of the redistribution layer 10 away from the bare chip 20 and is electrically connected to the redistribution layer 10.
  • the substrate 60 is located on the side of the second surface a2 of the redistribution layer 10 and is electrically connected to the redistribution layer 10.
  • the manner in which the substrate 60 and the redistribution layer 10 are electrically connected is not limited.
  • the substrate 60 and the redistribution layer 10 are soldered by the second solder balls 81.
  • the chip stack package structure 100 further includes a second underfill layer 82 located between the redistribution layer 10 and the substrate 60.
  • the chip stack package structure 100 further includes a heat dissipation cover 70, and the heat dissipation cover 70 has a groove.
  • the heat dissipation cover 70 is aligned with the substrate 60, and the groove and the substrate 60 form a receiving cavity.
  • the bare chip 20, the soldering assembly 30, and the redistribution layer 10 are all located in the accommodating cavity.
  • the chip stack package structure 100 further includes a thermally conductive adhesive layer 90.
  • the thermally conductive adhesive layer 90 is located between the heat dissipation cover 70 and the plastic encapsulation layer 50, and the heat dissipation cover 70 is bonded to the bare chip 20 and the plastic encapsulation layer 50 through the thermally conductive adhesive layer 90.
  • first bumps 31 are formed on the first surface a1 of the first redistribution layer 10.
  • this step may not be required.
  • a first solder ball 33 is placed on the surface of the first bump 31 away from the first redistribution layer 10.
  • a barrier wall 85 is formed on the first surface a1 of the first redistribution layer 10.
  • second bumps 32 are formed on the second surfaces b2 of the plurality of bare chips 20, respectively.
  • the first bumps 31 and the second bumps 32 are soldered through the first solder balls 33, so that the plurality of bare chips 20 are electrically connected to the redistribution layer 10, respectively.
  • the barrier wall 85 blocks the first gap N1 of the adjacent bare chip 20.
  • underfill is filled between the bare chip 20 and the redistribution layer 10 and cured to form a first underfill layer 40.
  • the first underfill layer 40 is bonded to the bare chip 20, the redistribution layer 10, the barrier wall 85, and the soldering assembly 30. Due to the existence of the barrier wall 85, the barrier wall 85 can block the underfill and prevent the underfill from overflowing into the first gap N1.
  • the above-mentioned plastic encapsulation layer 50 is formed on the side where the first surface b1 of the bare chip 20 is located.
  • the molding layer 50 can be prepared by a molding process (molding).
  • the plastic encapsulation layer 50 plays a role of plastic encapsulation and leveling, and can fill the first gap N1 between the adjacent bare chips 20.
  • the plastic encapsulation layer 50 is connected to the bare chip 20, the first underfill layer 40 and the redistribution layer 10.
  • the plastic encapsulation layer 50 is thinned to expose the first surface b1 of the bare chip 20.
  • the redistribution layer 10 and the substrate 60 are electrically connected through the second solder balls 81, and a second underfill layer 82 is formed between the redistribution layer 10 and the substrate 60.
  • a thermally conductive adhesive layer 90 that is bonded to the plastic encapsulation layer 50 and the bare chip 20 is formed on the side of the plastic encapsulation layer 50 away from the redistribution layer 10.
  • the heat dissipation cover 70 is aligned with the substrate 60, and the heat dissipation cover 70 and the thermal conductive adhesive layer 90 are bonded to form the chip stack package structure 100 as shown in FIG. 6c.
  • the substrate 60 is electrically connected to the PCB on the side away from the redistribution layer 10.
  • the redistribution layer 10 will be deformed.
  • the first gap N1 between the adjacent bare chips 20 and the portion directly below the first gap N1 in the redistribution layer 10 are subjected to greater deformation forces, and the side b3 of the bare chip 20 and the redistribution layer 10 The part directly below the first gap N1 is more prone to failure due to delamination or fracture.
  • the first underfill layer 40 is only located in the area enclosed by the bare chip 20, the barrier wall 85 and the redistribution layer 10.
  • the plastic encapsulation layer 50 is filled in the first gap N1, and the plastic encapsulation layer 50 is in contact with the side surface b3 of the bare chip 20.
  • the plastic encapsulation layer 50 Since the elastic modulus of the material constituting the plastic encapsulation layer 50 is greater than the elastic modulus of the material constituting the first underfill layer 40, the plastic encapsulation layer 50 has a small strain relative to the first underfill layer 40, that is, the plastic encapsulation layer 50 The degree of deformation of the first underfill layer 40 is relatively small. In this way, when the same deformation force is applied to the substrate 60, the degree of deformation of the plastic encapsulation layer 50 relative to the first underfill layer 40 is small. Therefore, compared with the structure in which the first underfill layer 40 is filled in the gap N1 between the adjacent bare chips 20 as shown in FIG. 8a, the possibility of delamination between the plastic encapsulation layer 50 and the bare chip 20 is greatly reduced.
  • the relative deformation force exerted by the plastic encapsulation layer 50 on the bare chip 20 is much smaller than the relative deformation force exerted by the first underfill layer 40 on the bare chip 20.
  • it can be reduced by about 3/4, which can be improved because The warpage and stress of the large-size package structure are affected, and no additional components are needed to solve the above problems, which can save the cost of the large-size package structure.
  • the strength of the material constituting the plastic encapsulation layer 50 is greater than the strength of the material constituting the first underfill layer 40, and the plastic encapsulation layer 50 is less likely to break compared to the first underfill layer 40.
  • the chip stack package structure provided by the embodiments of the present application can not only improve the performance of high-speed transmission, but also enhance the board level reliability (BLR) and package level reliability (PLR) of the chip stack package structure. .
  • the structure shown in FIG. 8c is limited by the process, and the side b3 of the bare chip 20 is still covered with underfill The relative deformation force received by the bare chip 20 is still relatively large.
  • the plastic encapsulation layer 50 covered by the side b3 of the bare chip 20 in the embodiment of the present application can reduce the possibility of delamination between the plastic encapsulation layer 50 and the bare chip 20.
  • the structure shown in FIG. 8d is easier to delaminate due to NCF, and the film layer formed by NCF will There are bubbles, resulting in poor filling effect.
  • the bare chip 20 is filled with underfill glue, which can improve the stability of the chip stack package structure.
  • the connection effect between the plastic encapsulation layer 50 and the bare chip 20 is better. Therefore, the size of the substrate 60 can be appropriately expanded to meet the needs of electronic devices for a large-size fan-out BGA package structure, thereby replacing the higher-cost chip on wafer on substrate (CoWoS).

Abstract

一种芯片堆叠封装结构及其封装方法、电子设备，涉及电子技术领域，用于解决大尺寸封装结构中部件脱层的问题。芯片堆叠封装结构（100），包括：重布线层（10）；多个间隔设置的裸芯片（20），相邻裸芯片（20）之间具有第一间隙（N1）；焊接组件（30），位于重布线层（10）与裸芯片（20）之间，用于支撑裸芯片（20），并实现裸芯片（20）与重布线层（10）的电连接；阻隔墙（85），设置于重布线层（10）朝向裸芯片（20）一侧，且与第一间隙（N1）位置对应；第一底部填充胶层（40），填充于重布线层（10）、裸芯片（20）以及阻隔墙（85）围成的区域内，且包裹焊接组件（30）；塑封层（50），覆盖裸芯片（20），且填充第一间隙（N1）。

Description

芯片堆叠封装结构及其封装方法、电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种芯片堆叠封装结构及其封装方法、电子设备。
背景技术
随着电子技术的发展，电子设备的功能不断的区域丰富化、全面化，使得高阶芯片演进迭代需求与日俱增，芯片的集成度持续的增加，多芯片集成合封成为趋势。由于堆叠的芯片数量增加，也因此驱动了倒装芯片球栅阵列(flipchipball grid array，FCBGA)封装结构尺寸的增大。
但随着封装结构尺寸的增大，封装结构中的各部件因材料不同，导致受热变形程度不一。而因各部件变形程度不一，部件之间会形成相对的变形力，在变形力的作用下出现脱层等问题，出现封装结构板级可靠性(board level reliability，BLR)较低的问题。
发明内容
本申请实施例提供一种芯片堆叠封装结构及其封装方法、电子设备，用于解决大尺寸封装结构中部件脱层的问题。
为达到上述目的，本实施例采用如下技术方案：
第一方面，提供一种芯片堆叠封装结构，包括:重布线层；多个间隔设置的裸芯片，相邻裸芯片之间具有第一间隙；焊接组件，位于重布线层与裸芯片之间，用于支撑裸芯片，并实现裸芯片与重布线层的电连接；阻隔墙，设置于重布线层朝向裸芯片一侧，且与第一间隙位置对应；第一底部填充胶层，填充于重布线层、裸芯片以及阻隔墙围成的区域内，且包裹焊接组件；塑封层，覆盖裸芯片，且填充第一间隙。本申请实施例中，通过在重布线层的第一表面上设置阻隔墙，使第一底部填充胶层仅位于裸芯片、阻隔墙以及重布线层围成的区域内，而不填充于相邻裸芯片之间的第一间隙处，使塑封层填充于第一间隙处，塑封层覆盖裸芯片的侧面。由于构成塑封层的材料的弹性模量，大于构成第一底部填充胶层的材料的弹性模量，因此，塑封层相对第一底部填充胶层的应变小，也就是塑封层相对第一底部填充胶层的变形程度较小。这样一来，在基板施加相同的变形力时，由于塑封层的变形程度小，因此，塑封层与裸芯片脱层的可能性大大降低。此外，由于塑封层的变形程度比第一底部填充胶层的变形程度小，因此，塑封层对裸芯片施加的相对变形力比第一底部填充胶层对裸芯片施加的相对变形力要小很多，通过仿真分析，可减小3/4左右，从而可改善因为大尺寸封装结构的翘曲和应力带来的影响，且无需额外增加部件来解决上述问题，可节约大尺寸封装结构的成本。再者，由于弹性模量大的材料，其强度也高。因此，构成塑封层的材料的强度，大于构成第一底部填充胶层的材料的强度，塑封层相比第一底部填充胶层断裂的可能性降低。因此，本申请实施例提供的芯片堆叠封装结构，既能提高高速传输的 性能，又能加强芯片堆叠封装结构的板级可靠性和封装级可靠性。
可选的，阻隔墙和与该阻隔墙相邻的裸芯片之间具有第二间隙；第二间隙小于，构成第一底部填充胶层的填充胶的毛细流动最小空间。这样一来，既能保证阻隔墙对底部填充胶的阻挡作用。相比阻隔墙与裸芯片接触，又能一方面，降低对工艺精度的要求，另一方面，避免阻隔墙与裸芯片连接后，阻隔墙发生形变时会对裸芯片施加力，影响裸芯片与重布线层电连接的稳定性。
可选的，阻隔墙的宽度大于与其位置对应的第一间隙的宽度，沿第一方向，阻隔墙与裸芯片朝向重布线层的表面之间具有第二间隙；其中，第一方向为垂直于重布线层的方向。这样一来，由于阻隔墙的宽度较大，因此，可减小第一底部填充胶层与重布线层的接触面积，降低第一底部填充胶层对重布线层施加的变形力。
可选的，沿第一方向，阻隔墙的厚度，大于裸芯片朝向重布线层的表面到重布线层的距离，阻隔墙与裸芯片朝向相邻裸芯片的表面之间具有第二间隙；其中，第一方向为垂直于重布线层的方向。这样一来，沿第一方向，阻隔墙与裸芯片没有交叠，便于阻隔墙的制备。
可选的，阻隔墙的与重布线层相交的表面与重布线层的夹角呈锐角。这样一来，第一底部填充胶层与阻隔墙表面的裂纹扩散比较慢，降低第一底部填充胶层与阻隔墙脱层的概率。
可选的，多个裸芯片排成至少一排，位于同一排的裸芯片并列设置。结构简单。
可选的，至少一排为多排，位于同一排中相邻裸芯片之间的阻隔墙，与位于相邻排之间的阻隔墙相连接。这样一来，可以避免填充胶从相邻阻隔墙之间的间隙处溢流，而流动至相邻裸芯片之间的第一间隙处。
可选的，焊接组件包括第一凸点、第二凸点、以及第一焊球；第一凸点与重布线层电连接，第二凸点与裸芯片电连接，第一焊球用于焊接第一凸点和第二凸点。
可选的，芯片堆叠封装结构还包括：基板，位于重布线层远离裸芯片一侧，且与重布线层电连接；散热盖，具有凹槽；散热盖与基板对合，凹槽与基板形成容纳腔；裸芯片和重布线层均位于容纳腔内。
第二方面，提供一种芯片堆叠封装结构的封装方法，包括：在重布线层上形成阻隔墙；将多个裸芯片，分别通过焊接组件与重布线层电连接；其中，阻隔墙与相邻裸芯片之间的第一间隙位置对应；在裸芯片、重布线层以及阻隔墙围成的区域内填充底部填充胶并固化，形成第一底部填充胶层；形成覆盖裸芯片的塑封层；其中，塑封层填充第一间隙。
第三方面，提供一种电子设备，包括第一方面任一项的芯片堆叠封装结构。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2a为本申请实施例提供的一种多个裸芯片的排布方式示意图；
图2b为本申请实施例提供的另一种多个裸芯片的排布方式示意图；
图2c为本申请实施例提供的又一种多个裸芯片的排布方式示意图；
图2d为本申请实施例提供的又一种多个裸芯片的排布方式示意图；
图2e为本申请实施例提供的一种沿图2a中A1-A2向的截面图；
图2f为本申请实施例提供的另一种沿图2a中A1-A2向的截面图；
图2g为本申请实施例提供的又一种沿图2a中A1-A2向的截面图；
图2h为本申请实施例提供的又一种沿图2a中A1-A2向的截面图；
图3a为本申请实施例提供的一种芯片堆叠封装结构的截面图；
图3b为本申请实施例提供的另一种芯片堆叠封装结构的结构示意图；
图3c为本申请实施例提供的又一种芯片堆叠封装结构的结构示意图；
图3d为本申请实施例提供的又一种芯片堆叠封装结构的结构示意图；
图3e为本申请实施例提供的又一种芯片堆叠封装结构的结构示意图；
图4a为本申请实施例提供的一种裸芯片与阻隔墙的分布示意图；
图4b为本申请实施例提供的另一种裸芯片与阻隔墙的分布示意图；
图4c为本申请实施例提供的又一种裸芯片与阻隔墙的分布示意图；
图5为本申请实施例提供的又一种芯片堆叠封装结构的截面图；
图6a为本申请实施例提供的又一种芯片堆叠封装结构的截面图；
图6b为本申请实施例提供的又一种芯片堆叠封装结构的截面图；
图6c为本申请实施例提供的又一种芯片堆叠封装结构的截面图；
图7a-图7k为本申请实施例提供的一种芯片堆叠封装结构的封装过程示意图；
图8a-8d为相关技术提供的一种芯片堆叠封装结构的截面图。
附图标记：
1-电子设备；2-显示模组；3-中框；4-壳体；5-盖板；100-芯片堆叠封装结构；10-重布线层；20-裸芯片；30-焊接组件；31-第一凸点；32-第二凸点；33-第一焊球；40-第一底部填充胶层；45-非导电填充材料；50-塑封层；60-基板；70-散热盖；81-第二焊球；82-第二底部填充胶层；85-阻隔墙；90-导热胶层。
具体实施方式
除非另作定义，本申请使用的技术术语或者科学术语应当为本领域技术人员所理解的通常意义。本申请说明书以及权利要求书中使用的术语“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“左”、“右”、“上”以及“下”等方位术语是相对于附图中的部件示意放置的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备可以为手机、电视、显示器、平板电脑、车载电脑等具有显示界面的终端设备，或者为智能手表、智能手环等智能显示穿戴设备，或者为服务器、存储器、基站等通信设备，或者为智能汽车等。本申请实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。
上述显示模组2，包括显示屏(display panel，DP)。
在本申请的一种可能的实施例中，显示模组2为液晶显示模组。在此情况下，上述显示屏为液晶显示屏(liquid crystal display，LCD)。基于此，显示模组2还包括位于液晶显示屏背面(远离LCD用于显示画面的一侧面)的背光模组(back light unit，BLU)。
背光模组可以向液晶显示屏提供光源，以使得液晶显示屏中的各个亚像素(sub pixel)能够发光以实现图像显示。
或者，在本申请的另一种可能的实施例中，显示模组2为有机发光二极管显示模组。在此情况下，上述显示屏为有机发光二极管(organic lightemitting diode，OLED)显示屏。由于OLED显示屏中每个亚像素内设置有电致发光层，所以可以使得OLED显示屏在接收到工作电压后，实现自发光。在此情况下，具有OLED显示屏的显示模组2中无需再设置上述背光模组。
盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。
中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。
上述电子设备1还包括设置于PCB上的主板、系统级芯片(system on chip，SOC)、芯片堆叠封装结构等电子器件，PCB用于承载上述电子器件，并与上述电子器件完成信号交互。
以芯片堆叠封装结构为例，若芯片堆叠封装结构出现裂纹、膜层断裂等问题，会影响芯片堆叠封装结构的性能。
基于此，本申请实施例提供一种芯片堆叠封装结构，如图2a所示，芯片堆叠封装结构100，包括重布线层10和多个间隔设置的裸芯片(die)20。
本申请实施例中，不对多个裸芯片20的排布方式进行限定。在一种可能的实施例中，多个裸芯片20没有规律的任意排布。
在另一种可能的实施例中，多个裸芯片20有规律的排布。如图2a所示，多个裸芯片20排成至少一排，位于同一排的裸芯片20并列设置。
在一些实施例中，如图2a所示，多个裸芯片20排成一排，多个裸芯片20并列设置。
在另一些实施例中，如图2b所示，多个裸芯片20排成多排，位于同一排的裸芯片20并列设置，且多个裸芯片20的长边的延伸方向相同。
在另一些实施例中，如图2c所示，多个裸芯片20排成多排，位于同一排的裸芯片20并列设置。多排裸芯片20中，包括长边沿第二方向延伸的至少一排裸芯片20和长边沿第三方向延伸的至少一排裸芯片20。其中，第二方向和第三方向垂直。
在另一些实施例中，如图2d所示，多个裸芯片20排成多排，位于同一排的裸芯片20并列设置，且裸芯片20的横截面的形状相同。
当然，图2a-图2d中多个裸芯片20的排布方式仅为一种示意，不做任何限定。
应当明白的是，第一，无论多个裸芯片20如何排布，如图2a-图2d所示，多个裸芯片20间隔设置，任意相邻裸芯片20之间具有第一间隙(gap)N1。
第二，在芯片堆叠封装结构100包括的裸芯片20的数量大于2时，相邻裸芯片20之间的第一间隙N1多个。如图2a所示，多个第一间隙N1的值可以不相同。图2a以芯片堆叠封装结构100包括四个裸芯片20为例，相邻裸芯片20之间的第一间隙N1有三个，分别是N1-1、N1-2、N1-3。N1-1、N1-2、N1-3的取值可以不相同。如图2b所示，多个第一间隙N1的值也可以相同。
第三，关于芯片堆叠封装结构100包括的多个裸芯片20的尺寸，如图2a所示，多个裸芯片20的横截面积的大小可以不相同。如图2b所示，多个裸芯片20的横截面积的大小也可以相同。
本申请实施例中裸芯片20的横截面积，是指裸芯片20平行于重布线层10的截面的面积，或者，理解为裸芯片20在重布线层10上的正投影的面积。
第四，关于芯片堆叠封装结构100包括的多个裸芯片20沿第一方向X上的厚度S1，如图2e(沿图2a中A1-A2向的剖视图)所示，多个裸芯片20的厚度S1可以相同。如图2f(沿图2a中A1-A2向的剖视图)所示，多个裸芯片20的厚度S1也可以不相同。本申请实施例中第一方向X，是指垂直于重布线层10的方向。
第五，如图2g(沿图2a中A1-A2向的剖视图)所示，最靠近重布线层10的裸芯片20，在其远离重布线层10一侧还可以层叠电连接有其他裸芯片20，最靠近重布线层10的裸芯片20与重布线层10电连接。
关于重布线层10和裸芯片20的位置关系，如图2e所示，重布线层10具有相对的第一表面a1和第二表面a2，重布线层10的第一表面a1朝向裸芯片20。裸芯片20具有相对的第一表面b1和第二表面b2，裸芯片20的第二表面b2朝向重布线层10的第一表面a1。
其中，裸芯片20可以是有源芯片，当然，裸芯片20也可以是非有源芯片。裸芯片20的第二表面b2可以是裸芯片20的有源面，也可以是裸芯片20的非有源面。
例如，裸芯片20是有源芯片，裸芯片20包括由硅构成的晶圆层，以及由介电层和金属布线交替设置构成的布线层，布线层设置在晶圆层上，布线层远离晶圆层的表面作为裸芯片20的有源面。
如图2e所示，芯片堆叠封装结构100还包括多个焊接组件30，焊接组件30位于重布线层10与裸芯片20之间，用于支撑裸芯片20，并实现裸芯片20与重布线层10的电连接。
应当明白的是，无论焊接组件30如何排布，任意两个焊接组件30绝缘。
关于焊接组件30的结构，在一种可能的实施例中，如图2g所示，焊接组件30为柱状结构，两端分别与重布线层10和裸芯片20电连接。
在另一种可能的实施例中，如图2h(沿图2a中A1-A2向的剖视图)所示，焊接组件30包括第一凸点31、第二凸点32、以及第一焊球33。
第一凸点31与重布线层10电连接。其中，第一凸点31可以在形成重布线层10时直接形成，也可以在将裸芯片20与重布线层10封装时形成。
第二凸点32与裸芯片20电连接。第二凸点32例如与裸芯片20有源面上的焊盘电连接。
第一凸点31和第二凸点32，例如可以是凸点下金属焊盘(under-bump metallization pad，UBM pad)或者铜柱等。
第一焊球33，位于第一凸点31和第二凸点32之间，用于焊接第一凸点31和第二凸点32。
芯片堆叠封装结构100，如图2e所示，还包括阻隔墙(dam)85和第一底部填充胶层40。
阻隔墙85设置于重布线层10朝向裸芯片20一侧，且与第一间隙N1位置对应，用于遮挡相邻裸芯片20之间的第一间隙N1，阻止第一底部填充胶层40进入第一间隙N1。
第一底部填充胶层40，填充于重布线层10、裸芯片20以及阻隔墙85围成的区域内，且第一底部填充胶层40包裹焊接组件30。
第一底部填充胶层40为整层结构，填充于多个裸芯片20与重布线层10之间。构成第一底部填充胶层40的材料例如可以是热固胶。
其中，由于阻隔墙85对相邻裸芯片20之间的第一间隙N1进行遮挡，因此，阻止第一底部填充胶层40填充相邻裸芯片20之间的第一间隙N1，第一底部填充胶层40未填充相邻裸芯片20之间的第一间隙N1。
此外，阻隔墙85尺寸可配合底部填充胶的胶量、点胶方式、底部填充胶的毛细流动最小空间、焊点高度(stand-off height，SOH)(即，裸芯片20的第二表面b2到重布线层10的第一表面a1的距离)、裸芯片20的排布方式以及第一间隙N1的尺寸等参数进行设计变动，能阻止底部填充胶进入相邻裸芯片20之间的第一间隙N1即可。
在一种可能的实施例中，如图2e所示，阻隔墙85与裸芯片20的第二表面b2无缝对接。这样一来，可以较好的阻止底部填充胶进入相邻裸芯片20之间的第一间隙N1。
在另一种可能的实施例中，阻隔墙85和与该阻隔墙85相邻的的裸芯片20未连接。
这样一来，既可以避免阻隔墙85与裸芯片20连接后，阻隔墙85发生形变时会对裸芯片20施加力，影响裸芯片20与重布线层10电连接的稳定性。还可以降低对阻隔墙85的工艺精度要求，可降低成本。
在一些实施例中，如图3a所示，阻隔墙85和与该阻隔墙85相邻的裸芯片20之间具有第二间隙N2。
关于第二间隙N2的大小，为了避免填充底部填充胶时，底部填充胶穿过第二间隙N2流进第一间隙N1处。阻隔墙85与裸芯片20之间的第二间隙N2，小于，构成第一底部填充胶层40的底部填充胶的毛细流动最小空间。
例如，底部填充胶的毛细流动最小空间为4um，那么第二间隙N2的尺寸小于4um。
关于第二间隙N2的位置，在一种可能的实施例中，如图3b所示，沿第一方向X，阻隔墙85的厚度h1，大于裸芯片20的第二表面b2到重布线层10的第一表面a1的距离h2，阻隔墙85与裸芯片20的侧面b3之间具有上述第二间隙N2。
如3a所示，虽然阻隔墙85与裸芯片20的侧面(朝向相邻裸芯片20的表面)b3 之间具有上述第二间隙N2，但是由于第二间隙N2小于构成第一底部填充胶层40的底部填充胶的毛细流动最小空间。因此，底部填充胶很难流过第二间隙N2处，也就几乎不会流动到第一间隙N1处。
其中，由于阻隔墙85仅是用于与裸芯片20的侧面b3形成第二间隙N2，从而阻止底部填充胶的流动。因此，为了节省成本，阻隔墙85的厚度h1也无需非常大。
这样一来，也便于阻隔墙85的制备和裸芯片20与重布线层10的焊接。
关于第二间隙N2的位置，在另一种可能的实施例中，如图3c所示，阻隔墙85的宽度h3大于与其位置对应(位于阻隔墙85上方)的第一间隙N1的宽度h4。沿第一方向X，阻隔墙85与裸芯片20的第二表面b2之间具有上述第二间隙N2。
其中，阻隔墙85的宽度方向Y垂直于阻隔墙85的延伸方向和第一方向X。
同理，如3d所示，虽然阻隔墙85与裸芯片20的第二表面b2之间具有上述第二间隙N2，但是由于第二间隙N2小于第一底部填充胶层40的底部填充胶的毛细流动最小空间。因此，底部填充胶很难流过第二间隙N2处，也就几乎不会流动到第一间隙N1处。
本申请实施例中，不对阻隔墙85的形状进行限定。为了便于制备，在一种可能的实施例中，如图3d所示，阻隔墙85的形状为矩形条。
也就是说，阻隔墙85，在沿阻隔墙85的宽度方向上的截面的形状为矩形。这样一来，阻隔墙85的与重布线层10相交的表面(与第一底部填充胶层40接触的表面)与重布线层10垂直。
由于阻隔墙85的与第一底部填充胶层40接触的表面与重布线层10垂直时，第一底部填充胶层40与阻隔墙85表面的裂纹扩散比较快，第一底部填充胶层40与阻隔墙85脱层较为容易。因此，在另一种可能的实施例中，如图3e所示，阻隔墙85与重布线层10相交的表面与重布线层10的夹角呈锐角，而非直角。
例如，阻隔墙85的形状为梯形条。也就是说，阻隔墙85，在沿阻隔墙85的宽度方向上的截面的形状为梯形。
这样一来，阻隔墙85的与第一底部填充胶层40接触的表面与重布线层10相交但不垂直，可以增加第一底部填充胶层40与阻隔墙85脱层的难度。
此外，本申请实施例中，不对阻隔墙85的材料进行限定。在一种可能的实施例中，构成阻隔墙85的材料为高分子材料(也称为聚合物材料)。
由于重布线层10中与阻隔墙85接触的膜层的材料为介电材料，也属于高分子材料。因此，高分子材料构成的阻隔墙85与重布线层10的粘结效果较好，可降低出现阻隔墙85与重布线层10脱层的概率。
在另一种可能的实施例中，构成阻隔墙85的材料为金属。其中，可以是金属单质，也可以是金属合金。
阻隔墙85的材料为金属时，可以通过电镀、光刻等成熟的工艺制备，制备方法简单，成本低。
在另一种可能的实施例中，构成阻隔墙85的材料的弹性模量，大于，构成第一底部填充胶层40的材料的弹性模量。
由于构成阻隔墙85的材料的弹性模量，大于，构成第一底部填充胶层40的材料 的弹性模量，因此，阻隔墙85的变形量小。相比于第一底部填充胶层40与重布线层10接触，阻隔墙85与重布线层10接触可以降低阻隔墙85与第一底部填充胶层40和重布线层10脱层的概率。
在重布线层10的第一表面a1上设置有多个阻隔墙85的情况下，关于多个阻隔墙85的关系，在一种可能的实施例中，如图4a所示，多个裸芯片20排成一排，多个裸芯片20并列设置，多个阻隔墙85并列设置。
在多个裸芯片20排成多排的情况下，为了避免底部填充胶从相邻阻隔墙85之间的间隙处溢流，而流动至相邻裸芯片20之间的第一间隙N1处。在另一种可能的实施例中，如图4b和图4c所示，多个裸芯片20排成多排，位于同一排的裸芯片20并列设置。位于同一排中相邻裸芯片20之间的阻隔墙85，与位于相邻排裸芯片20之间的阻隔墙85相连接。
也就是说，相交的阻隔墙85相连接，相互之间不具有间隙。
芯片堆叠封装结构100，如图2e所示，还包括塑封层50。
塑封层50覆盖裸芯片20，且填充相邻裸芯片20之间的第一间隙N1。
例如，构成塑封层50的材料为环氧树脂胶粘剂(epoxy molding compound，EMC)，通过膜封工艺(molding)制备形成。
其中，构成塑封层50的材料的弹性模量，大于，构成第一底部填充胶层40的材料的弹性模量。
需要说明的是，如图3a和图3d所示，在阻隔墙85与裸芯片20之间具有第二间隙N2的情况下，由于构成第一底部填充胶层40的底部填充胶没有流动到第二间隙N2。因此，在形成塑封层50时，塑封层50会填充阻隔墙85与裸芯片20之间的第二间隙N2。
由于塑封层50的散热效果较差，为了提高裸芯片20的散热效果，在一种可能的实施例中，如图5所示，塑封层50露出裸芯片20的第一表面b1，覆盖裸芯片20的与第一表面b1相交的侧面b3。
这样一来，裸芯片20可从第一表面b1处直接散热，无需经过塑封层50的传导，可提高裸芯片20的散热效果。
需要说明的是，如图5所示，在多个裸芯片20沿第一方向X上的厚度S1不相同的情况下，塑封层50露出厚度S1最大的裸芯片20的第一表面b1。
如图6a所示，芯片堆叠封装结构100还包括：基板(substrate)60。基板60位于重布线层10远离裸芯片20一侧，且与重布线层10电连接。
也就是说，基板60位于重布线层10的第二表面a2所在侧，且与重布线层10电连接。
其中，不对基板60与重布线层10电连接的方式进行限定。在一种可能的实施例中，如图6b所示，基板60与重布线层10通过第二焊球81焊接。
在这种情况下，如图6b所示，芯片堆叠封装结构100还包括位于重布线层10和基板60之间的第二底部填充胶层82。
如图6b所示，芯片堆叠封装结构100还包括散热盖70，散热盖70具有凹槽。散热盖70与基板60对合，凹槽与基板60形成容纳腔。裸芯片20、焊接组件30以及重 布线层10均位于容纳腔内。
为了使裸芯片20与散热盖70接触，提高裸芯片20的散热效果。在一种可能的实施例中，如图6c所示，芯片堆叠封装结构100还包括：导热胶层90。导热胶层90位于散热盖70与塑封层50之间，散热盖70与裸芯片20和塑封层50通过导热胶层90粘结。
以下，对图6c所示的芯片堆叠封装结构100的封装方法进行示意说明。
如图7a所示，在第一重布线层10的第一表面a1上形成第一凸点31。
其中，若用于封装的第一重布线层10上已经形成有第一凸点31，则可无需执行本步骤。
然后，如图7b所示，在第一凸点31远离第一重布线层10的表面放置第一焊球33。
然后，如图7c所示，在第一重布线层10的第一表面a1上形成阻隔墙85。
其中，制备图7b的结构的过程和制备图7c的结构的过程无先后顺序的要求。
然后，如图7d所示，在多个裸芯片20的第二表面b2上分别形成第二凸点32。
其中，制备图7a的结构的过程和制备图7d的结构的过程无先后顺序的要求。
同理，若用于封装的裸芯片20的第二表面b2上形成第二凸点32，则无需执行本步骤。
然后，如图7e所示，将第一凸点31和第二凸点32通过第一焊球33焊接，以使多个裸芯片20分别与重布线层10电连接。
此时，如图7e所示，阻隔墙85遮挡住相邻裸芯片20的第一间隙N1。
然后，如图7f所示，在裸芯片20与重布线层10之间填充底部填充胶并固化，形成第一底部填充胶层40。
其中，第一底部填充胶层40与裸芯片20、重布线层10、阻隔墙85以及焊接组件30均粘结。由于阻隔墙85的存在，阻隔墙85能对底部填充胶进行阻挡，避免底部填充胶溢流进第一间隙N1中。
然后，如图7g所示，在裸芯片20的第一表面b1所在侧形成上述塑封层50。
例如，可以通过模封工艺(molding)制备得到塑封层50。塑封层50起到塑封填平作用，可填充相邻裸芯片20的第一间隙N1，塑封层50与裸芯片20、第一底部填充胶层40以及重布线层10均连接。
然后，如图7h所示，对塑封层50进行减薄，以露出裸芯片20的第一表面b1。
然后，如图7i所示，将重布线层10与基板60通过第二焊球81电连接，并在重布线层10与基板60之间形成第二底部填充胶层82。
然后，如图7j所示，在塑封层50远离重布线层10的一侧形成与塑封层50和裸芯片20粘结的导热胶层90。
然后，将散热盖70与基板60对合，并使散热盖70与导热胶层90粘结，以形成如图6c所示的芯片堆叠封装结构100。
然后，如图7k所示，在需要将芯片堆叠封装结构100与PCB电连接时，将基板60远离重布线层10一侧与PCB电连接。
通过实际使用和仿真分析发现，芯片堆叠封装结构100中，因基板60在高温、冷 却过程中会产生较大的热机械变形，会对重布线层10施加变形力。尤其是相邻裸芯片20之间的第一间隙N1处和与重布线层10中位于第一间隙N1正下方的部分受到的变形力较大，裸芯片20的侧面b3和重布线层10中位于第一间隙N1正下方的部分比较容易出现因脱层或断裂而失效的问题。
本申请实施例中，通过在重布线层10的第一表面a1上设置阻隔墙85，使第一底部填充胶层40仅位于裸芯片20、阻隔墙85以及重布线层10围成的区域内，而不填充于相邻裸芯片20之间的第一间隙N1处，使塑封层50填充于第一间隙N1处，塑封层50与裸芯片20的侧面b3接触。由于构成塑封层50的材料的弹性模量，大于构成第一底部填充胶层40的材料的弹性模量，因此，塑封层50相对第一底部填充胶层40的应变小，也就是塑封层50相对第一底部填充胶层40的变形程度较小。这样一来，在基板60施加相同的变形力时，由于塑封层50相对第一底部填充胶层40的变形程度小。因此，与图8a所示的第一底部填充胶层40填充于相邻裸芯片20之间的间隙N1处的结构相比，塑封层50与裸芯片20脱层的可能性大大降低。并且塑封层50对裸芯片20施加的相对变形力比第一底部填充胶层40对裸芯片20施加的相对变形力要小很多，通过仿真分析，可减小3/4左右，从而可改善因为大尺寸封装结构的翘曲和应力带来的影响，且无需额外增加部件来解决上述问题，可节约大尺寸封装结构的成本。
再者，由于弹性模量大的材料，其强度也高。因此，构成塑封层50的材料的强度，大于构成第一底部填充胶层40的材料的强度，塑封层50相比第一底部填充胶层40断裂的可能性降低。
因此，本申请实施例提供的芯片堆叠封装结构，既能提高高速传输的性能，又能加强芯片堆叠封装结构的板级可靠性(board levelreliability，BLR)和封装级可靠性(package levelreliability，PLR)。
另外，与图8b所示的由塑封层50替代第一底部填充胶层40的芯片堆叠封装结构相比，由于构成塑封层50的材料的流动性较低，因此，图8b所示的结构中裸芯片20到重布线层10的距离需要比较大，且无法适用于大尺寸的封装结构。而本申请实施例中，由于底部填充胶在毛细现象的作用下，填充效果比较好，因此对焊点的高度和封装结构的尺寸不做特殊的限定，可适用于低焊点、大尺寸的封装结构。
与图8c所示的通过增加一道切割工序形成间隙，然后用塑封层50填充的芯片堆叠封装结构相比，图8c所示的结构由于受工艺限制，裸芯片20的侧面b3仍覆盖有底部填充胶，裸芯片20受到的相对变形力仍然比较大。而本申请实施例中裸芯片20的侧面b3覆盖的使塑封层50，可降低塑封层50与裸芯片20脱层的可能性。
与图8d所示的采用非导电填充材料(nonconductive film，NCF)替代底部填充胶的芯片堆叠封装结构相比，图8d所示的结构由于NCF比较容易脱层，且NCF形成的膜层中会有气泡，导致填充效果较差。而本申请实施例中裸芯片20采用底部填充胶填充，可提高芯片堆叠封装结构的稳定性。
再者，由于本申请实施例提供的芯片堆叠封装结构100，其塑封层50与裸芯片20的连接效果较好。因此，可以适当的扩大基板60的尺寸，以满足电子设备对大尺寸的扇出型BGA封装结构的需求，从而取代成本较高的基片上芯片(chip on wafer on substrate，CoWoS)。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种芯片堆叠封装结构，其特征在于，包括:
    重布线层；
    多个间隔设置的裸芯片，相邻所述裸芯片之间具有第一间隙；
    焊接组件，位于所述重布线层与所述裸芯片之间，用于支撑所述裸芯片，并实现所述裸芯片与所述重布线层的电连接；
    阻隔墙，设置于所述重布线层朝向所述裸芯片一侧，且与所述第一间隙位置对应；
    第一底部填充胶层，填充于所述重布线层、所述裸芯片以及所述阻隔墙围成的区域内，且包裹所述焊接组件；
    塑封层，覆盖所述裸芯片，且填充所述第一间隙。
  2. 根据权利要求1所述的芯片堆叠封装结构，其特征在于，所述阻隔墙和与该阻隔墙相邻的所述裸芯片之间具有第二间隙；所述第二间隙小于，构成所述第一底部填充胶层的填充胶的毛细流动最小空间。
  3. 根据权利要求2所述的芯片堆叠封装结构，其特征在于，所述阻隔墙的宽度大于与其位置对应的所述第一间隙的宽度，沿第一方向，所述阻隔墙与所述裸芯片朝向所述重布线层的表面之间具有所述第二间隙；
    其中，所述第一方向为垂直于所述重布线层的方向。
  4. 根据权利要求2所述的芯片堆叠封装结构，其特征在于，沿第一方向，所述阻隔墙的厚度，大于所述裸芯片朝向所述重布线层的表面到所述重布线层的距离，所述阻隔墙与所述裸芯片朝向相邻裸芯片的表面之间具有所述第二间隙；
    其中，所述第一方向为垂直于所述重布线层的方向。
  5. 根据权利要求1-4任一项所述的芯片堆叠封装结构，其特征在于，所述阻隔墙的与所述重布线层相交的表面与所述重布线层的夹角呈锐角。
  6. 根据权利要求1-5任一项所述的芯片堆叠封装结构，其特征在于，多个所述裸芯片排成至少一排，位于同一排的所述裸芯片并列设置。
  7. 根据权利要求6所述的芯片堆叠封装结构，其特征在于，所述至少一排为多排，位于同一排中相邻所述裸芯片之间的所述阻隔墙，与位于相邻排所述裸芯片之间的所述阻隔墙相连接。
  8. 根据权利要求1-7任一项所述的芯片堆叠封装结构，其特征在于，所述焊接组件包括第一凸点、第二凸点、以及第一焊球；
    所述第一凸点与所述重布线层电连接，所述第二凸点与所述裸芯片电连接，所述第一焊球用于焊接所述第一凸点和所述第二凸点。
  9. 根据权利要求1-8任一项所述的芯片堆叠封装结构，其特征在于，所述芯片堆叠封装结构还包括：
    基板，位于所述重布线层远离所述裸芯片一侧，且与所述重布线层电连接；
    散热盖，具有凹槽；所述散热盖与所述基板对合，所述凹槽与所述基板形成容纳腔；所述裸芯片和所述重布线层均位于所述容纳腔内。
  10. 一种芯片堆叠封装结构的封装方法，其特征在于，包括：
    在重布线层上形成阻隔墙；
    将多个裸芯片，分别通过焊接组件与所述重布线层电连接；其中，所述阻隔墙与相邻所述裸芯片之间的第一间隙位置对应；
    在所述裸芯片、所述重布线层以及所述阻隔墙围成的区域内填充底部填充胶并固化，形成第一底部填充胶层；
    形成覆盖所述裸芯片的塑封层；其中，所述塑封层填充所述第一间隙。
  11. 一种电子设备，其特征在于，包括权利要求1-9任一项所述的芯片堆叠封装结构。
PCT/CN2019/114866 2019-10-31 2019-10-31 芯片堆叠封装结构及其封装方法、电子设备 WO2021081943A1 (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115600542A (zh) * 2022-11-28 2023-01-13 飞腾信息技术有限公司（Cn） 一种芯片封装结构及其设计方法和相关设备
US20230060756A1 (en) * 2021-08-31 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure with multiple gap-filling layers and fabricating method thereof
CN116092956A (zh) * 2023-04-10 2023-05-09 北京华封集芯电子有限公司 芯片封装方法及芯片封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543968A (zh) * 2010-12-31 2012-07-04 财团法人工业技术研究院 三维立体堆叠芯片封装结构
JP2017005175A (ja) * 2015-06-12 2017-01-05 凸版印刷株式会社 半導体パッケージ基板、半導体パッケージおよびその製造方法
CN106816421A (zh) * 2017-03-22 2017-06-09 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN106887393A (zh) * 2017-03-22 2017-06-23 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN208655611U (zh) * 2018-06-26 2019-03-26 华天科技（昆山）电子有限公司 改善翘曲的扇出型晶圆级芯片封装结构
CN109599380A (zh) * 2013-07-10 2019-04-09 台湾积体电路制造股份有限公司 具有坝体结构的中介层上管芯组件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543968A (zh) * 2010-12-31 2012-07-04 财团法人工业技术研究院 三维立体堆叠芯片封装结构
CN109599380A (zh) * 2013-07-10 2019-04-09 台湾积体电路制造股份有限公司 具有坝体结构的中介层上管芯组件及其制造方法
JP2017005175A (ja) * 2015-06-12 2017-01-05 凸版印刷株式会社 半導体パッケージ基板、半導体パッケージおよびその製造方法
CN106816421A (zh) * 2017-03-22 2017-06-09 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN106887393A (zh) * 2017-03-22 2017-06-23 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN208655611U (zh) * 2018-06-26 2019-03-26 华天科技（昆山）电子有限公司 改善翘曲的扇出型晶圆级芯片封装结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230060756A1 (en) * 2021-08-31 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure with multiple gap-filling layers and fabricating method thereof
CN115600542A (zh) * 2022-11-28 2023-01-13 飞腾信息技术有限公司（Cn） 一种芯片封装结构及其设计方法和相关设备
CN116092956A (zh) * 2023-04-10 2023-05-09 北京华封集芯电子有限公司 芯片封装方法及芯片封装结构
CN116092956B (zh) * 2023-04-10 2023-11-03 北京华封集芯电子有限公司 芯片封装方法及芯片封装结构

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