CN114631179A - 芯片堆叠封装结构及其封装方法、电子设备 - Google Patents

芯片堆叠封装结构及其封装方法、电子设备 Download PDF

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CN114631179A
CN114631179A CN201980101842.7A CN201980101842A CN114631179A CN 114631179 A CN114631179 A CN 114631179A CN 201980101842 A CN201980101842 A CN 201980101842A CN 114631179 A CN114631179 A CN 114631179A
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layer
chip
gap
bare chip
bare
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CN114631179B (zh
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蔡崇宣
张弛
陶军磊
赵南
蒋尚轩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种芯片堆叠封装结构及其封装方法、电子设备，涉及电子技术领域，用于解决大尺寸封装结构中部件脱层的问题。芯片堆叠封装结构(100)，包括:重布线层(10)；多个间隔设置的裸芯片(20)，相邻裸芯片(20)之间具有第一间隙(N1)；焊接组件(30)，位于重布线层(10)与裸芯片(20)之间，用于支撑裸芯片(20)，并实现裸芯片(20)与重布线层(10)的电连接；阻隔墙(85)，设置于重布线层(10)朝向裸芯片(20)一侧，且与第一间隙(N1)位置对应；第一底部填充胶层(40)，填充于重布线层(10)、裸芯片(20)以及阻隔墙(85)围成的区域内，且包裹焊接组件(30)；塑封层(50)，覆盖裸芯片(20)，且填充第一间隙(N1)。

Description

PCT国内申请，说明书已公开。

Claims (11)

  1. PCT国内申请，权利要求书已公开。
CN201980101842.7A 2019-10-31 2019-10-31 芯片堆叠封装结构及其封装方法、电子设备 Active CN114631179B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115600542A (zh) * 2022-11-28 2023-01-13 飞腾信息技术有限公司（Cn） 一种芯片封装结构及其设计方法和相关设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230060756A1 (en) * 2021-08-31 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure with multiple gap-filling layers and fabricating method thereof
CN116092956B (zh) * 2023-04-10 2023-11-03 北京华封集芯电子有限公司 芯片封装方法及芯片封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543968A (zh) * 2010-12-31 2012-07-04 财团法人工业技术研究院 三维立体堆叠芯片封装结构
JP2017005175A (ja) * 2015-06-12 2017-01-05 凸版印刷株式会社 半導体パッケージ基板、半導体パッケージおよびその製造方法
CN106816421A (zh) * 2017-03-22 2017-06-09 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN106887393A (zh) * 2017-03-22 2017-06-23 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN208655611U (zh) * 2018-06-26 2019-03-26 华天科技（昆山）电子有限公司 改善翘曲的扇出型晶圆级芯片封装结构
CN109599380A (zh) * 2013-07-10 2019-04-09 台湾积体电路制造股份有限公司 具有坝体结构的中介层上管芯组件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543968A (zh) * 2010-12-31 2012-07-04 财团法人工业技术研究院 三维立体堆叠芯片封装结构
CN109599380A (zh) * 2013-07-10 2019-04-09 台湾积体电路制造股份有限公司 具有坝体结构的中介层上管芯组件及其制造方法
JP2017005175A (ja) * 2015-06-12 2017-01-05 凸版印刷株式会社 半導体パッケージ基板、半導体パッケージおよびその製造方法
CN106816421A (zh) * 2017-03-22 2017-06-09 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN106887393A (zh) * 2017-03-22 2017-06-23 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN208655611U (zh) * 2018-06-26 2019-03-26 华天科技（昆山）电子有限公司 改善翘曲的扇出型晶圆级芯片封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115600542A (zh) * 2022-11-28 2023-01-13 飞腾信息技术有限公司（Cn） 一种芯片封装结构及其设计方法和相关设备

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