TW201724303A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201724303A
TW201724303A TW106112032A TW106112032A TW201724303A TW 201724303 A TW201724303 A TW 201724303A TW 106112032 A TW106112032 A TW 106112032A TW 106112032 A TW106112032 A TW 106112032A TW 201724303 A TW201724303 A TW 201724303A
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Taiwan
Prior art keywords
substrate
semiconductor wafer
main surface
semiconductor device
pad
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TW106112032A
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English (en)
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TWI627689B (zh
Inventor
杉山道昭
木下順弘
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瑞薩電子股份有限公司
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Publication of TW201724303A publication Critical patent/TW201724303A/zh
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Publication of TWI627689B publication Critical patent/TWI627689B/zh

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Abstract

本發明之目的在於在將包含小徑之半導體晶片與大徑之半導體晶片之晶片積層體搭載於基材之上表面之半導體裝置中，防止對2片半導體晶片之連接部施加過度應力。 於支撐基板上搭載大徑之第1半導體晶片後，由於藉由在該第1半導體晶片上搭載小徑之第2半導體晶片，可抑制搭載於第1半導體晶片上之第2半導體晶片之傾斜或晃動，故可抑制過度應力施加於第1半導體晶片與第2半導體晶片之連接部。

Description

半導體裝置
本發明係關於一種半導體裝置之製造方法，且係關於一種有效應用於例如將包含小徑之半導體晶片與大徑之半導體晶片之晶片積層體搭載於基材之上表面之半導體裝置之製造中之技術。
專利文獻1揭示一種於配線基板之上表面搭載有控制器晶片，且於該控制器晶片之上表面積層記憶體晶片之SIP(System In Package：系統級封裝)型半導體裝置。控制記憶體晶片之控制器晶片係經由凸塊(突起)電極而覆晶(面朝下)安裝於配線基板之上表面，且於配線基板與控制器晶片之間隙填充有接著劑。另一方面，記憶體晶片係介隔接著劑而面朝上安裝於控制器晶片之上表面，且記憶體晶片之電極墊(接合墊)與配線基板之電極墊(接合導線)經由導線而電性連接。 專利文獻2及專利文獻3揭示一種於對向配置之金屬基板與配線基板之間搭載有複數個半導體晶片(晶片積層體)之COC(Chip On Chip：層疊式晶片)型半導體裝置。構成晶片積層體之複數個半導體晶片包含複數個記憶體晶片與控制該等記憶體晶片之介面晶片，且經由貫通各個半導體晶片而設置之貫通電極及設置於該貫通電極之兩端之凸塊電極而相互電性連接。上述晶片積層體係面積小於記憶體晶片之介面晶片配置於最接近配線基板之位置，且該介面晶片之凸塊電極與配線基板之電極墊經由導線凸塊而電性連接。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2005-191053號公報 [專利文獻2]日本專利特開2011-187574號公報 [專利文獻3]日本專利特開2010-251408號公報
[發明所欲解決之問題] 實現如上述專利文獻2或專利文獻3之晶片積層體構造之情形，若首先於基材(配線基板)之上表面搭載第1半導體晶片，接著，於該第1半導體晶片上積層較第1半導體晶片更大徑之第2半導體晶片，則會產生第2半導體晶片相對於下層之第1半導體晶片傾斜等組裝上較困難之問題。 其他問題與新穎特徵將自本說明書之記述及附加圖式而明確。 [解決問題之技術手段] 若簡單說明用以解決本申請案中揭示之問題之步驟中之代表性者之概要，則如下所述。 本申請案之一實施形態之半導體裝置之製造方法包含以下步驟。 (a)將具有第1主面、形成於上述第1主面之第1主面焊墊、及形成於上述第1主面焊墊上之第1導電性構件之第1半導體晶片，以與上述第1主面為相反側之第1背面與支撐基板對向之方式配置，而搭載於上述支撐基板上之步驟； (b)於上述(a)步驟後，將具有第2主面、形成於上述第2主面之第2主面焊墊、形成於上述第2主面焊墊上之第2導電性構件、及形成於與上述第2主面為相反側之第2背面且與上述第2主面焊墊電性連接之第2背面焊墊，且外形尺寸小於上述第1半導體晶片之第2半導體晶片，以上述第2背面與上述第1半導體晶片之上述第1主面對向之方式配置，而搭載於上述第1半導體晶片之上述第1主面上，且經由上述第1導電性構件而電性連接上述第1半導體晶片之上述第1主面焊墊與上述第2半導體晶片之上述第2背面焊墊之步驟； (c)於上述(b)步驟後，藉由密封材料密封上述第1半導體晶片、上述第2半導體晶片、及上述第2導電性構件之步驟； (d)於上述(c)步驟後，將具有第3面、形成於上述第3面之複數根接合導線、及形成於與上述第3面為相反側之第4面之複數個突起焊點之基底基板，以上述第3面與上述支撐基板對向之方式配置並以上述密封材料固定，且電性連接上述基底基板之上述接合導線與上述第2半導體晶片之上述第2導電性構件之步驟；及 (e)於上述(d)步驟後，於上述基底基板之上述複數個突起焊點之各者上配置外部端子之步驟。 [發明之效果] 若簡單說明根據本申請案中揭示之發明中之代表性者而獲得之效果，則如以下所述。 於支撐基板上搭載第1半導體晶片後，由於藉由在第1半導體晶片上搭載外形尺寸小於第1半導體晶片之第2半導體晶片，可抑制搭載於第1半導體晶片上之第2半導體晶片之傾斜或晃動，故可抑制過度應力施加於第1半導體晶片與第2半導體晶片之連接部。
以下，基於圖式詳細說明本發明之實施形態。另，於用以說明實施形態之所有圖中，對具有相同功能之構件標附相同符號，並省略其重複之說明。又，於實施形態中，除非特別必要，否則原則上不重複同一或相同之部分之說明。再者，於說明實施形態之圖式中，爲容易理解構成，有即便為俯視圖仍標附陰影線之情形、或即便為剖面圖仍省略陰影線之情形。 (實施形態1) ＜半導體裝置＞ 圖1係實施形態1之半導體裝置之上表面側俯視圖。圖2係該半導體裝置之背面側俯視圖。圖3係圖1之A－A線剖面圖。 本實施形態1之半導體裝置10係於基底基板(基材)11上搭載包含2片半導體晶片(微晶片12及記憶體晶片13)之晶片積層體之SIP (System In Package)型半導體裝置。 基底基板11係具備使環氧樹脂等合成樹脂含浸於例如玻璃纖維或碳纖維而形成之絕緣材料與形成於該絕緣材料之兩面之2層配線層之所謂之2層配線基板。基底基板11之平面形狀由四角形構成，其外形尺寸為例如縱×橫＝14 mm×14 mm，厚度＝0.22 mm。 上述2層配線層包含形成於基底基板11之晶片搭載面(在圖3中為基底基板11之上表面)之複數根接合導線(電極墊)14與形成於基底基板11之背面(安裝面)之複數個突起焊點(電極墊)15。複數根接合導線14及複數個突起焊點15以例如銅(Cu)膜與形成於其表面之電鍍膜構成。電鍍膜藉由以例如錫(Sn)為主成分之金屬膜構成。另，所謂主成分係指構成金屬膜之主要材料，意為亦包含該金屬膜之內部含有微小之雜質或其他金屬材料之情形。 又，複數根接合導線14與複數個突起焊點15之各者經由形成於基底基板11之內部(絕緣材料)之通孔配線16而相互電性連接。再者，基底基板11之晶片搭載面及背面，除了形成有電極墊(接合導線14、突起焊點15)之區域以外，以阻焊劑(絕緣膜)17覆蓋。 於上述基底基板11之晶片搭載面上搭載有微晶片12。微晶片12係在使其主面與基底基板11對向之狀態下搭載於基底基板11之晶片搭載面上。 圖4係微晶片12之主面側俯視圖。圖5係微晶片12之背面側俯視圖。圖6係微晶片12之局部放大剖面圖。 微晶片12之平面形狀由四角形構成，其外形尺寸為例如縱×橫＝6 mm×6 mm，厚度＝50 mm。如圖6所示，微晶片12具有例如p型之矽基板30。又，於矽基板30之主面上形成有構成邏輯電路之電路元件(第2半導體元件)之複數個n通道型MOS(Metal Oxide Semiconductor：金屬氧化物半導體)電晶體(Qn)。即，本實施形態之微晶片12係控制記憶體晶片13之半導體晶片。另，於矽基板30之主面上雖進而亦形成有p通道型MOS電晶體等之構成邏輯電路之其他電路元件(半導體元件)，但省略其等之圖示。 於上述複數個電路元件之上部形成有連接電路元件間之複數層之配線31。該等配線31以例如銅(Cu)或者鋁(Al)等之金屬膜構成。又，於電路元件與配線31之間、及下層之配線31與上層之配線31之間，形成有包含氧化矽膜等之複數層之層間絕緣膜32。再者，於該等層間絕緣膜32中形成有電性連接電路元件與配線31、及下層之配線31與上層之配線31之複數個接觸層33。 於微晶片12之主面之最上層形成有保護邏輯電路之表面保護膜(鈍化膜)34。表面保護膜34包含積層有例如氧化矽膜與氮化矽膜之絕緣膜。又，於微晶片12之最上層形成有藉由使表面保護膜34之一部分開口而露出配線31之一部分而形成之複數個主面焊墊(電極墊)35。 於上述複數個主面焊墊35之各者之表面形成有柱狀之凸塊電極36。凸塊電極36例如以自接近主面焊墊35之側依序積層有銅(Cu)膜、及包含錫(Sn)－銀(Ag)合金之焊錫膜之金屬膜構成。 形成於微晶片12之主面之上述複數個主面焊墊35及形成於其等之表面之凸塊電極36，如圖4所示，沿著微晶片12之4條邊而配置為一行。且，如圖3所示，微晶片12經由該等凸塊電極36而與基底基板11之接合導線14電性連接。 如圖6所示，於微晶片12之矽基板30中形成有自微晶片12之背面到達至配線31之複數個貫通電極37。該等貫通電極37例如藉由將銅(Cu)膜嵌入至於矽基板30開口之貫通孔而形成。又，於微晶片12之背面形成有與上述複數個貫通電極37之各者電性連接之背面焊墊38。背面焊墊38以例如銅(Cu)膜與形成於其表面之電鍍膜構成。電鍍膜藉由以例如錫(Sn)為主成分之金屬膜構成。 如此，形成於微晶片12之複數個電路元件經由配線31、接觸層33、及主面焊墊35而與微晶片12之主面之凸塊電極36電性連接。又，該等電路元件經由配線31、接觸層33、及貫通電極37而與微晶片12之背面之背面焊墊38電性連接。 如圖3所示，於微晶片12之背面上搭載有記憶體晶片13。記憶體晶片13係在使其主面與微晶片12之背面對向之狀態下搭載於微晶片12之背面上。 又，於微晶片12之背面與記憶體晶片13之主面之間隙中填充有接著劑47。於本實施形態1中，作為接著劑47，係使用熱硬化性樹脂薄膜之一種的NCF(Non Conductive Film：非導電薄膜)、或熱硬化性樹脂膏之一種的NCP(Non Conductive Paste：非導電膏)。 另，所謂NCF係由一般社團法人的日本半導體製造裝置協會(SEAJ：Semiconductor Equipment Association of Japan)規定者，係使用於半導體晶片之固定(接著)、或半導體晶片之電極面(主面)與基材(配線基板)之電路面(晶片搭載面)之接著，且不僅兼具底部填充之功能，還同時具有接著·絕緣之功能之薄膜狀之連接材料。 又，NCP亦與NCF相同，係同時具有半導體晶片之固定(接著)、底部填充之功能、及接著·絕緣之功能之連接材料。相對於NCF係預先加工成薄膜狀者，NCP之情形係成為膏狀，且於注入至半導體晶片與基材之間隙等後，經加熱硬化者。由於與NCF相比流動性更高，故具有亦可容易地填充狹窄間隙之優點。 圖7係記憶體晶片13之主面側俯視圖。圖8係記憶體晶片13之局部放大剖面圖。 記憶體晶片13之平面形狀由四角形構成，其外形尺寸為例如縱×橫＝9.2 mm×8.6 mm，厚度＝260 mm。即，搭載於微晶片12之背面上之記憶體晶片13之外形尺寸大於微晶片12之外形尺寸(縱×橫＝6 mm×6 mm)。 如圖8所示，記憶體晶片13具有例如p型之矽基板40。又，於矽基板40之主面上形成有半導體記憶體之一種的DRAM(Dynamic Random Access Memory：動態隨機存取記憶體)之記憶體單元(MC)。DRAM之記憶體單元(MC)包含記憶體單元選擇用MOS電晶體(Qs)與串聯連接於記憶體單元選擇用MOS電晶體(Qs)之資訊儲存用電容元件(C)。另，於矽基板40之主面上雖亦形成有構成DRAM電路(記憶體單元陣列及周邊電路)之其他電路元件(半導體元件)，但省略其等之圖示。另，於本實施形態中，雖針對具有DRAM電路之記憶體晶片13進行說明，但形成於記憶體晶片13之電路亦可為快閃記憶體電路或其他記憶體電路。 於上述複數個電路元件之上部形成有連接電路元件間之複數層之配線41。又，於電路元件與配線41之間、及下層之配線41與上層之配線41之間形成有複數層之層間絕緣膜42。再者，於該等層間絕緣膜42中形成有電性連接電路元件與配線41、及下層之配線41與上層之配線41之複數個接觸層43。 於記憶體晶片13之主面之最上層形成有保護DRAM電路之表面保護膜(鈍化膜)44。又，於記憶體晶片13之最上層形成有藉由使表面保護膜44之一部分開口並使配線41之一部分露出而形成之複數個主面焊墊(電極墊)45。 於上述複數個主面焊墊45之各者之表面形成有球(球體)狀之凸塊電極46。凸塊電極46例如以自接近主面焊墊45之側依序積層有銅(Cu)膜、鎳(Ni)膜、及包含錫(Sn)－銀(Ag)－銅(Cu)合金之焊錫膜之金屬膜構成。 形成於記憶體晶片13之主面之上述複數個主面焊墊45及形成於其等之表面之凸塊電極46，如圖7所示，係配置於記憶體晶片13之短邊(圖7之沿著Y方向之邊)之中央部，且沿著長邊(圖7之沿著X方向之邊)而形成。且，如圖3所示，記憶體晶片13經由該等凸塊電極46而與微晶片12之背面焊墊38電性連接。 另，雖於圖式中簡略化顯示，但形成於記憶體晶片13之主面之上述主面焊墊45之數量為約1200個，例如沿著記憶體晶片13之長邊(X方向)以約300個×4區塊之佈局配置。又，相互鄰接之主面焊墊45之間距於記憶體晶片13之短邊方向(Y方向)為40 mm，長邊方向(X方向)為50 mm。即，該記憶體晶片13係爲了藉由擴大匯流排寬度而謀求資料傳送速度之高速化，而具備較通常之DRAM晶片更多之輸入輸出引腳(主面焊墊45)。因此，經由凸塊電極46而與該記憶體晶片13之主面焊墊45電性連接之微晶片12之背面焊墊38之數量亦為約1200個左右。 如圖3所示，上述記憶體晶片13之背面介隔接著劑48而固定於子基板(支撐基板)50之晶片搭載面(在圖3中為子基板50之下表面)。子基板50例如包含平坦之合成樹脂板，其外形尺寸與基底基板11之外形尺寸相同(例如縱×橫＝14 mm×14 mm)。又，接著劑48為例如稱作晶粒附接膜(Die attach Film：DAF)之兼具晶粒接合劑之功能與切割膠帶之功能之薄膜狀接著劑。 由於上述子基板50係支撐記憶體晶片13之基材，故未形成有配線層。另，子基板50亦可藉合成樹脂以外者，例如玻璃、陶瓷、金屬等之板材構成。 由上述子基板50與基底基板11所包夾之2片半導體晶片(微晶片12及記憶體晶片13)係藉由填充於子基板50與基底基板11之間隙之密封材料49而氣密性密封。 於本實施形態1中，作為上述密封材料49，係使用上述之NCF。又，亦可使用NCP代替NCF。但，若考慮與基底基板11之貼合，則密封材料49之情形，較佳為使用較膏狀之密封材料更易確保平坦度之薄膜狀之密封材料。 另一方面，於形成於基底基板11之背面(安裝面)之複數個突起焊點15之各者之表面上連接有構成半導體裝置10之外部端子之焊錫球(焊錫材料)18。本實施形態1之半導體裝置10經由該等焊錫球18而安裝於未圖示之安裝基板(母板)。即，半導體裝置10之基底基板11係作為用以將搭載於其晶片搭載面上之2片半導體晶片(微晶片12及記憶體晶片13)連接於安裝基板(母板)之中介基板而發揮功能。 上述焊錫球18以例如僅錫(Sn)，錫－鉍(Sn－Bi)合金、或錫－銅－銀(Sn－Cu－Ag)合金等實質上不含鉛(Pb)之所謂之無鉛焊錫構成。 如此，本實施形態1之半導體裝置10係經由形成於微晶片12之主面焊墊35之複數個凸塊電極36而電性連接微晶片12與基底基板11，且經由形成於記憶體晶片13之主面焊墊45之複數個凸塊電極46而電性連接記憶體晶片13與微晶片12。藉此，由於可使介隔微晶片12而電性連接基底基板11與記憶體晶片13之資料傳送路徑之長度最短化，故可謀求資料傳送速度之高速化。 然而，本發明者，針對如本實施形態1之半導體裝置10般，在基底基板11上搭載包含微晶片12與記憶體晶片13之晶片積層體之SIP型半導體裝置之製造方法進行了研究。 一般而言，SIP型半導體裝置之微晶片(控制記憶體晶片之半導體晶片)具有在與外部機器之間進行信號之輸入輸出之外部介面電路與在與內部機器(此處為記憶體晶片)之間進行信號之輸入輸出之內部介面電路。因此，爲了縮短連接基底基板(配線基板)與晶片積層體之資料傳送路徑之長度而實現SIP型半導體裝置之高速動作，較理想為採用於接近基底基板之側配置微晶片，且於該微晶片上積層記憶體晶片之構成。 又，一般而言，於半導體晶片之製造步驟中，藉由縮小半導體晶片之外形尺寸，增加自1片半導體晶圓可取得之晶片數，而謀求生產效率之提高、製造成本之降低。因此，微晶片之外形尺寸具有逐年變小之傾向。然而，記憶體晶片之情形，伴隨大容量化之要求，其外形尺寸具有逐年變大之傾向，最近，一般為至少超過縱×橫＝6 mm×6 mm之外形尺寸。即，微晶片之外形尺寸與記憶體晶片之外形尺寸之差正在逐年擴大。 因此，於SIP型半導體裝置之製造步驟中，於基底基板(配線基板)上搭載小徑之微晶片後，若於微晶片上積層大徑之記憶體晶片，則記憶體晶片相對於微晶片之懸空量變大，從而記憶體晶片易產生傾斜或晃動。其結果，引起過度應力施加於微晶片與記憶體晶片之連接部而使兩者之連接可靠性降低，或記憶體晶片之懸空部中產生龜裂等之SIP型半導體裝置之可靠性及製造良率之降低。 因此，於本實施形態1中，使用以下說明之方法製造SIP型之半導體裝置10。 ＜半導體裝置之製造方法＞ 以下，針對本實施形態1之半導體裝置10之製造方法，一面參照圖式一面按步驟順序進行說明。 1.基材及晶片準備步驟： 圖9(a)係顯示本實施形態1之半導體裝置之製造中使用之大型基板之晶片搭載面之俯視圖，圖9(b)係該大型基板之剖面圖。 首先，準備圖9所示之大型基板100。大型基板100係平面形狀由長方形構成之平坦之基板，且利用以圖9(a)之二點鏈線表示之切割線DL1區劃為複數個(此處為6個)裝置區域。複數個裝置區域之各者，於沿著裝置區域之外緣(切割線DL1)切斷大型基板100時，係成為上述半導體裝置10之子基板50之區域，具有與子基板50相同之外形尺寸。 又，與準備上述大型基板100之步驟並行，切割(切斷)圖10所示之半導體晶圓20，藉此，準備複數個記憶體晶片(第1半導體晶片)13。如圖7及圖8所示，於複數個記憶體晶片13之各者之主面(第1主面)形成有構成DRAM電路之複數個電路元件(第1半導體元件)及複數個主面焊墊(第1主面焊墊)45。又，於複數個主面焊墊45之各者之表面形成有凸塊電極(第1導電性構件)46。 另，形成於主面焊墊45之表面之凸塊電極46並非限於球(球體)狀者，亦可為例如如形成於微晶片12之主面焊墊35之表面之凸塊電極36般之柱狀者。 於切割上述半導體晶圓20時，於其背面貼附上述接著劑48(晶粒附接膜、第1接著劑)，且同時切斷半導體晶圓20與接著劑48。若如此，則於經單片化之複數個記憶體晶片13之各者之背面殘留具有與記憶體晶片13相同之外形尺寸之接著劑48。藉此，於將記憶體晶片13搭載於大型基板100時，無需對大型基板100之各裝置區域供給接著劑之步驟。 2.晶粒接合步驟： 接著，如圖11(大型基板100之俯視圖)及圖12(顯示大型基板100之一個裝置區域之剖面圖)所示，於大型基板100之各裝置區域搭載記憶體晶片13。記憶體晶片13之搭載係根據使記憶體晶片13之背面(貼附有接著劑48之面、第1背面)與大型基板100之晶片搭載面(第1面)對向之所謂之面朝上安裝方式進行。即，於介隔接著劑48將記憶體晶片13之背面貼附於大型基板100之晶片搭載面後，藉由加熱大型基板100，使接著劑48硬化，而將記憶體晶片13固定於大型基板100之晶片搭載面。大型基板100之裝置區域與記憶體晶片13之位置對準係例如利用形成於大型基板100之各裝置區域之基準標記22而進行。 另，記憶體晶片13之晶粒接合並非限定於使用晶粒附接膜(接著劑48)之方法者，亦可根據例如對大型基板100之各裝置區域供給膏狀之接著劑之方法而進行。膏狀之接著劑(附帶膏之劑)具有較晶粒附接膜更廉價之優點。 接著，如圖13及圖14所示，於記憶體晶片13之主面上搭載薄膜狀之接著劑(第2接著劑)47。該接著劑47係上述之NCF，其外形尺寸小於記憶體晶片13之外形尺寸，且，大於下一步驟中搭載於記憶體晶片13之主面上之微晶片12之外形尺寸。另，如上述般，接著劑47亦可以NCP構成。 於記憶體晶片13之主面上搭載如NCF般之薄膜狀之接著劑47之情形時，較佳為採用真空層壓法。藉此，可防止於形成有凸塊電極46之記憶體晶片13之主面與接著劑47之間產生空隙。 接著，如圖15及圖16所示，於記憶體晶片13之主面上搭載微晶片12。如圖4及圖6所示，於微晶片12之主面(第2主面)上形成有構成邏輯電路之複數個電路元件(第2半導體元件)及複數個主面焊墊(第2主面焊墊)35。又，於複數個主面焊墊35之各者之表面上形成有凸塊電極(第2導電性構件)36。再者，如圖5及圖6所示，於微晶片12之背面(第2背面)上形成有與形成於矽基板30之複數個貫通電極37之各者電性連接之複數個背面焊墊38。 另，形成於主面焊墊35之表面之凸塊電極36並非限於柱狀者，亦可為例如如形成於記憶體晶片13之主面焊墊45之表面之凸塊電極46般之球(球體)狀者。又，微晶片12之凸塊電極36或記憶體晶片13之凸塊電極46亦可由金(Au)之突起電極構成。 微晶片12與記憶體晶片13同樣，與準備大型基板100之步驟並行準備。即，藉由切割(切斷)圖17所示之半導體晶圓21，而準備複數個微晶片(第2半導體晶片)12。 於切割上述半導體晶圓21時，於其背面貼附切割薄膜23，且僅切斷半導體晶圓21。若如此，則由於經單片化之複數個微晶片12亦成為貼附於切割薄膜23之狀態，故可將該等微晶片12一併搬送至晶粒接合步驟。 於記憶體晶片13之主面上搭載微晶片12時，於拾取貼附於切割薄膜23之微晶片12並配置於記憶體晶片13之上方後，使其背面與記憶體晶片13之主面對向。接著，藉由將微晶片12按壓於記憶體晶片13之主面上之接著劑47，而電性連接微晶片12之背面焊墊38與記憶體晶片13之凸塊電極46。且，藉由在該狀態下使接著劑47加熱硬化，將微晶片12固定於記憶體晶片13，且兩者之連接部(微晶片12之背面焊墊38、記憶體晶片13之主面焊墊45及凸塊電極46)利用接著劑47予以密封。 3.密封及基板貼合步驟： 接著，如圖18所示，於大型基板100之晶片搭載面上搭載薄膜狀之密封材料49。該密封材料49係上述之NCF。密封材料49係密封記憶體晶片13與微晶片12之構件，具有不會使形成於微晶片12主面之凸塊電極36露出之厚度的膜厚。又，密封材料49具有與大型基板100之外形尺寸相同之外形尺寸，且以覆蓋大型基板100之晶片搭載面整體之方式搭載。 於大型基板100之晶片搭載面上搭載如NCF般之薄膜狀之密封材料49時，較佳為採用真空層壓法。藉此，可防止於記憶體晶片13與接著劑47之間、或微晶片12與接著劑47之間產生空隙。 接著，準備圖19及圖20所示之大型配線基板200。圖19係顯示大型配線基板200之晶片搭載面之俯視圖。圖20係顯示大型配線基板200之安裝面之俯視圖。 大型配線基板200係平面形狀由長方形構成之配線基板，具有與大型基板100相同之外形尺寸。又，大型配線基板200藉由以圖19及圖20之二點鏈線表示之切割線DL2區劃為複數個(此處為6個)裝置區域。複數個裝置區域之各者，於沿著裝置區域之外緣(切割線DL2)切斷大型配線基板200時，係成為上述半導體裝置10之基底基板11之區域，具有與基底基板11相同之構造及相同之外形尺寸。於大型配線基板200之晶片搭載面(第3面)上，於每個裝置區域形成有複數根接合導線14，於安裝面(第4面)上，於每個裝置區域形成有複數個突起焊點15。 接著，如圖21(顯示大型配線基板200之一個裝置區域之剖面圖)所示，藉由使大型配線基板200之晶片搭載面與大型基板100對向，且將大型配線基板200按壓至下方(大型基板100之晶片搭載面方向)，而電性連接大型配線基板200之接合導線14與微晶片12之凸塊電極36。接著，在該狀態下使密封材料49加熱硬化。藉此，包含微晶片12與記憶體晶片13之晶片積層體固定於大型配線基板200與大型基板100之間，且藉由密封材料49而氣密性密封。 另，於上述製造方法中，雖於大型基板100之晶片搭載面上搭載密封材料49後，使大型配線基板200與大型基板100重合，但亦可如圖22所示，預先於大型配線基板200之晶片搭載面貼附密封材料49後，再使大型配線基板200與大型基板100重合。 又，於上述製造方法中，雖使相互具有相同之外形尺寸之大型配線基板200與大型基板100重合(圖21)，但大型配線基板200之外形尺寸亦可小於大型基板100之外形尺寸。 即，亦可將具有與大型基板100相同之外形尺寸之大型配線基板200預先分割為複數個區塊，且如圖23所示，使分割之大型配線基板200以區塊單位與大型基板100重合。又，亦可將大型配線基板200預先對每個裝置區域進行分割，且如圖24所示，使分割之大型配線基板200逐片重合於大型基板100之各裝置區域。該等方法係應用於起因於大型基板100或大型配線基板200之翹曲等，而難以使大型基板100之裝置區域與大型配線基板200之裝置區域正確地對位之情形等且有效之方法。 4.球安裝步驟： 接著，如圖25所示，於形成於大型配線基板200之安裝面之複數個突起焊點15之各者之表面連接焊錫球18。在突起焊點15之表面連接焊錫球18時，係於預先塗佈有助熔劑之突起焊點15之表面暫時固定焊錫球18後，使焊錫球18加熱回焊。 5.切斷步驟： 其後，藉由沿著各自之裝置區域之外緣(切割線DL1、DL2)切斷大型配線基板200及大型基板100，而完成圖1～圖3所示之本實施形態1之半導體裝置10。 如此，於本實施形態1中，於製造在基底基板11上搭載包含微晶片12與記憶體晶片13之晶片積層體之SIP型半導體裝置10時，首先，於大型基板100(子基板50)上搭載外形尺寸較大之記憶體晶片13。接著，於記憶體晶片13上積層外形尺寸小於記憶體晶片13之微晶片12，並電性連接記憶體晶片13與微晶片12。且，最後在微晶片12上積層大型配線基板200(基底基板11)，藉此，電性連接微晶片12與大型配線基板200(基底基板11)。 根據上述製造方法，藉由在外形尺寸較大之記憶體晶片13上積層外形尺寸較小之微晶片12，可抑制上段之微晶片12之傾斜或晃動。藉此，由於不會有過度應力施加於微晶片12與記憶體晶片13之連接部，故可抑制微晶片12與記憶體晶片13之連接可靠性之降低或晶片龜裂之產生，從而可使SIP型半導體裝置10之可靠性及製造良率提高。 ＜實施形態1之變化例＞ 於上述實施形態1中，雖於子基板50(大型基板100)上未設置配線層，但亦可如例如圖26所示，於構成子基板50(大型基板100)之絕緣材料之兩面(晶片搭載面及背面)形成配線51。 該情形，如圖示般，由於藉由於基底基板11之晶片搭載面預先形成配線19，且在基板貼合步驟之前經由形成於密封材料49之貫通電極(導電性構件)52而電性連接子基板50之配線51與基底基板11之配線19，而可於子基板50上亦搭載電子零件，故可使半導體裝置10之安裝密度提高。 又，該情形，作為子基板50之絕緣材料，亦可使用合成樹脂以外者，例如玻璃或陶瓷等。藉此，與使用包含合成樹脂之絕緣材料之情形相比，可使子基板50之厚度更薄。 (實施形態2) 於上述實施形態1之製造方法中，於大型基板100之晶片搭載面上搭載記憶體晶片13與微晶片12後，使大型基板100與大型配線基板200重合。與此相對，於本實施形態2之製造方法中，於大型基板100之晶片搭載面上搭載記憶體晶片13與微晶片12後，於微晶片12之主面上形成基底基板(大型配線基板)。 首先，如圖27(顯示大型基板100之一個裝置區域之剖面圖)所示，根據上述實施形態1之製造方法，於大型基板100之各裝置區域介隔晶粒附接膜等之接著劑48而搭載記憶體晶片13。另，於本實施形態2中使用之大型基板100之兩面(晶片搭載面及背面)，基於搭載於大型基板100之記憶體晶片13之保護與遮光(防止因入射至晶片內之光引起之記憶體單元之軟體錯誤)之目的，而形成黑色之阻焊劑(絕緣層)63。 接著，如圖28所示，於記憶體晶片13之主面上搭載如上述之NCF般之薄膜狀之接著劑47。雖於上述實施形態1中，於記憶體晶片13之主面上搭載外形尺寸小於記憶體晶片13之接著劑47(圖13、圖14)，但於本實施形態2中，使用具有與大型基板100相同之外形尺寸之接著劑47，且於大型基板100之晶片搭載面全面貼附接著劑47。 接著，如圖29所示，於記憶體晶片13之主面上搭載微晶片12，且電性連接微晶片12之背面焊墊38與記憶體晶片13之凸塊電極46後，使接著劑47加熱硬化。藉此，使微晶片12固定於記憶體晶片13，且兩者之連接部(微晶片12之背面焊墊38、記憶體晶片13之主面焊墊45及凸塊電極46)利用接著劑47予以密封。另，接著劑47亦可為如NCP般之膏狀之接著材料。 雖於上述實施形態1中，使用於主面焊墊35之表面形成凸塊電極36之微晶片12，但於本實施形態2中，使用於主面焊墊35之表面上未形成凸塊電極(第2導電性構件)36之微晶片12。 接著，如圖30所示，使用例如真空層壓法於微晶片12之主面及接著劑47之表面貼附絕緣薄膜60。該絕緣薄膜60較理想為以對於下一配線形成步驟中使用之電解電鍍液之耐藥品性、或與配線材料之密著性較高之絕緣材料構成。作為如此之絕緣材料，可例示作為多層配線基板之製造中、換言之、作為配線基板之絕緣材料使用之預浸片或ABF(Ajinomoto Build-up Film)(味之素增層膜：味之素精密技術公司商品名)等。 接著，如圖31所示，於形成於微晶片12之主面之主面焊墊35之上部之絕緣薄膜60上形成複數個開口61，且使主面焊墊35於該等開口61之底部露出。開口61係藉由例如對主面焊墊35之上部之絕緣薄膜60照射雷射光束而形成。 接著，如圖32所示，於絕緣薄膜60之表面及開口61之內部形成包含銅(Cu)等之配線62，且電性連接形成於微晶片12之主面之主面焊墊35與配線62。 形成配線62時，首先，於絕緣薄膜60之表面及開口61之內部使用無電解電鍍法或濺射法，形成包含薄的銅(Cu)膜之屏蔽層。接著，於使用電解電鍍法於屏蔽層之表面形成厚的銅(Cu)膜後，以將光阻膜設為遮罩之蝕刻將2層之銅(Cu)膜圖案化。 接著，如圖33所示，於形成有配線62之絕緣薄膜60之表面全面貼附第2層絕緣薄膜64後，藉由例如對絕緣薄膜64照射雷射光束，而於配線62之上部之絕緣薄膜64形成通孔(開口)65，從而使配線62於通孔65之底部露出。 接著，如圖34所示，於第2層絕緣薄膜64之表面及通孔65之內部形成包含銅(Cu)膜之第2層配線66，且通過通孔65而電性連接第2層配線66與第1層配線62。第2層配線66可藉由與第1層配線62相同之方法形成。 接著，如圖35所示，於絕緣薄膜64之表面形成用以保護配線66之阻焊劑(絕緣膜)67後，藉由蝕刻阻焊劑67使第2層配線66之一部分露出，而形成複數個突起焊點(電極墊)68。根據至此之步驟，於微晶片12之主面上形成具有2層之配線62、66之基底基板69。 接著，於基底基板69之突起焊點68之表面形成包含鎳(Ni)膜與金(Au)膜之電鍍膜(未圖示)後，如圖36所示，於突起焊點68之表面連接焊錫球18。焊錫球18之連接以與實施形態1之焊錫球18相同之方法進行。 接著，如圖37所示，卸除不需要之大型基板100。其時，爲了記憶體晶片13之遮光及保護，而於記憶體晶片13之背面預先留下阻焊劑63。 其後，藉由切斷基底基板69，而完成如圖38所示之本實施形態2之半導體裝置70。另，此處，雖於卸除不需要之大型基板100後切斷基底基板69，但亦可於切斷基底基板69與大型基板100而將半導體裝置70單片化後，自記憶體晶片13之背面卸除大型基板100。 根據上述製造方法，藉由在外形尺寸較大之記憶體晶片13上積層外形尺寸較小之微晶片12，可抑制上段之微晶片12之傾斜或晃動。藉此，由於不會有過度應力施加於微晶片12與記憶體晶片13之連接部，故可抑制微晶片12與記憶體晶片13之連接可靠性之降低或晶片龜裂之產生，從而可使SIP型半導體裝置70之可靠性及製造良率提高。 又，根據上述製造方法，由於在球安裝步驟後卸除不需要之大型基板100，故與實施形態1之半導體裝置10相比，可實現更薄型之半導體裝置70。 ＜實施形態2之變化例＞ 於上述實施形態2中，雖於球安裝步驟後卸除大型基板100，但亦可與實施形態1相同，留下大型基板100。該情形，如圖39所示，由於切斷大型基板100而獲得之子基板(支撐基板)71係固定於記憶體晶片13之背面側，故可使半導體裝置70之機械強度提高。另，該情形時，由於入射至記憶體晶片13之光被子基板71遮蔽，故亦可不於大型基板100之表面設置黑色之阻焊劑63。 又，該情形時，由於與實施形態1之變化例(圖26)相同地，藉由於子基板71形成配線，而於子基板71上亦可搭載電子零件，故可使半導體裝置70之安裝密度提高。 以上，雖基於實施形態具體說明由本發明者完成之發明，但本發明並非限定於至此所記載之實施形態者，當然可於不脫離其主旨之範圍內進行各種變更。 (變化例1) 例如，於上述實施形態1、2中，作為半導體裝置之外部端子，雖採用於基底基板之突起焊點(電極墊)之表面形成球(球體)狀之焊錫材料(焊錫球)之所謂之BGA(Ball Grid Array：球狀柵格陣列)構造，但亦可代替焊錫球，採用以少量之焊錫材料包覆突起焊點之表面之所謂之LGA(Land Grid Array：平台柵格陣列)構造。 (變化例2) 又，於上述實施形態1、2中，作為記憶體晶片雖例示形成有DRAM之半導體晶片，但記憶體晶片亦可為形成有快閃記憶體之半導體晶片、或形成有SRAM(Static Random Access Memory：靜態隨機存取記憶體)之半導體晶片。 (變化例3) 又，於上述實施形態1、2中，作為基底基板(大型配線基板)雖例示2層配線基板，但亦可為具有4層或其以上之配線層之多層配線基板。
10‧‧‧半導體裝置
11‧‧‧基底基板(基材)
12‧‧‧微晶片(第2半導體晶片)
13‧‧‧記憶體晶片(第1半導體晶片)
14‧‧‧接合導線(電極墊)
15‧‧‧突起焊點(電極墊)
16‧‧‧通孔配線
17‧‧‧阻焊劑(絕緣層)
18‧‧‧焊錫球(焊錫材料)
19‧‧‧配線
20‧‧‧半導體晶圓
21‧‧‧半導體晶圓
22‧‧‧基準標記
23‧‧‧切割薄膜
30‧‧‧矽基板
31‧‧‧配線
32‧‧‧層間絕緣膜
33‧‧‧接觸層
34‧‧‧表面保護膜(鈍化膜)
35‧‧‧主面焊墊(第2主面焊墊、電極墊)
36‧‧‧凸塊電極(第2導電性構件)
37‧‧‧貫通電極
38‧‧‧背面焊墊
40‧‧‧矽基板
41‧‧‧配線
42‧‧‧層間絕緣膜
43‧‧‧接觸層
44‧‧‧表面保護膜(鈍化膜)
45‧‧‧主面焊墊(第1主面焊墊、電極墊)
46‧‧‧凸塊電極(第1導電性構件)
47‧‧‧接著劑(第2接著劑)
48‧‧‧接著劑(第1接著劑)
49‧‧‧密封材料
50‧‧‧子基板(支撐基板)
51‧‧‧配線
52‧‧‧貫通電極(導電性構件)
60‧‧‧絕緣薄膜(薄膜)
61‧‧‧開口
62‧‧‧配線
63‧‧‧阻焊劑(絕緣膜)
64‧‧‧絕緣薄膜
65‧‧‧通孔(開口)
66‧‧‧配線
67‧‧‧阻焊劑(絕緣膜)
68‧‧‧突起焊點(電極墊)
69‧‧‧基底基板
70‧‧‧半導體裝置
71‧‧‧子基板(支撐基板)
100‧‧‧大型基板
200‧‧‧大型配線基板
C‧‧‧資訊儲存用電容元件
DL1‧‧‧切割線
DL2‧‧‧切割線
MC‧‧‧記憶體單元
Qn‧‧‧n通道型MOS電晶體
Qs‧‧‧記憶體單元選擇用MOS電晶體
圖1係實施形態1之半導體裝置之上表面側俯視圖。 圖2係實施形態1之半導體裝置之背面側俯視圖。 圖3係圖1之A－A線剖面圖。 圖4係微晶片之主面側俯視圖。 圖5係微晶片之背面側俯視圖。 圖6係微晶片之局部放大剖面圖。 圖7係記憶體晶片之主面側俯視圖。 圖8係記憶體晶片之局部放大剖面圖。 圖9(a)係顯示實施形態1之半導體裝置之製造中使用之大型基板之晶片搭載面之俯視圖，(b)係大型基板之剖面圖。 圖10係實施形態1之半導體裝置之製造中使用之半導體晶圓之俯視圖。 圖11係顯示實施形態1之半導體裝置之製造方法之俯視圖。 圖12係顯示實施形態1之半導體裝置之製造方法之局部放大剖面圖。 圖13係顯示接續圖11之半導體裝置之製造方法之俯視圖。 圖14係顯示接續圖12之半導體裝置之製造方法之局部放大剖面圖。 圖15係顯示接續圖13之半導體裝置之製造方法之俯視圖。 圖16係顯示接續圖14之半導體裝置之製造方法之局部放大剖面圖。 圖17係實施形態1之半導體裝置之製造中使用之半導體晶圓之俯視圖。 圖18係顯示接續圖16之半導體裝置之製造方法之局部放大剖面圖。 圖19係顯示實施形態1之半導體裝置之製造中使用之大型配線基板之晶片搭載面之俯視圖。 圖20係顯示實施形態1之半導體裝置之製造中使用之大型配線基板之安裝面之俯視圖。 圖21係顯示接續圖18之半導體裝置之製造方法之局部放大剖面圖。 圖22係顯示接續圖16之半導體裝置之製造方法之另一例之局部放大剖面圖。 圖23係顯示接續圖18之半導體裝置之製造方法之另一例之俯視圖。 圖24係顯示接續圖18之半導體裝置之製造方法之另一例之俯視圖。 圖25係顯示接續圖21之半導體裝置之製造方法之局部放大剖面圖。 圖26係顯示實施形態1之半導體裝置之變化例之剖面圖。 圖27係顯示實施形態2之半導體裝置之製造方法之局部放大剖面圖。 圖28係顯示接續圖27之半導體裝置之製造方法之局部放大剖面圖。 圖29係顯示接續圖28之半導體裝置之製造方法之局部放大剖面圖。 圖30係顯示接續圖29之半導體裝置之製造方法之局部放大剖面圖。 圖31係顯示接續圖30之半導體裝置之製造方法之局部放大剖面圖。 圖32係顯示接續圖31之半導體裝置之製造方法之局部放大剖面圖。 圖33係顯示接續圖32之半導體裝置之製造方法之局部放大剖面圖。 圖34係顯示接續圖33之半導體裝置之製造方法之局部放大剖面圖。 圖35係顯示接續圖34之半導體裝置之製造方法之局部放大剖面圖。 圖36係顯示接續圖35之半導體裝置之製造方法之局部放大剖面圖。 圖37係顯示接續圖36之半導體裝置之製造方法之局部放大剖面圖。 圖38係顯示實施形態2之半導體裝置之剖面圖。 圖39係顯示實施形態2之半導體裝置之變化例之剖面圖。
12‧‧‧微晶片(第2半導體晶片)
13‧‧‧記憶體晶片(第1半導體晶片)
14‧‧‧接合導線(電極墊)
15‧‧‧突起焊點(電極墊)
16‧‧‧通孔配線
35‧‧‧主面焊墊(第2主面焊墊、電極墊)
36‧‧‧凸塊電極(第2導電性構件)
37‧‧‧貫通電極
38‧‧‧背面焊墊
45‧‧‧主面焊墊(第1主面焊墊、電極墊)
46‧‧‧凸塊電極(第1導電性構件)
47‧‧‧接著劑(第2接著劑)
48‧‧‧接著劑(第1接著劑)
49‧‧‧密封材料
100‧‧‧大型基板
200‧‧‧大型配線基板

Claims (8)

  1. 一種半導體裝置，其包含： (a)第1基板，其具有第1面； (b)第1半導體晶片，其搭載於上述第1基板之上述第1面上，以使上述第1半導體晶片之第1背面與上述第1基板之上述第1面對向， 上述第1半導體晶片具有與上述第1背面為相反側之第1主面、形成於上述第1主面之第1主面焊墊、及形成於上述第1主面焊墊上之第1導電性構件； (c)第2半導體晶片，其搭載於上述第1半導體晶片之上述第1主面上，以使上述第2半導體晶片之第2背面與上述第1半導體晶片之上述第1主面對向，經由上述第1導電性構件而電性連接上述第1半導體晶片之上述第1主面焊墊與上述第2半導體晶片之第2背面焊墊， 上述第2半導體晶片具有與上述第2背面為相反側之第2主面、形成於上述第2主面上之第2主面焊墊、及形成於上述第2主面焊墊上之第2導電性構件， 上述第2背面焊墊形成於上述第2背面且與上述第2主面焊墊電性連接， 於俯視時，上述第2半導體晶片之外形尺寸小於上述第1半導體晶片之外形尺寸； (d)一體式(one-piece body)之密封材料，其密封上述第1半導體晶片、上述第2半導體晶片、及上述第2導電性構件； (e)基底基板，其直接搭載於上述密封材料，以使上述基底基板之第3面與上述第1基板之上述第1面對向，電性連接形成於上述基底基板之上述第3面之接合導線與上述第2半導體晶片之上述第2導電性構件， 上述基底基板之第4面與上述第3面為相反側， 突起焊點形成於上述第4面且與上述接合導線電性連接；及 (f)外部端子，其形成於上述突起焊點。
  2. 如請求項1之半導體裝置，其中上述密封材料係非導電薄膜(NCF，Non Conductive Film)或非導電膏(NCP，Non Conductive Paste)。
  3. 如請求項1之半導體裝置，其中上述密封材料包含熱硬化性樹脂。
  4. 如請求項1之半導體裝置，其中上述第1基板與上述第2基板之間的間隙填充有上述密封材料。
  5. 如請求項1之半導體裝置，其中上述第2半導體晶片之上述第2背面焊墊係經由形成於上述第2半導體晶片內之貫通電極而與上述第2主面焊墊電性連接。
  6. 如請求項1之半導體裝置，其中上述第1半導體晶片係形成有記憶體電路之記憶體晶片，上述第2半導體晶片係形成有控制上述第1半導體晶片的上述記憶體電路之控制電路之微晶片。
  7. 如請求項6之半導體裝置，其中上述第1半導體晶片之上述記憶體電路係DRAM電路。
  8. 如請求項1之半導體裝置，其中 配線形成於上述第1基板之上述第1面上； 貫通電極形成於上述密封材料中，且通過上述貫通電極而使形成於上述第1基板上之上述配線與形成於上述基底基板上之上述接合導線電性連接。
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