CN103681516B - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN103681516B
CN103681516B CN201310314424.0A CN201310314424A CN103681516B CN 103681516 B CN103681516 B CN 103681516B CN 201310314424 A CN201310314424 A CN 201310314424A CN 103681516 B CN103681516 B CN 103681516B
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chip
semiconductor chip
main surface
substrate
semiconductor
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CN103681516A (zh
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杉山道昭
木下顺弘
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

通过在衬底的顶表面之上装配包括具有小直径的半导体芯片和具有大直径的半导体芯片的芯片层压制件形成的半导体装置中，防止过度的压力施加至这两个半导体芯片的接合点。通过在支撑衬底之上装配具有大直径的第一半导体芯片，然后在所述第一半导体芯片之上装配具有小直径的第二半导体芯片，可以：抑制装配在所述第一半导体芯片之上的第二半导体芯片的倾斜和不稳定；从而阻止过度的压力施加至所述第一半导体芯片和第二半导体芯片的接合点。

Description

制造半导体装置的方法
相关申请的交叉引用
在此通过引用并入2012年8月31日提交的日本专利申请第2012-190993号的全部公布内容，包括说明书、附图和摘要。
技术领域
本发明涉及一种制造半导体装置的方法和一种可有效地应用到例如通过在衬底的顶表面之上装配芯片层压制件形成半导体装置的制造技术，所述芯片层压制件包括小直径半导体芯片和大直径半导体芯片。
背景技术
专利文献1公开了通过在配线衬底的顶表面之上装配控制器芯片和在该控制器芯片的顶表面之上层压存储器芯片形成的SIP（System In Package，系统级封装）型半导体装置。使用倒装（正面朝下）焊接法通过凸点（突起）电极将控制存储器芯片的控制器芯片装配在配线衬底的顶表面之上，在配线衬底和控制器芯片之间的间隙填充粘合剂。同时，使用正面朝上焊接法通过粘合剂将存储器芯片装配在控制器芯片的顶表面之上，存储器芯片的电极焊盘（焊盘）通过电线与配线衬底的电极焊盘（焊接引线）电连接。
专利文献2和3公开了一种通过在相对布置的金属衬底和配线衬底之间装配多个半导体芯片（芯片层压制件）来形成的COC（Chip On Chip，叠层芯片）型半导体装置。配置所述芯片层压制件的半导体芯片：包括多个存储器芯片和控制所述存储器芯片的接口芯片；并且通过穿透所述半导体芯片形成的通孔和在所述通孔的两端形成的凸点电极彼此电连接。在所述芯片层压制件中，具有比存储器芯片小的面积的接口芯片布置在最靠近配线衬底的位置，并且接口芯片的凸点电极通过布线凸痕与配线衬底的电极焊盘电连接。
【在先技术文献】
【专利文献】
专利文献1日本未审查专利公开文献2005-191053
专利文献2日本未审查专利公开文献2011-187574
专利文献3日本未审查专利公开文献2010-251408
发明内容
当生产专利文献2和3公开的这样的芯片层压制件结构时，如果意图首先在衬底（布线衬底）的顶表面之上装配第一半导体芯片并且然后在所述第一半导体芯片之上层压具有比所述第一半导体芯片大的直径的第二半导体芯片，所产生的问题是组装困难，包括第二半导体芯片向下面的第一半导体芯片倾斜。
根据本说明书的描述和附图，其他问题和新颖特征会显而易见。
用于解决本申请披露的问题的手段的代表性要点简要阐述如下。
根据本申请的一种实施方式的制造半导体装置的方法，包括下述步骤：
（a）在支撑衬底之上装配第一半导体芯片，第一半导体芯片具有第一主表面、在所述第一主表面上形成的第一主表面焊盘、和在所述第一主表面焊盘之上形成的第一导电部件，以使与所述第一主表面相反的第一背表面面向所述支撑衬底；
（b）在所述步骤（a）之后，将第二半导体芯片装配在所述第一半导体芯片的第一主表面之上以使第二背表面面向所述第一半导体芯片的第一主表面，并且通过所述第一导电部件将所述第一半导体芯片的第一主表面焊盘与所述第二半导体芯片的第二背表面焊盘电连接，所述第二半导体芯片具有第二主表面、在所述第二主表面之上形成的第二主表面焊盘、在所述第二主表面焊盘之上形成的第二导电部件、以及在与所述第二主表面相反的所述第二背表面上形成并且与所述第二主表面焊盘电连接的第二背表面焊盘，且第二半导体芯片具有比所述第一半导体芯片的外形尺寸小的外形尺寸；
（c）在所述步骤（b）之后，使用密封材料密封所述第一半导体芯片、所述第二半导体芯片、以及第二导电部件，以便所述第二导电部件不从所述密封材料中暴露；
（d）在所述步骤（c）之后，使用密封材料固定基部衬底，基部衬底具有第三表面、在所述第三表面之上形成的多个焊接引线、以及在与所述第三表面相对的第四表面之上形成的多个隆起连接盘，以使所述第三表面面向所述支撑衬底，并且将所述基部衬底的焊接引线与所述第二半导体芯片的第二导电部件电连接；以及
（e）在所述步骤（d）之后，在所述基部衬底的所述多个隆起连接盘的每个隆起连接盘处布置外部端子。
通过本申请公开的本发明获得的代表性效果简要阐述如下。
通过在支撑衬底之上装配第一半导体芯片之后在所述第一半导体芯片之上装配具有比第一半导体芯片小的外形尺寸的第二半导体芯片，可以：抑制装配在所述第一半导体芯片之上的所述第二半导体芯片的倾斜和不稳定；从而阻止过度的压力施加至所述第一半导体芯片和所述第二半导体芯片的接合处。
附图说明
图1是根据实施方式1的半导体装置的顶表面侧的平面图。
图2是根据实施方式1的半导体装置的背表面侧的平面图。
图3是沿图1中线A-A截取的截面图。
图4是微型计算机芯片的主表面侧的平面图。
图5是微型计算机芯片的背表面侧的平面图。
图6是微型计算机芯片的部分扩大截面图。
图7是存储器芯片的主表面侧的平面图。
图8是存储器芯片的部分扩大截面图。
图9A是显示根据实施方式1用于制造半导体装置的大型衬底的芯片装配表面的俯视图，并且图9是所述大型衬底的截面图。
图10是根据实施方式1的用于制造半导体装置的半导体晶片的平面图。
图11是显示根据实施方式1的制造半导体装置的方法的平面图。
图12是显示根据实施方式1的制造半导体装置的方法的部分扩大截面图。
图13是显示接着图11的制造半导体装置的方法的平面图。
图14是显示接着图12的制造半导体装置的方法的部分扩大截面图。
图15是显示接着图13的制造半导体装置的方法的平面图。
图16是显示接着图14的制造半导体装置的方法的部分扩大截面图。
图17是根据实施方式1用于制造半导体装置的半导体晶片的平面图。
图18是显示接着图16的制造半导体装置的方法的部分扩大截面图。
图19是根据实施方式1的用于制造半导体装置的大型配线衬底的芯片装配表面的平面图。
图20是根据实施方式1的用于制造半导体装置的大型配线衬底的装配表面的平面图。
图21是显示接着图18的制造半导体装置的方法的部分扩大截面图。
图22是显示接着图16的制造半导体装置的方法的另一实施例的部分扩大截面图。
图23是显示接着图18的制造半导体装置的方法的另一实施例的平面图。
图24是显示接着图18的制造半导体装置的方法的另一实施例的平面图。
图25是显示接着图21的制造半导体装置的方法的部分扩大截面图。
图26是显示根据实施方式1的半导体装置的修改实施例的截面图。
图27是显示根据实施方式2的制造半导体装置的方法的部分扩展截面图。
图28是显示接着图27的制造半导体装置的方法的部分扩大截面图。
图29是显示接着图28的制造半导体装置的方法的部分扩大截面图。
图30是显示接着图29的制造半导体装置的方法的部分扩大截面图。
图31是显示接着图30的制造半导体装置的方法的部分扩大截面图。
图32是显示接着图31的制造半导体装置的方法的部分扩大截面图。
图33是显示接着图32的制造半导体装置的方法的部分扩大截面图。
图33是显示接着图32的制造半导体装置的方法的部分扩大截面图。
图34是显示接着图33的制造半导体装置的方法的部分扩大截面图。
图35是显示接着图34的制造半导体装置的方法的部分扩大截面图。
图36是显示接着图35的制造半导体装置的方法的部分扩大截面图。
图37是显示接着图36的制造半导体装置的方法的部分扩大截面图。
图38是显示根据实施方式2的半导体装置的截面图。
图39是显示根据实施方式2的半导体装置的修改实施例的截面图。
具体实施方式
根据本发明的实施方式在下面参考附图进行具体阐述。在此，在用于阐述实施方式的所有附图中，具有相同功能的部件使用相同的附图标记标识，并且不重复阐述。而且，在这些实施方式中，相同或相似的部分原则上不重复阐述，除非特别需要。而且，在用于阐述实施方式的附图中，为了使配置易于理解，阴影线有时候甚至可应用在平面图中，或者甚至在截面图中可省略。
（实施方式1）
<半导体装置>
图1是根据实施方式1的半导体装置的顶表面侧的平面图。图2是该半导体装置的背表面侧的平面图。图3是沿图1的线A-A截取的截面图。
根据实施方式1的半导体装置10是SIP（系统级封装）型半导体装置，所述半导体装置是通过在基部衬底（基材）11之上装配包括两个半导体芯片（微型计算机芯片12和存储器芯片13）的芯片层压制件来形成的。
基部衬底11是所谓的双层配线衬底，例如具有通过将合成树脂（例如，环氧树脂）浸渍到玻璃纤维或碳素纤维形成的绝缘部件和在所述绝缘部件的两个表面之上形成的两个布线层。例如，基部衬底11的平面形状为四角形，其外形尺寸为长14mm、宽14mm、厚0.22mm。
所述两个布线层包括在基部衬底11的芯片装配表面（图3中基部衬底11的顶表面）之上形成的多个焊接引线（电极焊盘）14和在基部衬底11的背表面（装配表面）之上形成的多个隆起连接盘（电极焊盘）15。例如，焊接引线14和隆起连接盘15包括铜（Cu）膜和在铜膜的表面之上形成的镀膜。例如，所述镀膜包括含有锡（Sn）作为主要成分的金属膜。所述主要成分是指配置金属膜的主要材料，并且包括在该金属膜的内部含有细杂质和另外的金属材料的情形。
而且，焊接引线14的每一个通过在基部衬底11的内部（绝缘部件）内形成的通孔配线16与隆起连接盘15的每一个电连接。而且，基部衬底11的芯片装配表面和背表面除了形成电极焊盘（焊接引线14和隆起连接盘15）的区域之外覆盖有阻焊膜（绝缘膜）17。
微型计算机芯片12装配在基部衬底11的芯片装配表面之上。微型计算机芯片12装配在基部衬底11的芯片装配表面之上使得该微型计算机芯片的主表面可以与基部衬底11相对。
图4是微型计算机芯片12的主表面侧的平面图。图5是微型计算机芯片12的背表面侧的平面图。图6是微型计算机芯片12的部分扩大截面图。
例如，微型计算机芯片12的平面形状为四角形，微型计算机芯片12的外形尺寸为长6mm、宽6mm、厚50μm。例如，如图6所示，微型计算机芯片12具有p型硅衬底30。而且，在硅衬底30的主表面之上形成配置逻辑电路的电路元件（第二半导体元件）的多个n沟道型MOS晶体管（Qn）。这就是说，根据本实施方式的微型计算机芯片12为控制存储器芯片13的半导体芯片。本文，在硅衬底30的主表面之上还形成配置逻辑电路的其他电路元件（半导体元件）（例如，p沟道型MOS晶体管），但省略了这些电路元件的图。
在电路元件的上部形成将电路元件与另外的电路元件连接的多层配线31。配线31包括例如铜（Cu）或铝（Al）的金属膜。而且，在电路元件和配线31之间以及在下层的配线31和上层的配线31之间形成包括氧化硅膜的多层的夹层绝缘膜32。而且，在夹层绝缘膜32中形成将电路元件与配线31以及下层的配线31和上层的配线31电连接的多个接触层33。
在微型计算机芯片12的主表面之上的最上层形成保护逻辑电路的表面保护膜（钝化膜）34。表面保护膜34由例如通过层压氧化硅膜和氮化硅膜形成的绝缘膜组成。而且，通过表面保护膜34的开口部分和配线31的暴露部分形成的多个主表面焊盘（电极焊盘）35形成在微型计算机芯片12的最上层。
柱状的凸点电极36形成在各个主表面焊盘35的表面之上。凸点电极36由金属膜组成，所述金属膜例如从较靠近主表面焊盘35的一侧按顺序层压铜（Cu）膜和包括锡（Sn）-银（Ag）合金的焊料膜形成。
在微型计算机芯片12的主表面之上形成的主表面焊盘35和在主表面焊盘35之上形成的凸点电极36沿微型计算机芯片12的四个侧边成一行布置，如图4所示。然后，微型计算机芯片12通过凸点电极36与基部衬底11的焊接引线14电连接，如图3所示。
如图6所示，在微型计算机芯片12的硅衬底30内形成从微型计算机芯片12的背表面到配线31的多个通孔37。各个通孔37例如通过将铜（Cu）膜嵌入硅衬底30内的通孔开口内形成。而且，在微型计算机芯片12的背表面上形成分别与通孔37电连接的背表面焊盘38。各个背表面焊盘38例如由铜（Cu）膜和在铜膜表面上形成的镀膜组成。所述镀膜例如由含有锡（Sn）作为主要成分的金属膜组成。
这样，在微型计算机芯片12中形成的电路元件通过配线31、接触层33、和主表面焊盘35与微型计算机芯片12的主表面之上的凸点电极36电连接。而且，电路元件通过配线31、接触层33、和通孔37与微型计算机芯片12的背表面之上的背表面焊盘38电连接。
存储器芯片13装配在微型计算机芯片12的背表面之上，如图3所示。存储器芯片13装配在微型计算机芯片12的背表面之上使得存储器芯片13的主表面可以与微型计算机芯片12的背表面相对。
而且，在微型计算机芯片12的背表面和存储器芯片13的主表面之间的间隙填充粘合剂47。在实施方式1中，作为粘合剂47，使用的是NCF（Non Conductive Film，非导电膜）（是一种热固性树脂膜）或NCP（Non Conductive Paste，非导电胶）（是一种热固性树脂胶）。
此处，NCF：由一般社团法人日本半导体制造装置协会（Semiconductor EquipmentAssociation of Japan，SEAJ）规定；是具有用于固定（胶接）半导体芯片或粘合半导体芯片的电极表面（主表面）至衬底（配线衬底）的电路表面（芯片装配表面）的膜状的连接材料；并且不仅具有底层填料的功能还同时具有粘合/绝缘的功能。
NCP，与NCF类似，是用于固定（胶接）半导体芯片的连接材料，且不仅具有底层填料的功能还同时具有粘合/绝缘的功能。然而NCF是事先加工成膜状的材料，NCP是膏状材料，是在注射进入半导体芯片和衬底等之间的间隙之后通过加热固化的材料。NCP的优势在于流动性比NCF的流动性高，因而即使窄的间隙也可以容易地填充。
图7是存储器芯片13的主表面侧的平面图。图8是存储器芯片13的部分扩大截面图。
存储器芯片13的平面形状为四角形且存储器芯片13的外形尺寸为例如长9.2mm、宽8.6mm、厚260μm。这就是说，装配在微型计算机芯片12的背表面之上的存储器芯片13的外形尺寸比微型计算机芯片12的外形尺寸（长6mm且宽6mm）大。
存储器芯片13具有p型硅衬底40，例如如图8所示。DRAM（Dynamic Random AccessMemories，动态随机存取存储器）（是半导体存储器的一个种类）的存储单元（MC）形成在硅衬底40的主表面之上。各个DRAM存储器单元（MC）包括存储单元选择MOS晶体管（Qs）和与该存储单元选择MOS晶体管（Qs）串联连接的信息存储电容元件（C）。本文中，在硅衬底40的主表面之上还形成配置DRAM电路（存储单元阵列和外围电路）的其他电路元件（半导体元件），但省略这些电路元件的图。而且，尽管在本实施方式中基于具有DRAM电路的存储器芯片13作了说明，但在存储器芯片13之上形成的电路还可以是闪存电路或其他存储器电路。
将电路元件与其他电路元件连接的多层配线41形成在电路元件的上部。而且，在所述电路元件与配线41之间和下层的配线41与上层的配线41之间形成多层的夹层绝缘膜42。而且，在夹层的绝缘膜42中形成将电路元件与配线41电连接和将下层的配线41电连接至上层的配线41的多个接触层43。
保护DRAM电路的表面保护膜（钝化膜）44形成在存储器芯片13的主表面之上的最上层。而且，在存储器芯片13的最上层处形成通过表面保护膜44的开口部分和配线41的暴露部分形成的多个主表面焊盘（电极焊盘）45。
球（球体）状的凸点电极46形成在各个主表焊盘45的表面之上。各个凸点电极46由金属膜组成，所述金属膜例如通过从较靠近主表面焊盘45的一侧按顺序层压铜（Cu）膜、镍（Ni）膜、和包括锡（Sn）-银（Ag）合金的焊料膜形成。
在存储器芯片13的主表面之上形成的主表面焊盘45和在存储器芯片13的表面之上形成的凸点电极46布置在存储器芯片13的短边（图7中沿Y方向的边）的中心部分并且沿长边（图7中沿X方向的边）形成，如图7所示。然后存储器芯片13通过凸点电极46与微型计算机芯片12的背表面焊盘38电连接，如图3所示。
尽管图是简化的，但在存储器芯片13的主表面之上形成的主表面焊盘45的数目为约1200，并且所述主表面焊盘45被布置以形成例如沿Y方向4行、每行包括沿存储器芯片13的长边（X方向）约300个的布局。然后彼此相邻的主表面焊盘45之间的距离在存储器芯片13的短边方向（Y方向）为40μm、在长边方向（X方向）为50μm。这就是说，存储器芯片13具有比普通DRAM芯片多的输入-输出引脚（主表面焊盘45），从而通过扩展总线宽度来提高数据传输速率。因此，通过凸点电极46与存储器芯片13的主表面焊盘45电连接的微型计算机芯片12的背表面焊盘38的数目也为约1200。
如图3所示，存储器芯片13的背表面通过粘合剂48固定至副衬底（支撑衬底）50的芯片装配表面（图3中副衬底50的背表面）。副衬底50例如由平坦的合成树脂板组成，且副衬底50的外形尺寸与基部衬底11的外形尺寸（例如，长14mm且宽14mm）相同。而且，粘合剂48是例如被称为晶片贴膜（DAF）且具有粘晶和切割胶带的功能的膜状粘合剂。
副衬底50是支撑存储器芯片13的衬底，因而没有配线层形成。本文，副衬底50可包括除了合成树脂板之外的材料，例如玻璃板、陶瓷板或金属板。
使用应用于副衬底50和基部衬底11之间的间隙的密封材料49将在副衬底50和基部衬底11之间插入的两个半导体芯片（半导体芯片12和存储器芯片13）气密密封。
在实施方式1中，上述NCF用作密封材料49。而且，也可以使用NCP取代NCF。然而，考虑到粘住基部衬底11，在密封材料49的情形下，优选使用很可能获得比膏状密封材料更好平坦度的膜状密封材料。
同时，配置半导体装置10的外部端子的焊料球（焊料）18连接至基部衬底11的背表面（装配表面）之上形成的各个隆起连接面15的表面。根据实施方式1的半导体装置10通过这些焊料球18装配在图中未示出的装配衬底（母插件板）上。这就是说，半导体装置10的基部衬底11充当内插基板将装配在基部衬底11的芯片装配表面之上的两个半导体芯片（微型计算机芯片12和存储器芯片13）连接至装配衬底（母插件板）。
焊料球18由基本上不含有铅（Pb）的无铅焊料组成，例如仅含有锡（Sn）、锡-铋（Sn-Bi）合金、或锡-铜-银（Sn-Cu-Ag）合金。
这样，根据实施方式1的半导体装置10通过微型计算机芯片12的主表面焊盘35之上形成的凸点电极36将微型计算机芯片12与基部衬底11电连接，并且通过存储器芯片13的主表面焊盘45之上形成的凸点电极46将存储器芯片13与微型计算机芯片12电连接。因此，可以使穿过微型计算机芯片12电连接基部衬底11与存储器芯片13的数据传输路径的长度最小化，从而可以提高数据传输速率。
同时，本申请发明人还研究了通过在基部衬底11之上装配由微型计算机芯片12和存储器芯片13组成的芯片层压制件形成的SIP型半导体装置（类似于根据实施方式1的半导体装置10）的制造方法。
一般而言，SIP型半导体装置的微型计算机芯片（控制存储器芯片的半导体芯片）具有外部接口电路和内部接口电路，其中，所述外部接口电路用于输入来自外部设备的信号和向外部设备输出信号，所述内部接口电路用于输入来自内部设备（此处为存储器芯片）的信号和向内部设备输出信号。因此，优选地采用下述配置：将微型计算机芯片布置在更靠近基部衬底（配线衬底）的一侧并且在微型计算机芯片之上层压存储器芯片，从而缩短连接基部衬底和芯片层压制件的数据传输路径的长度并且实现SIP型半导体装置的高速操作。
而且，通常在半导体芯片的制造步骤中，通过减小半导体芯片的外形尺寸和增加从半导体晶片上获取的芯片数目来尝试改善制造效率和降低制造成本。为了达到该目的，微型计算机芯片的外形尺寸趋于逐年减小。然而，在存储器芯片的情形下，外形尺寸趋于随着大容量需求的增长而逐年增加，而且超过长6mm和宽6mm的外形尺寸近年来也变得普遍。这就是说，微型计算机芯片的外形尺寸和存储器芯片的外形尺寸之间的差异正逐年扩大。
因而在SIP型半导体装置的制造步骤中，如果大直径的存储器芯片在小直径的微型计算机芯片装配在基部衬底（配线衬底）之上后层压在该微型计算机芯片之上，存储器芯片伸出微型计算机芯片的比例上升，并且很可能引起存储器芯片的倾斜和不稳定。结果，过度的压力被施加至微型计算机芯片和存储器芯片的接合点，从而使这两个芯片的接合点的可靠性退化，在存储器芯片的伸出部分产生破裂，从而使SIP型半导体装置的可靠性和制造产量退化。
鉴于上述情况，在实施方式1中，通过下述的方法制造SIP型半导体装置10。
<制造半导体装置的方法>
下面根据与附图有关的步骤顺序阐述制造根据实施方式1的半导体装置10的方法。
图9A是显示出用于制造根据实施方式1的半导体装置的大型衬底的芯片装配表面的平面图，图9B是该大型衬底的截面图。
首先，提供图9所示的大型衬底100。大型衬底100为平坦衬底，其平面形状为矩形，并且通过切割线DL1（图9A中使用双点划线示出）分为多个装置区域（本文为6个装置区域）。各个装置区域：是当大型衬底100沿装置区域的外边缘（切割线DL1）切割时变成半导体装置10的副衬底50的区域；并且具有与副衬底50相同的外形尺寸。
而且，通过切割（切断）图10中所示的半导体晶片20提供多个存储器芯片（第一半导体芯片）13，与提供大型衬底100的步骤并行。如图7和图8所示，配置DRAM电路的多个电路元件（第一半导体元件）和多个主表面焊盘（第一主表面焊盘）45形成在各个存储器芯片13的主表面（第一主表面）之上。而且，凸点电极（第一导电部件）46形成在各个主表面焊盘45的表面之上。
此处，在主表面焊盘45的表面之上形成的凸点电极46的形状不限于球（球体）状，而可以是柱状，例如与在微型计算机芯片12的主表面焊盘35的表面之上形成的凸点电极36类似。
当半导体晶片20被切割时，粘合剂48（晶片贴膜，第一粘合剂）粘附至半导体晶片20的背表面侧，并且半导体晶片20和粘合剂48同时被切割。通过这样做，与存储器芯片13具有相同外部尺寸的粘合剂48保持在各单一化的存储器芯片13的背表面之上。因此，当存储器芯片13装配在大型衬底100之上时，向大型衬底100的装置区域提供粘合剂的步骤变得不是必须的。
2.芯片焊接步骤
继续地，如图11（大型衬底100的平面图）和图12（显示大型衬底100的一个装置区域的截面图）所示，存储器芯片13装配在大型衬底100的各个装置区域之上。存储器芯片13通过所谓的正面朝上装配方法进行装配，所述面朝上安装方法为：使存储器芯片13的背表面（粘合剂48粘附的表面，第一背表面）与大型衬底100的芯片装配表面（第一表面）相对。这就是说，在存储器芯片13的背表面通过粘合剂48粘附至大型衬底100的芯片装配表面之后，大型衬底100被加热，粘合剂48被固化，进而使存储器芯片固定至大型衬底100的芯片装配表面。大型衬底100的装置区域和存储器芯片13的位置调整例如通过利用形成在大型衬底100的装置区域内的基准标记22来执行。
本文，存储器芯片13的芯片焊接不限于使用晶片贴膜（粘合剂48）的方法，还可以例如通过向大型衬底100的装置区域提供膏状粘合剂的方法来执行。膏状粘合剂的优势在于比晶片贴膜便宜。
接下来如图13和图14所示，膜状粘合剂（第二粘合剂）47装配在存储器芯片13的主表面之上。粘合剂47是上述的NCF，并且粘合剂47的外形尺寸比存储器芯片13的外形尺寸小并且比在下一个步骤中装配在存储器芯片13的主表面之上的微型计算机芯片12的外形尺寸大。此处，粘合剂47还可以包括前述的NCP。
在存储器芯片13的主表面之上装配NCF这样的膜状粘合剂47的情形下，优选地采用真空层压方法。通过这样做，可以防止存储器芯片13的主表面（在该表面上形成凸点电极46）和粘合剂47之间形成间隙。
接下来如图15和图16所示，微型计算机芯片12装配在存储器芯片13的主表面之上。如图4和图6所示，配置逻辑电路的多个电路元件（第二半导体元件）和多个主表面焊盘（第二主表面焊盘）35形成在微型计算机芯片12的主表面（第二主表面）之上。而且，凸点电极（第二导电部件）36形成在各个主表面焊盘35的表面之上。而且，如图5和图6所示，分别与硅衬底30内形成的多个通孔37电连接的多个背表面焊盘38形成在微型计算机芯片12的背表面（第二背表面）之上。
本文，在主表面焊盘35的表面之上形成的凸点电极36的形状不限于柱状，还可以是球（球体）状，例如与存储器芯片13的主表面焊盘45的表面之上形成的凸点电极46类似。此外，微型计算机芯片12的凸点电极36和存储器芯片13的凸点电极46可以由金（Au）的突出电极构成。
与提供大型衬底100的步骤并行，以与提供存储器芯片13相同的方式提供微型计算机芯片12。这就是说，通过切割（切断）半导体晶片21提供多个微型计算机芯片（第二半导体芯片）12，如图17所示。
当半导体晶片21被切割时，切割膜23附着在半导体晶片21的背表面，并且仅切割半导体晶片21。通过这样做，单一化的微型计算机芯片12还处于附着至切割膜23的状态，从而可以将微型计算机芯片12整体地输送至焊接步骤。
当微型计算机芯片12装配在存储器芯片13的主表面之上时，在附着至切割膜23的微型计算机芯片12被拾起并布置在存储器芯片13的上方之后，微型计算机芯片12的背表面与存储器芯片13的主表面相对。接着，通过将微型计算机芯片12按压至存储器芯片13的主表面之上的粘合剂47上，微型计算机12的背表面焊盘38与存储器芯片13的凸点电极46电连接。然后，通过在此状态下加热和固化粘合剂47，微型计算机芯片12固定至存储器芯片13并且所述两个芯片的接合点（微型计算机芯片12的背表面焊盘38和存储器芯片13的主表面焊盘45和凸点电极46）使用粘合剂47密封。
3.密封和衬底粘贴步骤
接下来如图18所示，膜状密封材料49装配在大型衬底100的芯片装配表面之上。密封材料49是上述的NCF。密封材料49是密封存储器芯片13和微型计算机芯片12的部件并且具有厚的膜厚度以便微型计算机芯片12的主表面之上形成的凸点电极36不被暴露。而且，密封材料49具有与大型衬底100的外形尺寸相同的外形尺寸，并且装配密封材料49以覆盖大型衬底100的整个芯片装配表面。
在大型衬底100的芯片装配表面之上装配NCF这样的膜状密封材料49的情形下，优选地采用真空层压方法。通过这样做，可以防止在存储器芯片13和粘合剂47之间或在微型计算机芯片12和粘合剂47之间形成间隙。
接着，提供如图19和图20所示的大型配线衬底200。图19是显示大型配线衬底200的芯片装配表面的平面图。图20是示出大型配线衬底的装配表面的平面图。
大型配线衬底200是平面形状为矩形并且具有与大型衬底100相同的外形尺寸的配线衬底。而且，大型配线衬底200通过图19和图20中使用双点划线所示的切割线DL2划分为多个（此处6个）装置区域。各个装置区域：是当大型配线衬底200沿装置区域的外部边缘（切割线DL2）切割时变成上述的半导体装置10的基部衬底11的区域；并且具有与基部衬底11相同的结构和外形尺寸。多个焊接引线14形成在大型配线衬底200的芯片装配表面（第三表面）之上的各个装置区域内，并且多个隆起连接盘15形成在装配表面（第四表面）之上的各个装置区域内。
接着，如图21所示（显示大型配线衬底200的一个装置区域的截面图），通过将大型配线衬底200的芯片装配表面与大型衬底100相对并且向下按压大型配线衬底200（沿大型衬底100的芯片装配表面的方向），大型配线衬底200的焊接引线14与微型计算机芯片12的凸点电极36电连接。然后，在此状态下加热和固化密封材料49。通过这样做，由微型计算机芯片12和存储器芯片13组成的芯片层压制件固定在大型配线衬底200和大型衬底100之间并且使用密封材料49气密密封。
本文，尽管在上述的方法中在密封材料49装配在大型衬底100的芯片装配表面之上后大型配线衬底200和大型衬底100进行层压，但还可以在事先将密封材料49附着在大型配线衬底200的芯片装配表面后层压大型配线衬底200和大型衬底100，如图22所示。
而且，尽管在上述制造方法中层压具有相同外形尺寸的大型配线衬底200和大型衬底100（图21），但大型配线衬底200的外形尺寸可以比大型衬底100的外形尺寸小。
这就是说，还可以将与大型衬底100具有相同外部尺寸的大型配线衬底200事先切割为多个块，而后将所述切割后的大型配线衬底200的各个块层压至大型衬底100，如图23所示。而且，还可以事先将大型配线衬底200切割为装置区域而后逐个将所述切割后的大型配线衬底200层压至大型衬底100的各装置区域，如图24所示。这些方法在下述情形下可有效地适用：由于大型衬底100或大型配线衬底200的翘曲等，相对于大型配线衬底200的装置区域，大型衬底100的装置区域难以精确调整。
4.球装配步骤
接着，如图25所示，焊料球18连接至在大型配线衬底200的装配表面之上形成的各隆起连接盘15的表面。为了将焊料球18连接至各隆起连接盘15的表面，焊料球18暂时固定至事先涂覆有焊剂的各隆起连接盘15的表面，然后加热并回流。
5.切割步骤
接着，通过沿着各自装置区域的外部边缘（切割线DL1和DL2）切割大型衬底100和大型配线衬底200完成根据图1至图3所示实施方式1的半导体装置10。
在这种方法中，在实施方式1中，当制造通过在基部衬底11之上装配由微型计算机芯片12和存储器芯片13组成的芯片层压制件形成的SIP型半导体装置10时，首先将具有大外形尺寸的存储器芯片13装配在大型衬底100（副衬底50）之上。接着，具有比存储器芯片13小的外形尺寸的微型计算机芯片12在存储器芯片13之上层压并且将存储器芯片13与微型计算机芯片12电连接。然后最终，大型配线衬底200（基部衬底11）在微型计算机芯片12之上层压并且从而使微型计算机芯片12与大型配线衬底200（基部衬底11）电连接。
通过上述制造方法，通过在具有大外形尺寸的存储器芯片13之上层压具有小外形尺寸的微型计算机芯片12可以抑制上层的微型计算机芯片12的倾斜和不稳定。通过这样做，对微型计算机芯片12和存储器芯片13的接合点未施加过度的压力，从而可以：抑制微型计算机芯片12和存储器芯片13的接合点的可靠性的退化和芯片破裂的发生；改善SIP型半导体装置10的可靠性和制造产量。
<实施方式1的修改实施例>
尽管在上述实施方式1中没有在副衬底50（大型衬底100）之上形成配线层，但还可以在配置副衬底50（大型衬底100）的绝缘部件的两个表面（芯片装配表面和背表面）之上形成配线51，例如图26所示。
在这种情形下，还可以在通过下述方法在副衬底50之上装配电子元件：预先在基部衬底11的芯片装配表面之上形成配线19并且通过如图所示的在粘贴步骤之前形成于密封材料49内的通孔（导电部件）52将副衬底50的配线51与基部衬底11的配线19电连接，从而可以改善半导体装置10的装配密度。
在这种情形下，进一步地，作为副衬底50的绝缘部件，可以使用除了合成树脂之外的材料，例如玻璃或陶瓷。通过这样做，与使用由合成树脂组成的绝缘部件的情形相比，可以减小副衬底50的厚度。
（实施方式2）
在根据实施方式1的制造方法中，在存储器芯片13和微型计算机芯片12装配在大型衬底100的芯片装配表面之上后，大型衬底100和大型配线衬底200层压在一起。另一方面，在根据实施方式2的制造方法中，在存储器芯片13和微型计算机芯片12装配在大型衬底100的芯片装配表面之上后，基部衬底（大型配线衬底）形成在微型计算机芯片12的主表面之上。
首先如图27（显示大型衬底100的一个装置区域的截面图）所示，存储器芯片13通过粘合剂48（例如根据实施方式1的制造方法的晶片贴膜）装配在大型衬底100的各装置区域内。此处，黑色阻焊剂（绝缘层）63形成在实施方式2中所使用的大型衬底100的两个表面（芯片装配表面和背表面）之上，目的是为保护大型衬底100之上装配的存储器芯片13和遮挡光（防止由于光进入芯片而导致的存储单元的软错误）。
接着，如图28所示，膜状粘合剂47（例如上述NCF）装配在存储器芯片13的主表面之上。尽管在实施方式1中具有比存储器芯片13小的外形尺寸的粘合剂47装配在存储芯片13的主表面之上（图13和图14），但在实施方式2中使用具有与大型衬底100相同外形尺寸的粘合剂47并且将粘合剂47粘附至大型衬底100的整个芯片装配表面。
接着，如图29所示，在微型计算机芯片12装配至存储器芯片13的主表面且微型计算机芯片12的背表面焊盘38与存储器芯片13的凸点电极46电连接后，粘合剂47被加热并固化。微型计算机芯片12从而固定至存储器芯片13并且所述两个芯片的接合点（微型计算机芯片12的背表面焊盘38和存储器芯片13的主表面焊盘45和凸点电极46）使用粘合剂47密封。此处，粘合剂47还可以是膏状粘合剂材料，例如NCP。
尽管在实施方式1中使用具有在主表面焊盘35的表面之上形成的凸点电极36的微型计算机芯片12，但在实施方式2中使用不具有在主表面焊盘35的表面之上形成的凸点电极（第二导电部件）36的微型计算机芯片12。
接着，如图30所示，绝缘膜60通过例如真空层压方法附着在微型计算机芯片12的主表面和粘合剂47的表面之上。优选地，绝缘膜60由对随后的配线形成步骤中使用的电解电镀液具有高耐化学性并且对配线材料具有高粘合性的绝缘部件组成。这样的绝缘部件的例子为预浸料和ABF（Ajinomoto Build-up Film，是由Ajinomoto Fine-Techno Co.生产的产品的商品名称），所述预浸料和ABF用于制造多层的配线衬底，换而言之，用作用于配线衬底的绝缘部件。
接着，如图31所示，在微型计算机芯片的主表面之上形成的主表面焊盘35的上方的绝缘膜60上形成多个开口61，所述主表面焊盘35在开口61的底部暴露。例如，通过使用激光束照射主表面焊盘35上方的绝缘膜60形成所述开口61。
接着，如图32所示，由铜（Cu）等组成的配线62形成在绝缘膜60的表面之上和开口61内，配线62与形成在微型计算机芯片12的主表面之上的主表面焊盘35电连接。
配线62通过下述步骤形成。首先，通过非电解电镀或溅射方法在开口61内和绝缘膜60的表面之上形成由薄铜（Cu）膜组成的籽晶层。接着，在通过电解电镀方法在籽晶层的表面之上形成厚铜（Cu）膜之后，通过使用光敏抗蚀膜作为掩膜进行蚀刻使所述两层铜（Cu）膜形成图案。
接着，如图33所示，在第二分层绝缘膜64附着至绝缘膜60（配线62形成在绝缘膜60之上）的整个表面之后，例如使用激光束照射绝缘膜64来在配线62之上的绝缘膜64内形成通孔（开口）65，配线62在通孔65的底部暴露。
接着，如图34所示，在通孔65内和第二分层绝缘膜64的表面之上形成由铜（Cu）膜组成的第二分层配线66，随后第二分层配线66通过通孔65与第一分层配线62电连接。第二分层配线66可以通过与第一分层配线62相同的步骤形成。
接着，如图35所示，在保护配线66的阻焊剂（绝缘膜）67形成在绝缘膜64的表面之上后，通过蚀刻阻焊剂67并由此暴露第二分层配线66的部分形成多个隆起连接盘（电极焊盘）68。通过上述步骤，在微型计算机芯片12的主表面之上形成了具有两层配线62和66的基部衬底69。
接着，在基部衬底69的隆起连接盘68的表面之上形成由镍（Ni）膜和金（Au）膜组成的镀膜（图中未示出）之后，焊料球18连接至隆起连接盘68的表面，如图36所示。焊料球18通过与实施方式1中的焊料球18相同的方法进行连接。
接着，如图37所示，移走不再必需的大型衬底100。在这种情况下，阻焊剂63留在存储器芯片13的背表面之上以遮光和保护存储器芯片13。
接着，通过切割基部衬底69完成图38中所示的根据实施方式2的半导体装置70。本文，尽管在本例中基部衬底69是在不必要的大型衬底100移走之后进行切割，还可以在通过切割基部衬底69和大型衬底100将半导体装置70单一化之后将大型衬底100从存储器芯片13的背表面移走。
通过上述制造方法，可以通过在具有大外形尺寸的存储器芯片13之上层压具有小外形尺寸的微型计算机芯片12来抑制上层的微型计算机芯片12的倾斜和不稳定。通过这样做，不会对微型计算机芯片12和存储器芯片13的接合点施加过度的压力，从而可以：抑制微型计算机芯片12和存储器芯片13的接合点的可靠性的退化和芯片破裂的发生；并且改善SIP型半导体装置70的可靠性和制造产量。
而且，通过上述制造方法，在球装配步骤之后移走不再必需的大型衬底100，从而可以实现比实施方式1的半导体装置10薄的半导体装置70。
<实施方式2的修改实施例>
尽管在实施方式2中在球装配步骤之后移走大型衬底100，但与实施方式1类似，可保留大型衬底100。在这样的情况下，通过切割大型衬底100获得的副衬底（支撑衬底）71固定在存储器芯片13的背表面侧，如图39所示，从而可以改善半导体装置70的机械强度。此处在这种情形下，由于进入存储器芯片13的光由副衬底71遮挡，可以不在大型衬底100的表面之上形成黑色阻焊剂63。
进一步地，在此情况下，也可以通过以与实施方式1的修改实施例（图26）相同的方式在副衬底71之上形成配线来在副衬底71之上装配电子元件，从而可以提高半导体装置70的装配密度。
尽管由本申请发明人创建的本发明到此已经根据实施方式进行了具体的阐述，但本发明并不限于上述的实施方式，当然本发明可以在不脱离本发明的要旨的范围内进行各种不同的修改。
（修改的实施例1）
例如，尽管在实施方式1和2中采用通过在基部衬底的隆起连接盘（电极焊盘）的表面之上形成球（球体）状焊料（焊料球）获得的所谓BGA（Ball Grid Array,球面栅格阵列）结构作为半导体装置的外部端子，但还可以采用通过使用少量的焊料代替焊料球覆盖隆起连接盘的表面获得的所谓的LGA（Land Grid Array,平面栅格阵列）。
（修改的实施例2）
此外，尽管在实施方式1和2中将由DRAM组成的半导体芯片作为存储器芯片的例子，存储器芯片可以是由闪存或SRAM（静态随机存取器）组成的半导体芯片。
（修改的实施例3）
此外，尽管在实施方式1和2中将双层配线衬底作为基部衬底（大型配线衬底）的例子，所述基部层还可以是具有四层或更多层配线层的多层配线衬底。

Claims (10)

1.一种制造半导体装置的方法，包括如下步骤：
(a)提供具有第一表面的支撑衬底；
(b)在所述步骤(a)之后，将第一半导体芯片装配在所述支撑衬底的第一表面之上以便所述第一半导体芯片的第一背表面面向所述支撑衬底的第一表面，
其中所述第一半导体芯片具有第一主表面、第一半导体元件、在所述第一主表面上形成的并且与所述第一半导体元件电连接的第一主表面焊盘、以及在所述第一主表面焊盘之上形成的第一导电部件，以及
其中，所述第一背表面与所述第一主表面相反；
(c)在所述步骤(b)之后，将第二半导体芯片装配在所述第一半导体芯片的第一主表面之上以便所述第二半导体芯片的第二背表面面向所述第一半导体芯片的第一主表面，并且
通过所述第一导电部件将所述第一半导体芯片的第一主表面焊盘与所述第二半导体芯片的第二背表面焊盘电连接，
其中所述第二半导体芯片具有第二主表面、第二半导体元件、在所述第二主表面之上形成的并且与所述第二半导体元件电连接的第二主表面焊盘、以及在所述第二主表面焊盘之上形成的第二导电部件，
其中所述第二背表面与所述第二主表面相反，
其中所述第二背表面焊盘在所述第二背表面上形成且与所述第二主表面焊盘电连接，以及
其中，在平面视图中，所述第二半导体芯片的区域比所述第一半导体芯片的区域小；
(d)在所述步骤(c)之后，通过单次应用密封材料密封所述第一半导体芯片、所述第二半导体芯片、和所述第二导电部件，以便所述第二导电部件不从所述密封材料中暴露；
(e)在所述步骤(d)之后，在所述支撑衬底的第一表面之上布置基部衬底以便所述基部衬底的第三表面面向所述支撑衬底的第一表面，
将所述基部衬底直接安装至所述密封材料，以及将所述基部衬底的焊接引线与所述第二半导体芯片的第二导电部件电连接，
其中所述焊接引线形成在所述第三表面上，
其中所述基部衬底的第四表面与所述第三表面相反，以及
其中隆起连接盘在所述第四表面上形成并且与所述焊接引线电连接；以及
(f)在所述步骤(e)之后，在所述基部衬底的隆起连接盘上形成外部端子。
2.根据权利要求1所述的制造半导体装置的方法，其中所述密封材料为NCF。
3.根据权利要求1所述的制造半导体装置的方法，
其中所述密封材料包括热固性树脂，
其中所述步骤(d)在所述密封材料的固化反应未开始的温度执行，以及
其中所述步骤(e)在所述密封材料的固化反应开始的温度执行。
4.根据权利要求1所述的制造半导体装置的方法，其中，使用所述密封材料填充所述基部衬底和所述支撑衬底之间的间隙。
5.根据权利要求1所述的制造半导体装置的方法，其中所述步骤(c)包括使用粘合剂填充所述第一半导体芯片的第一主表面和所述第二半导体芯片的第二背表面之间的间隙的步骤。
6.根据权利要求5所述的制造半导体装置的方法，其中所述粘合剂为NCF或NCP。
7.根据权利要求1所述的制造半导体装置的方法，其中所述第二半导体芯片的第二背表面焊盘通过在所述第二半导体芯片内形成的通孔与所述第二主表面焊盘电连接。
8.根据权利要求1所述的制造半导体装置的方法，其中所述第一半导体芯片为形成有存储器电路的存储器芯片，所述第二半导体芯片为形成有控制所述第一半导体芯片的存储器电路的控制电路的微型计算机芯片。
9.根据权利要求8所述的制造半导体装置的方法，其中所述第一半导体芯片的存储器电路为DRAM电路。
10.根据权利要求1所述的制造半导体装置的方法，
其中，在所述步骤(a)中提供的所述支撑衬底的第一表面之上形成配线，以及
其中，在所述步骤(d)之后，在所述密封材料内形成通孔，在所述支撑衬底之上形成的所述配线通过所述通孔与所述基部衬底之上形成的焊接引线电连接。
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