WO2018126545A1 - 一种高可靠性电子封装结构、电路板及设备 - Google Patents

一种高可靠性电子封装结构、电路板及设备 Download PDF

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Publication number
WO2018126545A1
WO2018126545A1 PCT/CN2017/078888 CN2017078888W WO2018126545A1 WO 2018126545 A1 WO2018126545 A1 WO 2018126545A1 CN 2017078888 W CN2017078888 W CN 2017078888W WO 2018126545 A1 WO2018126545 A1 WO 2018126545A1
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Prior art keywords
encapsulation layer
layer
package
region
mechanical support
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PCT/CN2017/078888
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English (en)
French (fr)
Inventor
史洪宾
叶润清
龙浩晖
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to JP2018562580A priority Critical patent/JP6726309B2/ja
Priority to KR1020187032994A priority patent/KR102152041B1/ko
Priority to CN201780005368.9A priority patent/CN108541340A/zh
Priority to US16/339,195 priority patent/US11011477B2/en
Publication of WO2018126545A1 publication Critical patent/WO2018126545A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/32—Layered products comprising a layer of synthetic resin comprising polyolefins
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/08—Interconnection of layers by mechanical means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00—Layers arrangement
    • B32B2250/05—5 or more layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00—Layers arrangement
    • B32B2250/42—Alternating layers, e.g. ABAB(C), AABBAABB(C)
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
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    • B32B2250/44—Number of layers variable across the laminate
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/30—Properties of the layers or laminate having particular thermal properties
    • B32B2307/302—Conductive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
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    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/38—Layered products comprising a layer of synthetic resin comprising epoxy resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of electronic boards, and in particular to a high reliability electronic package structure, circuit board and device.
  • PoP package on package
  • IMC Intermetallic Compound
  • underfill materials are widely used to protect board level solder joints. Underfill distributes the mechanical and thermal stresses originally concentrated on the corner joints of the component to all solder joints relatively evenly, improving the overall reliability of the PoP.
  • the current board-level underfilll usually uses a low-viscosity underfill without a filler, which allows the PoP under the package layer and the printed circuit board (PCB).
  • PCB printed circuit board
  • Embodiments of the present invention relate to a high reliability electronic package structure, circuit board, and device.
  • the problem of failure of the silicon wafer inside the package layer on the PoP caused by partial filling of the encapsulation layer on the PoP is achieved by the package structure of the upper layer of the PoP and the package structure of the lower layer.
  • an embodiment of the present invention provides a high-reliability electronic package structure including: a plurality of package layers and a mechanical support layer; and a plurality of package layers in each of the plurality of package layers An area is provided with an electrical function solder joint, and any two adjacent encapsulation layers are connected by electrical function solder joints; a mechanical support layer is disposed in a second area of each encapsulation layer of the plurality of encapsulation layers, and the mechanical support layer is used to support adjacent Two encapsulation layers; wherein the first region is disposed at a periphery of the second region.
  • the mechanical support layer is disposed in the second region of any adjacent encapsulation layer of the multi-layer encapsulation layer, and the deformation variable when the multi-encapsulation layer is mechanically deformed is reduced, thereby solving the problem that the silicon wafer fracture in the encapsulation layer fails.
  • the mechanical support layer is disposed on the upper or lower surface of each of the encapsulation layers, which solves the problem of failure of the silicon wafer inside the encapsulation layer.
  • the mechanical support layer comprises a non-functional solder ball or a plastic seal.
  • the embodiment of the present invention provides a circuit board, wherein the circuit board includes a PCB board, an electronic component, and a mechanical support layer; and the PCB board passes through a pad and a setting disposed in the first area of the PCB board.
  • the electrical function solder joints of the first region of the electronic component are connected; the mechanical support layer is disposed at the second region of the electronic component; wherein the first region is disposed at a periphery of the second region.
  • the mechanical support layer is disposed in the second region of the electronic component, and the deformation variable when the multi-package layer is mechanically deformed is reduced, thereby solving the problem that the silicon wafer breaks in the package layer.
  • an embodiment of the present invention provides an apparatus including the high reliability electronic package structure described above.
  • the technical solution provided by the embodiment of the present invention can solve the problem that the internal silicon wafer of the encapsulation layer or the lower encapsulation layer on the PoP is subjected to mechanical load and fracture failure.
  • FIG. 2 is a schematic structural diagram of a first high reliability electronic package structure according to an embodiment of the present invention.
  • 3(a)-3(b) are schematic structural diagrams of a second high reliability electronic package structure according to an embodiment of the present invention.
  • 4(a)-4(b) are schematic structural diagrams of a third high reliability electronic package structure according to an embodiment of the present invention.
  • 5(a)-5(d) are schematic structural diagrams of a fourth high reliability electronic package structure according to an embodiment of the present invention.
  • 6(a)-6(d) are schematic structural diagrams of a fifth high reliability electronic package structure according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a high reliability electronic package structure according to an embodiment of the present invention.
  • the high reliability electronic package structure includes a plurality of encapsulation layers and support layers.
  • the plurality of encapsulation layers includes at least two encapsulation layers. Electrical function solder joints are disposed in a first region of each of the plurality of package layers, and any two adjacent package layers are connected by electrical function solder joints; and a second region of each of the plurality of package layers is disposed a mechanical support layer for supporting two adjacent encapsulation layers; wherein the first region is disposed at a periphery of the second region.
  • the encapsulation layer 210, the encapsulation layer 220, the encapsulation layer 230, the encapsulation layer 240, and the encapsulation layer 250, and four mechanical support layers are exemplified.
  • electrical function solder joints an encapsulation layer 210 and an encapsulation layer 220, an encapsulation layer 220 and an encapsulation layer 230, and a package are disposed in a first region of the encapsulation layer 210, the encapsulation layer 220, the encapsulation layer 230, the encapsulation layer 240, and the encapsulation layer 250.
  • the layer 230 and the encapsulation layer 240, the encapsulation layer 240 and the encapsulation layer 250 are all connected by electrical function solder joints; and the mechanical support is provided in the second region of the encapsulation layer 210, the encapsulation layer 220, the encapsulation layer 230, the encapsulation layer 240, and the encapsulation layer 250.
  • the first region is located on an upper surface or a lower surface of each of the plurality of encapsulation layers.
  • the encapsulation layer 210 and the encapsulation layer 220 are taken as an example for illustration. Specifically, a first region of the encapsulation layer 210 is disposed on a lower surface of the encapsulation layer 210, a first region of the encapsulation layer 220 is disposed on an upper surface of the encapsulation layer 220, a first region of the encapsulation layer 210, and a second region of the encapsulation layer 220 correspond.
  • the mechanical support layer comprises a non-electrical function solder joint or a plastic seal.
  • Non-electrical functional solder joints as opposed to electrical functional solder joints, are used to support any two encapsulation layers.
  • Non-electrical function solder joints can be Dummy ball or Epoxy Mold Compound (EMC).
  • each of the plurality of encapsulation layers has a regular shape.
  • each of the plurality of encapsulation layers has a square shape, and the first region is each of the plurality of encapsulation layers.
  • the second region is the central region of each of the plurality of encapsulation layers.
  • the high reliability electronic package structure includes two encapsulation layers, such as an encapsulation layer and a lower encapsulation layer.
  • a mechanical support layer is disposed on a lower surface of the upper encapsulation layer.
  • the mechanical support layer is a Dummy ball.
  • a Dummy ball is disposed in a first region of a lower surface of the upper encapsulation layer.
  • the deformation of the upper encapsulation layer under mechanical load is reduced, thereby solving the problem of silicon wafer fracture failure inside the upper encapsulation layer.
  • FIG. 3(a) is a bottom view of the upper encapsulation layer
  • FIG. 3(b) is a side view of the upper encapsulation layer.
  • the mechanical support is increased by adding a Dummy ball to the first region of the lower surface of the upper encapsulation layer, and the deformation of the upper encapsulation layer under mechanical load is reduced, thereby solving the failure of the silicon wafer in the upper encapsulation layer. problem.
  • the feasibility of the embodiment of the present invention is described in terms of a process.
  • the Dummy ball can be soldered to the substrate of the upper package layer simultaneously with the electrical function solder joints disposed in the first region of the upper package layer, without adding extra to the prior art.
  • the process step only needs to add a dummy pad at a position corresponding to the upper surface of the lower package layer.
  • the stress level of the upper encapsulation layer when the mechanical load is applied to the embodiment of the present invention and the prior art solution can be employed by finite element analysis. Assume that the finite element analysis has a load condition of 50N.
  • the following table is the stress (MPa) of the upper package when subjected to mechanical load according to an embodiment of the present invention and a prior art solution.
  • the stress of the upper portion of the upper package layer is improved by 74.6% compared with the prior art.
  • stress analysis when subjected to mechanical load, stress analysis may be performed on any region of the upper encapsulation layer, for example, stress analysis may be performed on the upper left corner of the upper encapsulation layer, because when the underfill layer is filled with underfill, There is also an underfill fill in the upper left corner of the encapsulation layer, so stress analysis can be performed on the upper left corner of the upper encapsulation layer.
  • the Dummy ball is added to the second region of the lower surface of the upper encapsulation layer, which can reduce the deformation of the upper encapsulation layer when subjected to mechanical load. If the upper encapsulation layer overflows, the stress near the edge of the overflow will be significantly improved, thereby solving the problem of failure of the silicon wafer inside the upper encapsulation layer.
  • the mechanical support layer is EMC, in order to distinguish from the EMC of the upper surface of the upper encapsulation layer,
  • the mechanical support layer is hereinafter referred to as Dummy EMC.
  • FIG. 4(a) is a bottom view of the upper encapsulation layer
  • FIG. 4(b) is a side view of the upper encapsulation layer.
  • Dummy EMC is disposed in the second region of the lower surface of the upper encapsulation layer.
  • the deformation of the upper encapsulation layer under mechanical load is reduced, thereby solving the problem of silicon wafer fracture failure inside the upper encapsulation layer.
  • the stress level of the upper encapsulation layer can be employed by the finite element analysis for the embodiment of the present invention and the prior art solution under the stress of the mechanical load. Assume that the finite element analysis has a load condition of 50N.
  • the following table is the stress (MPa) of the upper package when subjected to mechanical load according to an embodiment of the present invention and a prior art solution.
  • the upper surface stress of the upper encapsulation layer is improved by 96% compared with the prior art.
  • the deformation of the upper encapsulation layer when subjected to mechanical load can be reduced. If the upper encapsulation layer overflows, the stress near the edge of the overflow will be significantly improved, thereby solving the problem of failure of the silicon wafer inside the upper encapsulation layer.
  • the Dummy EMC's face support can significantly improve the stress on the upper encapsulation layer relative to the point support of the Dummy ball.
  • the Dummy EMC's surface support is compared to the Dummy ball's point support, it can block the flow of underfill to the solderless area of the encapsulation layer, reducing the area of the overflow area. This ensures the underfill fillet height at the periphery of the upper surface of the lower encapsulation layer, thereby improving the quality stability of the dispensing process of the lower encapsulation layer and avoiding the problem of void delamination of the lower surface.
  • a mechanical support layer is disposed on the upper surface of the lower encapsulation layer.
  • the mechanical support layer is disposed in a second region of the upper surface of the lower encapsulation layer.
  • the mechanical support layer is a Dummy ball.
  • FIG. 5(a) is a side view of the lower encapsulation layer
  • FIG. 5(b) is a side view
  • FIG. 5(c) is a top view of the lower encapsulation layer
  • FIG. 5 ( d) is a bottom view of the lower encapsulation layer.
  • a Dummy ball is disposed in a second region of the upper surface of the lower encapsulation layer.
  • the deformation of the upper encapsulation layer under mechanical load is reduced, thereby solving the problem of silicon wafer fracture failure inside the upper encapsulation layer.
  • the Dummy ball may be soldered to the Dummy pad on the transfer board portion of the lower package layer by reflow soldering.
  • the lower surface of the upper encapsulation layer adds a Dummy pad corresponding to the Dummy ball at a corresponding position, so that the upper encapsulation layer and the lower encapsulation layer package form a dummy solder joint.
  • Non-functional solder joints refer to solder joints soldered to the PCB, but are not connected to specific electronics.
  • the Dummy ball is added to the second region on the lower encapsulation layer, which can reduce the deformation of the upper encapsulation layer when subjected to mechanical load. If the upper encapsulation layer overflows, the stress near the edge of the overflow will be significantly improved, thereby solving the problem of failure of the silicon wafer inside the upper encapsulation layer.
  • the mechanical support layer is Dummy EMC.
  • FIG. 6(a) is a side view of the lower encapsulation layer
  • FIG. 6(b) is a side view
  • FIG. 6(c) is a top view of the lower encapsulation layer
  • Dummy EMC is disposed in the second region of the upper surface of the lower encapsulation layer to reduce the deformation of the upper encapsulation layer when subjected to mechanical load, thereby solving the problem of silicon wafer fracture failure inside the upper encapsulation layer.
  • the Dummy EMC can be simultaneously or separately molded onto the transfer board of the lower package layer with the EMC in the middle of the package of the lower package layer.
  • the deformation of the upper encapsulation layer when subjected to mechanical load can be reduced. If the upper encapsulation layer overflows, the stress near the edge of the overflow will be significantly improved, thereby solving the problem of failure of the silicon wafer inside the upper encapsulation layer.
  • the Dummy EMC's face support can significantly improve the stress on the upper encapsulation layer relative to the point support of the Dummy ball.
  • the Dummy EMC's surface support is compared to the Dummy ball's point support, it can block the flow of the underfill-free encapsulation layer without solder joints, reducing the area of the overflow area. This ensures that the underfill fillet height of the outer surface of the lower encapsulation layer is ensured, thereby improving the quality of the dispensing process of the lower encapsulation layer, and avoiding problems such as void and delamination defects on the lower surface.
  • mechanical support layer can be equivalently replaced by Dummy ball or Dummy EMC or other structures and materials of the same principle.
  • the Dummy ball and the Dummy EMC have wider heat dissipation channels than the conventional PoP.
  • the heat generated by the encapsulation layer under the conventional PoP can only be exported to the upper encapsulation layer through the limited peripheral solder joint between the upper and lower encapsulation layers.
  • the Dummy ball and the Dummy EMC provided in the embodiment of the present application can also be used as the lower package.
  • the layer is a heat-conducting channel that encloses the layer.
  • the circuit board includes a PCB board 710, a mechanical support layer 720, and an electronic component 730.
  • the PCB board is connected to the electrical function solder joint disposed in the first area of the electronic component through the pad disposed in the first area of the PCB board; the mechanical support layer is disposed in the second area of the electronic component; wherein, An area is disposed on the periphery of the second area.
  • the electronic component may be a single-layer Ball Grid Array (BGA) of peripheral solder joints, or a mechanical support layer may be disposed in a central region, with specific reference to FIG. 7(a)- (b); wherein FIG. 7(a) shows that no mechanical support layer is provided, FIG. 7(b) sets Dummy ball, and FIG. 7(c) sets Dummy EMC. It can solve the problem of silicon wafer fracture failure in BGA.
  • BGA Ball Grid Array
  • the first area of the BGA is the periphery of the BGA, and the second area is the central area of the BGA.
  • the mechanical support layer is disposed in the second region of the electronic component, and the deformation variable when the multi-package layer is mechanically deformed is reduced, thereby solving the problem that the silicon wafer breaks in the package layer.
  • FIG. 8 is a device according to an embodiment of the present invention, which includes the high reliability electronic package structure provided in FIG. 1 to FIG. Only three high-reliability electronic package structures are illustrated in FIG. 8 as an example.
  • the high reliability electronic package structure is soldered to a printed circuit board. Can be applied to portable devices such as mobile phones.
  • Dummy ball or Dummy EMC Enhance the mechanical support of the upper encapsulation layer by Dummy ball or Dummy EMC, and reduce the risk of failure of the silicon wafer inside the encapsulation layer when subjected to external load.
  • the Dummy EMC solution can also reduce the possibility of underfill overflowing to the gap between the upper and lower encapsulation layers by forming a similar full fill effect between the upper and lower encapsulation layers prior to dispensing.
  • Dummy ball and Dummy EMC, especially high thermal conductivity EMC can widen the heat dissipation channel from the lower package layer to the upper package layer, improve heat dissipation, electrical performance and thermal / mechanical reliability
  • Dummy ball can also share the mechanical/thermal stress on the peripheral functional solder joint between the lower package layer and the upper package layer, and improve the reliability of the peripheral solder joint between the lower package layer and the upper package layer.
  • Dummy EMC forms a symmetrical structure on the lower and lower sides of the lower package substrate or the upper package layer, which helps to improve the lower encapsulation layer and the upper encapsulation layer due to the coefficient of thermal expansion (CTE) of the various parts inside the package.
  • CTE coefficient of thermal expansion

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Abstract

一种高可靠性电子封装结构、电路板及设备，该高可靠性电子封装结构包括：高可靠性电子封装结构包括多个封装层（210-250）和机械支撑；在多个封装层的每个封装层的第一区域设置电气功能焊点，任意相邻的两个封装层通过电气功能焊点连接；在多个封装层的每个封装层的第二区域设置机械支撑层，机械支撑层用于支撑相邻的两个封装层；其中，第一区域设置在第二区域的外围。通过该技术方案，可解决上封装层或下封装层的内部硅片，在受到机械荷载，断裂失效的问题。

Description

一种高可靠性电子封装结构、电路板及设备 技术领域
本发明涉及电子板领域，尤其涉及一种高可靠性电子封装结构、电路板及设备。
背景技术
为了满足便携式及可穿戴设备对电子封装组件短小轻薄的要求，通过堆叠封装(Package on Package,PoP)把应用处理器(Application Processor,AP)和存储器等堆叠在一起，此种解决方案得到了越来越广泛的应用。PoP作为终端产品中尺寸最大的电子元件，面临着严峻的机械和环境可靠性风险。如在跌落冲击和温度循环荷载下的板级(PoP和主板之间的)焊点金属化合物(Intermetallic Compound,IMC)或引线断裂失效等(见图2)。
现有技术中，为了改善PoP在跌落、弯曲和温度循环等荷载下的可靠性，下表面填充(underfill)材料被广泛用于保护板级焊点。Underfill可以将原本集中在元件角落焊点上的机械和热应力相对平均地分配到所有焊点，从而提升PoP的整体可靠性。为了改善underfill的填充速度和返修性，目前的板级underfilll通常选用没有填料(filler)的低粘度underfill,这使得在对PoP下封装层和印制电路板(Printed circuit board，PCB)之间进行下表面填充时,underfill会在点胶边溢到PoP下层和上封装层之间的局部区域。在这种情况下，PoP在受到机械载荷时会在溢胶边缘位置产生应力集中，并最终导致上封装层内的硅片断裂。
发明内容
本发明实施例涉及一种高可靠性电子封装结构、电路板及设备。通过PoP上层的封装结构和下层的封装结构以实现PoP上封装层局部填充导致的PoP上封装层内部硅片断裂失效的问题。
第一方面，本发明实施例提供了一种高可靠性电子封装结构，该高可靠性电子封装结构包括：包括多个封装层和机械支撑层；在多个封装层的每个封装层的第一区域设置电气功能焊点，任意相邻的两个封装层通过电气功能焊点连接；在多个封装层的每个封装层的第二区域设置机械支撑层，机械支撑层用于支撑相邻的两个封装层；其中，第一区域设置在第二区域的外围。
本发明实施例通过在多层封装层的中任意相邻的封装层第二区域设置机械支撑层，减少多封装层受到机械形变时的形变量，解决了封装层内部硅片断裂失效的问题。
在一个可能的实施例中，机械支撑层设置在每个封装层的上表面或者下表面，解决了封装层内部硅片断裂失效的问题。
在一个可能的实施例中，机械支撑层包括非功能焊球或塑封。
第二方面，本发明实施例他、提供了一种电路板，其特征在于，电路板包括PCB板、电子元器件和机械支撑层；PCB板通过设置在PCB板第一区域的焊盘与设置在电子元器件的第一区域的电气功能焊点相连接；机械支撑层设置在电子元器件的第二区域；其中，第一区域设置在第二区域的外围。
本发明实施例通过在电子元器件的第二区域设置机械支撑层，减少多封装层受到机械形变时的形变量，解决了封装层内部硅片断裂失效的问题。
第三方面，本发明实施例提供了一种设备，该设备包括上述的高可靠性电子封装结构。
相较于现有技术，本发明实施例提供的技术方案可以解决PoP上封装层或下封装层的内部硅片，在受到机械荷载，断裂失效的问题。
附图说明
[根据细则26改正10.07.2017]　
图1(a-1)-图1(a-2)为现有技术中电子封装的结构示意图；
图2为本发明实施例提供的第一种高可靠性电子封装结构的结构示意图；
[根据细则26改正10.07.2017]　
图3(a)-图3(b)为本发明实施例提供的第二种高可靠性电子封装结构的结构示意图；
[根据细则26改正10.07.2017]　
图4(a)-图4(b)为本发明实施例提供的第三种高可靠性电子封装结构的结构示意图；
[根据细则26改正10.07.2017]　
图5(a)-图5(d)为本发明实施例提供的第四种高可靠性电子封装结构的结构示意图；
[根据细则26改正10.07.2017]　
图6(a)-图6(d)为本发明实施例提供的第五种高可靠性电子封装结构的结构示意图；
[根据细则26改正10.07.2017]　
图7(a)-图7(c)为一种电路板的结构示意图；
图8为本发明实施例提供的一种设备的结构示意图。
具体实施方式
在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明实施例。在本发明实施例和权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其它含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能的组合。本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
图2为本发明实施例提供的一种高可靠性电子封装结构的结构示意图。如图2所示，该高可靠性电子封装结构包括多个封装层和支撑层。多个封装层包括至少两个封装层。在多个封装层的每个封装层的第一区域设置电气功能焊点，任意相邻的两个封装层通过电气功能焊点连接；在多个封装层的每个封装层的第二区域设置机械支撑层，机械支撑层用于支撑相邻的两个封装层；其中，第一区域设置在第二区域的外围。在附图2中以封装层210、封装层220、封装层230、封装层240和封装层250、4个机械支撑层为一个示例。
具体地，在封装层210、封装层220、封装层230、封装层240、封装层250的第一区域设置电气功能焊点，封装层210与封装层220，封装层220与封装层230，封装层230与封装层240，封装层240与封装层250都通过电气功能焊点连接；以及在封装层210、封装层220、封装层230、封装层240、封装层250的第二区域设置机械支撑层，其中，第一区域设置在第二区域的外围。电气功能焊点是为了实现多个封装层之间的电气连接，也就是实现物理上的连接，多个封装层之间有信号传输。
在一个可能的实施例中，第一区域位于多个封装层的每个封装层的上表面或下表面。
以封装层210和封装层220为例说明。具体地，封装层210的第一区域设置在封装层210的下表面，封装层220的第一区域设置在封装层220的上表面，封装层210的第一区域和封装层220的第二区域对应。
在一个可能的实施例中，机械支撑层包括非电气功能焊点或塑封。
需要说明的是，机械支撑层可以通过非电气功能焊点或塑封或相同原理的其他结构和材料来等效替代。非电气功能焊点，与电气功能焊点相对于，非电气功能焊点用于支持任意两个封装层。非电气功能焊点可以为假焊点(Dummy ball)或塑封(Epoxy Mold Compound，EMC)。
在一个可能的实施例中，多个封装层中每个封装层是规则的形状，例如，多个多个封装层中每个封装层的形状是方形，第一区域是多个封装层中每个封装层的四周，那么第二区域就是多个封装层中每个封装层的中央区域。
在一个可能的实施例中，高可靠性电子封装结构包括两个封装层，如上封装层和下封装层。
在一个可能的实施例中，对于上封装层，机械支撑层设置在上封装层的下表面。
在一个可能的实施例中，机械支撑层为Dummy ball。
具体地，在上封装层的下表面的第一区域设置Dummy ball。减少上封装层在受到机械荷载时发生的形变，进而解决了上封装层内部的硅片断裂失效的问题。具体如附图3所示，其中附图3(a)为上封装层的仰视图，附图3(b)为上封装层的侧视图。
本发明实施例，通过在上封装层的下表面的第一区域增加Dummy ball来增加机械支撑，减少上封装层在受到机械荷载时的形变量，进而解决了上封装层内部硅片断裂失效的问题。
从工艺方面说明本发明实施例的可行性，Dummy ball可以和上封装层第一区域设置的电气功能焊点同时焊接到上封装层的基板(substrate)上，相较于现有技术不增加额外的工艺步骤，只需要在下封装层的上表面对应的位置增加假焊盘(Dummy pad)。
为了验证本发明实施例的改善效果，可采用有限元分析对本发明实施例和现有技术方案，在受到机械荷载时，上封装层的应力水平。假设，有限元分析的荷载条件为50N。
下表为本发明实施例和现有技术方案，在受到机械荷载时，上层封装的应力(MPa)。
Figure PCTCN2017078888-appb-000001
从上表可知，本发明实施例相较于现有技术，上封装层上部应力改善了74.6％。
在本发明实施例中，在受到机械荷载时，可以对上封装层的任意区域进行应力分析，例如可以对上封装层的左上角进行应力分析，因为，在给上封装层填充underfill时，上封装层的左上角也会有underfill填充，所以可以对上封装层的左上角进行应力分析。
需要说明的是，有限元分析的过程是现有技术。且与有限元分析具有相同功能的都可以进行等效替换。
本发明实施例在上封装层的下表面第二区域增加Dummy ball，可以减少上封装层在受到机械荷载时的形变量。若上封装层发生溢胶，溢胶边缘附近的应力也会被明显改善，进而解决了上封装层内部硅片断裂失效的问题。
在一个可能的实施例中，机械支撑层为EMC，为了与上封装层的上表面的EMC区分， 机械支撑层在下文称为Dummy EMC。具体如附图4所示，其中附图4(a)为上封装层的仰视图，附图4(b)为上封装层的侧视图。
具体地，在上封装层的下表面第二区域设置Dummy EMC。减少上封装层在受到机械荷载时发生的形变，进而解决了上封装层内部的硅片断裂失效的问题。
从工艺方面说明本发明实施例的可行性，Dummy EMC可以和上封装层的上表面的EMC同时或分别注塑(molding)到上封装层的封装基板(substrate)上。相较于现有技术，本发明实施例不增加额外的工艺步骤。
为了验证本发明实施例的改善效果，可采用有限元分析对本发明实施例和现有技术方案，在受到机械荷载时的应力，上封装层的应力水平。假设，有限元分析的荷载条件为50N。
下表为本发明实施例和现有技术方案，在受到机械荷载时，上层封装的应力(MPa)。
Figure PCTCN2017078888-appb-000002
从上表可知，本发明实施例相较于现有技术，上封装层上表面应力改善了96％。
本发明实施例通过在上封装层的下表面的第二区域，增加Dummy EMC，可以减少上封装层在受到机械荷载时的形变量。若上封装层发生溢胶，溢胶边缘附近的应力也会被明显改善，进而解决了上封装层内部硅片断裂失效的问题。此外，Dummy EMC的面支撑相对于Dummy ball的点支撑可以更明显地改善上封装层的应力。同时，由于Dummy EMC的面支撑相较于Dummy ball的点支撑，可以阻挡underfill向上封装层无焊点的区域的流动，减少溢胶区域面积。这就保证了下封装层的上表面外围的underfill fillet高度，进而提高了下封装层的间隙的点胶工艺质量稳定性，避免下表面气泡(void)分层缺陷等问题。
在一个可能的实施例中，对于下封装层，机械支撑层设置在下封装层的上表面。
具体地，机械支撑层设置在下封装层的上表面的第二区域。
在一个可能的实施例中，机械支撑层为Dummy ball。具体如附图5所示，其中附图5(a)为下封装层的侧视图，附图5(b)为侧视图，附图5(c)为下封装层的俯视图，附图5(d)为下封装层的仰视图。
具体地，在下封装层的上表面的第二区域设置Dummy ball。减少上封装层在受到机械荷载时发生的形变，进而解决了上封装层内部的硅片断裂失效的问题。
在本发明实施例，通过在下封装层的上表面的第二区域增加Dummy ball来增加机械支撑，可以减少上封装层在受到机械荷载时的形变量，进而解决了上封装层内部硅片断裂失效的问题。
从工艺方面说明本发明实施例的可行性，Dummy ball可采用回流焊接(reflow)的方式焊接到下封装层的转接板上部的Dummy pad上。上封装层的下表面在对应的位置增加与Dummy ball对应的Dummy pad，以便上封装层和下封装层封装形成非功能焊点(dummy solder joint)。非功能焊点是指焊接到PCB板上的焊点，但是不连接具体的电子器件。
本发明实施例在下封装层上的第二区域增加Dummy ball，可以减少上封装层在受到机械荷载时的形变量。若上封装层发生溢胶，溢胶边缘附近的应力也会被明显改善，进而解决了上封装层内部硅片断裂失效的问题。
在一个可能的实施例中，机械支撑层为Dummy EMC。具体如附图6所示，其中附图6(a)为下封装层的侧视图，附图6(b)为侧视图，附图6(c)为下封装层的俯视图，附图6(d)为下封装层的仰视图
具体地，在下封装层的上表面的第二区域设置Dummy EMC，减少上封装层在受到机械荷载时发生的形变，进而解决了上封装层内部的硅片断裂失效的问题。
从工艺方面说明本发明实施例的可行性，Dummy EMC可以和下封装层的封装中部的EMC同时或分别注塑(molding)到下封装层的转接板上。
本发明实施例，通过在下封装层的上表面的第二区域，增加Dummy EMC，可以减少上封装层在受到机械荷载时的形变量。若上封装层发生溢胶，溢胶边缘附近的应力也会被明显改善，进而解决了上封装层内部硅片断裂失效的问题。此外，Dummy EMC的面支撑相对于Dummy ball的点支撑可以更明显地改善上封装层的应力。同时，由于Dummy EMC的面支撑相较于Dummy ball的点支撑，可以阻挡underfill向上封装层无焊点区域的流动，减少溢胶区域面积。这就保证了保证了下封装层的上表面外围的underfill fillet高度，进而提高了下封装层的间隙的点胶工艺质量稳定性，避免下表面出现void,分层缺陷等问题。
需要说明的是，机械支撑层可以通过Dummy ball或Dummy EMC或相同原理的其他结构和材料来等效替代。
在本发明实施例中，Dummy ball和Dummy EMC相对于传统PoP有更宽的散热通道。传统PoP下封装层产生的热量只能通过上、下封装层之间有限的外围焊点导出到上封装层，在此基础上，本申请实施例设置的Dummy ball和Dummy EMC也可以作为下封装层向上封装层导热的通道。
图7(a)-(c)为一种电路板的结构示意图。如图7所示，该电路板包括：PCB板710、机械支撑层720和电子元器件730。
具体地，PCB板通过设置在PCB板第一区域的焊盘与设置在电子元器件的第一区域的电气功能焊点相连接；机械支撑层设置在电子元器件的第二区域；其中，第一区域设置在第二区域的外围。
在一个可能的实施例中，电子元器件可以为外围焊点的单层球形栅格阵列(Ball Grid Array，BGA)，也可以在中央区域设置机械支撑层，具体参照附图7(a)-(b)；其中附图7(a)为没有设置机械支撑层，附图7(b)设置Dummy ball，附图7(c)设置Dummy EMC。可以解决BGA内部硅片断裂失效的问题。
需要说明的是，BGA的第一区域是BGA的外围，第二区域是BGA的中央区域。
本发明实施例通过在电子元器件的第二区域设置机械支撑层，减少多封装层受到机械形变时的形变量，解决了封装层内部硅片断裂失效的问题。
图8为本发明实施例提供的一种设备，该设备包括附图1-附图6中提供的高可靠性的电子封装结构。在附图8中仅以三个高可靠性电子封装结构为示例进行说明。
在一种可能的实施例中，该高可靠性电子封装结构是焊接到印制电路板。可应用于便携式设备如手机等。
本发明技术方案的效果有以下几点：
1、通过Dummy ball或Dummy EMC增强对上封装层的机械支撑，降低在受到外部荷载时上封装层内部硅片断裂失效风险。此外Dummy EMC方案还可以通过在点胶前在上封装层和下封装层之间形成类似完全填充的效果，来实现降低underfill向上溢到上封装层和下封装层之间的缝隙的可能性。
2、Dummy ball和Dummy EMC，尤其是高导热率EMC可以扩宽从下封装层到上封装层的散热通道,改善散热、电气性能和热/机械可靠性
3、Dummy ball还可以分摊下封装层和上封装层之间外围功能焊点受到的机械/热应力，改善下封装层和上封装层之间外围焊点的可靠性。
4、Dummy EMC在下封装层基板或上封装层转接板上下两侧形成对称结构，这有助于改善下封装层和上封装层由于封装内部各部分材料热膨胀系数(Coefficient of Thermal Expansion，CTE)差异而导致的翘曲(Warpage)以及与warpage紧密相关的组装良率。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关硬件来完成，所述的程序可以存储于一个设备的可读存储介质中，该程序在执行时，包括上述全部或部分步骤，所述的存储介质，如：FLASH、EEPROM等。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

  1. 一种高可靠性电子封装结构，其特征在于，所述高可靠性电子封装结构包括多个封装层和机械支撑层；
    在所述多个封装层的每个封装层的第一区域设置电气功能焊点，任意相邻的两个封装层通过所述电气功能焊点连接；
    在所述多个封装层的每个封装层的第二区域设置机械支撑层，所述机械支撑层用于支撑所述相邻的两个封装层；其中，所述第一区域设置在所述第二区域的外围。
  2. 根据权利要求1所述的高可靠性电子封装结构，其特征在于，所述第一区域位于所述每个封装层的上表面或者下表面。
  3. 根据权利要求1或2所述的高可靠性电子封装结构，其特征在于，所述机械支撑层包括非电气功能焊点或塑封。
  4. 一种电路板，其特征在于，所述电路板包括PCB板、电子元器件和机械支撑层；所述PCB板通过设置在所述PCB板第一区域的焊盘与设置在所述电子元器件的第一区域的电气功能焊点相连接；所述机械支撑层设置在所述电子元器件的第二区域；其中，所述第一区域设置在所述第二区域的外围。
  5. 一种设备，其特征在于，包括如权利要求1至3任一项所述的高可靠性电子封装结构。
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