JP2017041603A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017041603A JP2017041603A JP2015163959A JP2015163959A JP2017041603A JP 2017041603 A JP2017041603 A JP 2017041603A JP 2015163959 A JP2015163959 A JP 2015163959A JP 2015163959 A JP2015163959 A JP 2015163959A JP 2017041603 A JP2017041603 A JP 2017041603A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- memory device
- wiring board
- resin
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、半導体装置PKG1の回路構成例を説明した後、半導体装置PKG1の構造について説明する。図1は、本実施の形態の半導体装置が有する回路の構成例を示す説明図である。
次に、図1に示す半導体装置PKG1の構造について説明する。図2は、図1に示す半導体装置のデバイス搭載面側の平面図である。図3は、図2に示す半導体装置のA−A線に沿った断面図である。また、図4は、図2に示す半導体装置の下面側の構造を示す平面図である。また、図5は、図2に示すロジックデバイスの表面側の平面図である。また、図6は、図2に示すメモリデバイスの表面側の平面図である。また、図7は、図6のA−A線に沿った断面図である。
次に、図2に示す配線基板10の上面10tにおける複数の半導体デバイスのレイアウトの詳細について説明する。図2に示すように、本実施の形態の配線基板10の上面10tに搭載される複数の半導体デバイスのうち、ロジックデバイスLCは、他の半導体デバイス(メモリデバイスMC)との間隔(離間距離)、および配線基板10の上面10tの周縁端との間隔(離間距離)が大きい。
図8は、図2に示す配線基板のデバイス搭載面のうち、ロジックデバイスと配線基板の辺の間に配置されるメモリデバイスの周辺を強調して示す平面図である。図9は、図8のA−A線の拡大断面図である。
次に、図1〜図12を用いて説明した半導体装置PKG1の製造工程について説明する。以下の説明では、製造工程の流れを示すフロー図と、図1〜図12を必要に応じて参照しながら説明する。図13は、図1〜図12を用いて説明した半導体装置の製造工程の概要を示す説明図である。なお、本実施の形態では、説明を単純化するために、図2に示す配線基板10に半導体デバイスを搭載する実施態様について説明する。しかし、変形例としては、配線基板10に相当する複数の製品形成領域を備える、所謂多数個取り基板を準備して、複数の半導体装置を一括して組立てた後、製品形成領域毎に個片化する方法もある。この場合、組立工程を効率化することができる。
まず、配線基板準備工程では、図14に示す配線基板10を準備する。図14は、図13に示す配線基板準備工程で準備する配線基板のデバイス搭載面側を示す平面図である。本工程で準備する配線基板10には、上面10t側に複数のデバイス搭載領域DBR(図3に示す半導体デバイスが搭載される予定領域)が設けられ、複数のデバイス搭載領域DBRのそれぞれの内側には、開口部において絶縁膜17tから露出する複数のボンディングパッド14が形成されている。
次に、デバイス搭載工程では、図2に示すように配線基板10のデバイス搭載領域DBR(図14参照)にロジックデバイスLCおよび複数のメモリデバイスMCのそれぞれを搭載する。
次に、接続部封止工程では、複数の突起電極SB2により半導体デバイスと配線基板とが電気的に接続された接続部分の周囲を、樹脂などの絶縁材料で封止する。図15は、図13に示す接続部封止工程で、半導体デバイスと配線基板の間に樹脂を配置して半導体デバイスの電極と配線基板の端子の接続部分を封止した状態を示す拡大断面図である。なお、図15では、樹脂の供給方向の一例を幅が広い矢印で示している。
次に、ボールマウント工程では、図3に示すように、配線基板10の下面10bに形成された複数の端子15に、外部端子になる複数の半田ボールSB1を接合する。
次に、検査工程では、半導体装置PKG1(図1参照)の外観検査など、必要な検査を行う。ここで、上記した接続部封止工程で使用した樹脂UFが配線基板10の周縁端を超えて広がり、例えば一部が配線基板10の側面に付着した場合、外観検査工程において、不良品と判定される場合がある。
例えば、上記実施の形態では、接続部封止工程で、半導体デバイスと配線基板10とを電気的に接続する接続部分を封止する樹脂UFの配置方法として、デバイス搭載工程の後で、樹脂UFを供給する、後注入方式の実施態様について説明した。しかし、接続部分の封止方法には種々の変形例がある。図16は、図13に対する変形例である半導体装置の製造工程の概要を示す説明図である。図17は、図16に示す封止材配置工程において、デバイス搭載領域に樹脂材料を配置した状態を示す平面図である。また、図18は、図16に示すデバイス搭載工程において、半導体デバイスを裏面側から押圧して配線基板上に搭載している状態を示す拡大断面図である。
また、上記実施の形態では、ダム部DMの例として、図19に示すように、絶縁膜17t上に突出するように形成した壁(凸部)であるダム部DMを用いて説明した。しかし、図19に示す変形例のダム部DMTのように、絶縁膜17t上に配置された絶縁膜18に形成された溝パターンをダム部DMとして用いても良い。図19は、図9に対する変形例である半導体装置の拡大断面図である。
また例えば、上記実施の形態で説明した図2に示す半導体装置PKG1の半導体デバイスのレイアウトは、幾つかの半導体デバイスが配線基板10の周縁端の近傍に配置される場合の一例である。したがって、半導体デバイスのレイアウトには、種々の変形例がある。例えば、半導体デバイスが1個だけの場合であっても、他の電子部品との接続の関係などの理由により、配線基板の周縁部に寄せて半導体デバイスを搭載する場合が考えられる。この場合、上記実施の形態で説明した技術を適用することにより、樹脂UFが配線基板の周縁端にまで広がることを抑制できる。
また、上記実施の形態では、半導体デバイスを配線基板に搭載して、半導体デバイスと配線基板とを電気的に接続する方法として、フリップチップ接続方式を取り上げて説明した。しかし、変形例として、半導体デバイスの電極配置面の反対側に位置する裏面と配線基板の上面とを対向させた状態で、配線基板上に半導体デバイスを搭載しても良い。
また、上記実施の形態および各変形例では、配線基板10の上面10t上に搭載された複数の半導体デバイスは、カバー部材や放熱部材などの他の部材に覆われず、露出している実施態様について説明した。しかし、図21に示す半導体装置PKG4のように、半導体デバイスが、他の部材で覆われていても良い。図21は図2に対する変形例である半導体装置の上面図である。また、図22は図21のA−A線に沿った断面図である。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)第1面、前記第1面に形成された第1絶縁膜、および前記第1絶縁膜に形成された第1ダム部を有する配線基板を準備する工程、
(b)前記配線基板の前記第1面上に第1半導体デバイスを搭載する工程、
(c)前記第1絶縁膜と前記第1半導体デバイスとの間に第1樹脂を配置する工程、
ここで、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記(b)工程では、平面視において、前記第1半導体デバイスが、前記第1半導体デバイスと前記第1辺との間隔が前記第1半導体デバイスと前記第2辺との間隔より小さくなるように、前記配線基板の前記第1面に搭載され、
前記第1ダム部は、前記第1半導体デバイスと前記第1辺との間に形成されている一方、前記第1半導体デバイスと前記第2辺との間には形成されていない。
以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)第1面、前記第1面に形成された第1絶縁膜、および前記第1絶縁膜に形成された第1ダム部を有する配線基板を準備する工程、
(b)前記配線基板の前記第1面上に第1樹脂を配置する工程、
(c)前記第1樹脂に第1半導体デバイスを押し付けて、前記第1半導体デバイスを前記配線基板上に搭載する工程、
ここで、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記(b)工程では、平面視において、前記第1半導体デバイスが、前記第1半導体デバイスと前記第1辺との間隔が前記第1半導体デバイスと前記第2辺との間隔より小さくなるように、前記配線基板の前記第1面に搭載され、
前記第1ダム部は、前記第1半導体デバイスと前記第1辺との間に形成されている一方、前記第1半導体デバイスと前記第2辺との間には形成されていない。
第1面、前記第1面に形成された第1絶縁膜、および前記第1絶縁膜に形成されたダム部を有する配線基板と、
前記配線基板の前記第1面上に搭載された第1半導体デバイスおよび第2半導体デバイスと、
前記第1絶縁膜と前記第1半導体デバイスとの間に位置する第1樹脂と、
前記第1絶縁膜と前記第2半導体デバイスとの間に位置する第2樹脂と、
を含み、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記第1面において、前記第1半導体デバイスは、前記第1辺と前記第2辺との間に搭載され、かつ、前記第2半導体デバイスは、前記第1半導体デバイスと前記第2辺との間に搭載され、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2半導体デバイスとの間隔より小さく、
前記第2半導体デバイスと前記第2辺との間隔は、前記第1半導体デバイスと前記第2半導体デバイスとの間隔より小さく、
前記ダム部は、前記第1半導体デバイスと前記第1辺との間、および前記第2半導体デバイスと前記第2辺の間にそれぞれ形成され、かつ、前記第1半導体デバイスと前記第2半導体デバイスとの間には形成されていない、半導体装置。
第1面、前記第1面に形成された第1絶縁膜、および前記第1絶縁膜に形成されたダム部を有する配線基板と、
前記配線基板の前記第1面上に搭載された第1半導体デバイスおよび第2半導体デバイスと、
前記第1絶縁膜と前記第1半導体デバイスとの間に位置する第1樹脂と、
前記第1絶縁膜と前記第2半導体デバイスとの間に位置する第2樹脂と、
を含み、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記第1面において、前記第1半導体デバイスおよび前記第2半導体デバイスのそれぞれは、前記第1辺と前記第2辺との間に搭載され、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔、および前記第1半導体デバイスと前記第2半導体デバイスとの間隔のそれぞれより小さく、
前記第2半導体デバイスと前記第1辺との間隔は、前記第2半導体デバイスと前記第2辺との間隔、および前記第1半導体デバイスと前記第2半導体デバイスとの間隔のそれぞれより小さく、
前記第1半導体デバイスと前記第2半導体デバイスの間隔は、前記第1半導体デバイスおよび前記第2半導体デバイスのうちの1つ分の大きさよりも大きく、
前記第1半導体デバイスと前記第1辺との間には前記ダム部のうちの第1ダム部が形成され、
前記第2半導体デバイスと前記第1辺との間には前記ダム部のうちの第2ダム部が形成され、
前記第1ダム部と前記第2ダム部とは分離されている、半導体装置。
10b 下面(面、主面、実装面)
10s 側面
10s1、10s2、10s3、10s4 基板辺
10t 上面(面、主面、デバイス搭載面)
12TW スルーホール配線
12VW ビア配線
12WL 配線
13 絶縁層
13c コア層(コア材、コア絶縁層)
14 ボンディングパッド(ボンディングリード、半導体デバイス接続用端子)
15 端子(ランド、外部接続端子)
17b、17t、18 絶縁膜(ソルダレジスト膜)
21P 電極(チップ端子、ボンディングパッド)
21s1、21s2、21s3、21s4、22s1、22s2、22s3、22s4 デバイス辺(辺)
22 半導体チップ(メモリチップ)
22DB、33 接着材
22P 電極(チップ端子、ボンディングパッド)
22WL 配線
22WS 配線基板(パッケージ基板)
30 押圧治具
31 部材(放熱部材)
31SU 支持部
32 接着層
BW ワイヤ(導電性部材)
BR1 領域
CAC 入出力回路
CG1、CG2 隙間
CTL 制御回路
DBR デバイス搭載領域
DM、DM1、DM11、DM12、DM2、DM3、DMT ダム部
DMs 側面
LC ロジックデバイス(半導体デバイス)
LCb 裏面(主面、下面)
LCt 表面(主面、上面)
M1、M2、M3、M4、MC メモリデバイス(半導体デバイス)
MCb 裏面(主面、下面)
MCt 表面(主面、上面)
MR 封止体(樹脂、封止材)
NCL 封止材
PD 電極(パッド)
PKG1、PKG2、PKG3、PKG4 半導体装置
PR1、PR3、PR4 周縁領域
PRC 演算処理回路
PWR1、PWR2 電力供給経路
RAM メモリ回路
SB1 半田ボール(半田材、外部端子、電極、外部電極)
SB2 突起電極(バンプ電極、導電性部材)
SGP1、SGP2 信号伝送経路
SP1、SP2、SP3、SP4、SP5、SP6、SP7、SPL1、SPL3、SPLs1、SPLs2、SPLs3、SPLs4、SPMM1 間隔(離間距離)
UF 樹脂(アンダフィル樹脂、絶縁性樹脂)
WL1、WL2、WL3、WL4、WL5、WL6 配線層
Claims (16)
- 第1面、前記第1面に形成された第1絶縁膜、および前記第1絶縁膜に形成されたダム部を有する配線基板と、
前記配線基板の前記第1面上に搭載された第1半導体デバイスと、
前記第1絶縁膜と前記第1半導体デバイスとの間に位置する第1樹脂と、
を含み、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔より小さく、
前記ダム部は、前記第1半導体デバイスと前記第1辺との間に形成され、かつ、前記第1半導体デバイスと前記第2辺との間には形成されていない、半導体装置。 - 請求項1において、
前記第1面の平面形状は、前記第1辺と、前記第2辺と、前記第1辺および前記第2辺のそれぞれと交差する第3辺と、前記第3辺の反対側に位置し、かつ、前記第1辺および前記第2辺のそれぞれと交差する第4辺と、を有する四角形から成り、
前記第1半導体デバイスと前記第3辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔より小さく、
前記配線基板は、
前記第1絶縁膜に形成され、かつ、前記第1半導体デバイスと前記第1辺との間に形成された第1ダム部と、
前記第1絶縁膜に形成され、かつ、前記第1半導体デバイスと前記第3辺との間に形成された第2ダム部と、
を有し、
前記第2ダム部は、前記第1ダム部と繋がっている、半導体装置。 - 請求項2において、
前記第1面のうち、前記第1半導体デバイスと前記第1辺との間に位置する領域の全ておよび前記第1半導体デバイスおよび前記第3辺との間に位置する領域の全ては、前記第1絶縁膜で覆われている、半導体装置。 - 請求項2において、
前記第1半導体デバイスと前記第3辺との間隔は、前記第1半導体デバイスと前記第1辺との間隔と同じである、半導体装置。 - 請求項1において、
前記第1面の平面形状は、前記第1辺と、前記第2辺と、前記第1辺および前記第2辺のそれぞれと交差する第3辺と、前記第3辺の反対側に位置し、かつ、前記第1辺および前記第2辺のそれぞれと交差する第4辺と、を有する四角形から成り、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第3辺との間隔、および前記第1半導体デバイスと前記第4辺との間隔のそれぞれより小さい、半導体装置。 - 請求項5において、
前記第1面のうち、前記第1半導体デバイスと前記第1辺との間に位置する領域の全ておよび前記第1半導体デバイスおよび前記第3辺との間に位置する領域の全ては、前記第1絶縁膜で覆われている、半導体装置。 - 請求項1において、
前記第1面の平面形状は、前記第1辺と、前記第2辺と、前記第1辺および前記第2辺のそれぞれと交差する第3辺と、前記第3辺の反対側に位置し、かつ、前記第1辺および前記第2辺のそれぞれと交差する第4辺と、を有する四角形から成り、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第3辺との間隔より小さく、
前記ダム部は、前記第1半導体デバイスと前記第3辺との間には形成されていない、半導体装置。 - 請求項1において、
前記配線基板の前記第1面上には、前記第2辺と前記第1辺との間に第2半導体デバイスが搭載され、
前記第1半導体デバイスと前記第1辺との間隔は、前記第2半導体デバイスと前記第1辺との間隔、および前記第2半導体デバイスと前記第2辺との間隔のそれぞれよりも小さい、半導体装置。 - 請求項8において、
前記第2半導体デバイスは、前記第1半導体デバイスと前記第2辺との間に搭載され、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2半導体デバイスとの間隔よりも小さい、半導体装置。 - 請求項9において、
前記第1半導体デバイスは第1回路を有し、前記第2半導体デバイスは前記第1回路の動作を制御する第2回路を有する、半導体装置。 - 請求項8において、
前記第1半導体デバイスと前記第1面との隙間は、前記第2半導体デバイスと前記第1面との隙間よりも大きい、半導体装置。 - 請求項1において、
前記第1面の平面形状は、前記第1辺と、前記第2辺と、前記第1辺および前記第2辺のそれぞれと交差する第3辺と、前記第3辺の反対側に位置し、かつ、前記第1辺および前記第2辺のそれぞれと交差する第4辺と、を有する四角形から成り、
前記第1半導体デバイスと前記第3辺との間には、第2半導体デバイスが搭載され、
平面視において、前記第2半導体デバイスと前記第3辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔より小さく、
前記配線基板は
前記第1絶縁膜に形成され、かつ、前記第1半導体デバイスと前記第1辺との間に形成された第1ダム部と、
前記第1絶縁膜に形成され、かつ、前記第2半導体デバイスと前記第3辺との間に形成された第2ダム部と、
を有する、半導体装置。 - 請求項1において、
前記第1面の平面形状は、前記第1辺と、前記第2辺と、前記第1辺および前記第2辺のそれぞれと交差する第3辺と、前記第3辺の反対側に位置し、かつ、前記第1辺および前記第2辺のそれぞれと交差する第4辺と、を有する四角形から成り、
前記第1半導体デバイスと前記第3辺との間には、第2半導体デバイスが搭載され、
平面視において、前記第2半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔より小さく、
前記配線基板は、
前記第1絶縁膜に形成され、かつ、前記第1半導体デバイスと前記第1辺との間に形成された第1ダム部と、
前記第1絶縁膜に形成され、かつ、前記第2半導体デバイスと前記第1辺との間に形成された第2ダム部と、
を有する、半導体装置。 - 請求項13において、
前記第1ダム部と前記第2ダム部とは繋がっている、半導体装置。 - 請求項1において、
配線基板の前記第1面上には、前記第1半導体デバイスの全体を覆っている第1部材が配置され、
前記第1面のうち、前記ダム部と前記第1辺との間に位置する領域には、前記第1部材を支持する支持部が接着されている、半導体装置。 - 第1面、前記第1面に形成された第1絶縁膜、前記第1絶縁膜上に形成された第2絶縁膜、および前記第2絶縁膜に形成されたダム部を有する配線基板と、
前記配線基板の前記第1面上に搭載された第1半導体デバイスと、
前記第1絶縁膜と前記第1半導体デバイスとの間に位置する第1樹脂と、
を含み、
前記第1面は、第1辺と、前記第1辺の反対側に位置する第2辺と、を有し、
前記第1半導体デバイスと前記第1辺との間隔は、前記第1半導体デバイスと前記第2辺との間隔より小さく、
前記ダム部は、前記第1半導体デバイスと前記第1辺との間に形成され、かつ、前記第1半導体デバイスと前記第2辺との間には形成されていない、半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US10586716B2 (en) * | 2017-06-09 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
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CN106469708A (zh) | 2017-03-01 |
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