TWI325626B - Method for packaging a semiconductor device - Google Patents

Method for packaging a semiconductor device Download PDF

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Publication number
TWI325626B
TWI325626B TW095142507A TW95142507A TWI325626B TW I325626 B TWI325626 B TW I325626B TW 095142507 A TW095142507 A TW 095142507A TW 95142507 A TW95142507 A TW 95142507A TW I325626 B TWI325626 B TW I325626B
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Taiwan
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conductive
stackable
contacts
base substrate
semiconductor device
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TW095142507A
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English (en)
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TW200735325A (en
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Viswanadam Gautham
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Freescale Semiconductor Inc
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Publication of TW200735325A publication Critical patent/TW200735325A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

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1325626 九、發明說明·· 【發明所屬之技術領域】 且更明確地說， 本發明一般係關於半導體裝置之封裝 係關於一種形成一堆疊封裝的方法。 f先前技術】 配。電子裝置的精密性’需要於軔 女於較小的封裝中提供更多 的功此。已經有人開發出堆疊戎曰 飞日日粒與堆疊式封裝三維 (3D)封裝，以符合此需求。一般夾卞认見 • L 奴來說，堆疊式晶粒封裝係 藉由彼此堆疊多個晶片而形成。— &曰μ 1 % 取 堆疊式晶粒封裝中的該 #日日片可藉由焊線連接或覆 復日日連接而破電耦合。另一方 面’堆疊式封裝則係藉由姑士祕 〆 糟由彼此堆疊多個封裝而形成，其中 母個封裝均包含單一晶片。 、 不疊式晶粒封裝之形成卻有數項問題。舉例來 :;、= ?有焊：連接的堆疊式封裝時，上層晶㈣ ’等焊绩：曰曰片為且，其相差數額必須足以提供用於製造 該專烊線連接的面積。據 ^ ^ _ 母個連續上層晶片的黏著 面積較佳的係越來越小， 旦 而限制了可被堆疊的封裝數 堆疊式封二:ί封裝通常並非以陣列(ΜΑΡ)格式來處理； 並且：會二？係利用液態封膠或中央閘極鑄模來處理， 並且僅會於分離之後才進行 造循環時間來形成堆疊式封F :據此’便需要較長的製 聯的复它門勺人 ，裝。和堆疊式封裝之形成相關 能是^正_ rs’難以在進行堆疊之前確保—晶粒的功 且目同數量的晶粒堆疊會具有較大的整體封裝 H6230.doc 厚度。 可靠堆疊式封裝的方法秘 …一 士刀跪 種製造可靠、低成本 ，本發明的目的便係提供 【發明内容】成本、且多功能之堆^封裝的方法。 以下結合附圖撻屮 杈出的#細說明係希望作為本 較佳具體實施例之巧昍 赞月之目刖 唯Η成而並非希望其代表實施本發明的 唯一形式。應瞭解，藉^ ^00 ^ ^ 由希望包含在本發明之精神及範痛 内的不同具體實施例，介叮—a上 及乾可 ， 11亦可貫現相同或等效功能。 為達上面討論及盆0 半導體穿… 與優點’本發明提供-種封裝 " 法。該方法包含下面步驟：於一基底芙拓 中形成複數個穿透孔； 、^ 以及於該基底基板的第一側上沉積 電材#肖以形成―導電h該導電材料會填充該複 穿透孔。料電層會被圖案化絲刻，以便形成複數 條互連線路以及複數個觸點。於該複數個觸點上會形成複 數個導電支撐體。該等導電支撐體會穿過該複數個穿透孔 中數個個別穿透孔。 本發明還提供-種封裝半導體裝置的方法，其包含下面 步驟·於-基底基板中形成複數個穿透孔；於該基底基板 的第-側上沉積—導電材料，用以形成一導電g ;以及圖 案化且银刻該導電層’以便形成複數條互連線路以及複數 個觸點β該導電材料會至少部份填充該複數個穿透孔。於 *玄等觸點上會形成複數個導電支撐體。該等導電支撐體實 質上彼此平行，實質上垂直於該基底基板，且穿過該複數 116230.doc 1325626 個穿透孔中數個個別穿透孔。至少一半導體晶粒會被電輕 合至該等互連線路以及觸點。 本發明進一步提供一種封裝半導體裝置的方法，其包含 下面步驟.於一基底基板中形成複數個穿透孔，·於該基底 基板的第一側上沉積一導電材料，用以形成一導電層，其 中《玄導電材料會填充該等穿透孔；以及圖案化且飯刻該導 電層以便形成複數條互連線路以及複數個觸點。於該複 數個觸點上會形成複數個實質平行的導電支樓體。該等導 電支樓體實質上垂直於該基底基板，且穿過該複數個穿透 孔中數個個別穿透孔。本發明會對該等互連線路、觸點、 以及導電支樓體套用一無電終端。複數個晶粒會被電麵合 至該等互連線路與觸點，並且會實施—鱗模作業以囊封該 晶粒’其中每—個導電支標體的至少一末端會被露出。依 此方式便會形成一第一可堆疊組件。本發明會形成_實質 上和該第-可堆疊組件雷同的第二可堆疊組件。藉由將該 第二可堆疊組件堆疊於該第_可堆疊組件上便會形成一堆 疊式組件。該等第一與第二可堆疊組件中其中一者會藉由 該等導電支禮體被W合至另—者。接著該堆疊式組件會 被切割或分離成複數個堆疊式封裝。 【實施方式】 圖1至8為根據本發明'~~且體音尬A丨 ，、髖貫施例之一種用於封裝半導 體裝置的方法。現在參考圖i中顯示的係一基底基板 10’其厚度至少約_耳。雖然於本特殊範例中有指定 基底基板10的厚度，不過應該瞭解的係，本發明並不僅限 I16230.doc 1325626 於該基底基板蘭該厚度。如熟f本技術者所知者，該基 底基板1G可由-聚醯亞胺（PI)膠帶或是特定其它非導電材 料所製成。 現在參考圖2’圖巾顯示出於該基底基板iq巾形成複數 個穿透孔12。該等穿透孔12可藉由鑽#或熟f本技術的人 士已知的特$其它合宜方法來形心料穿透孔12的尺寸 :圍介於約2〇〇Um至約600 um之間，且該等穿透孔以係被 設置或定位在每片基板1〇的周圍處。 圖3所示的係一導電材料14，舉例來說，被沉積在基底 基板10之第一側16上的銅，用以形成一導電層18。從圖中 可以看出’導電材料14會填充該等穿透孔12。基底基板ι〇 的第二側20較佳的係會於導電材料14的沉積期間受到遮 蔽。於此特殊範例中’該導電層18的厚度約5微米（㈣）。 不過，應該瞭解的係，本發明並不僅限於此導電層18的厚 度。
現在參考圖4，該導電層18會被圖案化且蝕刻，以便形 成複數條互連線路以及複數個觸點22。如圖中所示，於該 等觸點22上會形成複數個導電支撐體24,每一個導電支撐 體24均穿過該等穿透孔12中數個個別穿透孔12。該等導電 支揮體24實質上彼此平行且實質上垂直於該基底基板 «亥等導電支撐體24係由一導電材料（例如銅）所形成，且 可藉由一附加製程（例如電鍍）來形成。於此特殊範例中， 每一個導電支撐體24的寬度均約為200 。不過，應該瞭 解的係，本發明並不僅限於該導電支撐體24的寬度，或是 116230.doc 1325626 用於形成該等導電支撐體24所使用的材料類型或方法。 δ亥等互連線路與觸點22會使用本技術中已知的標準微麥 技術（例如光蝕刻）來進行圖案化與蝕刻。於該等觸點U上 形成該等導電支撐體24之前，會先使用一光阻遮罩來對該 等互連線路進行遮罩處理。此等光阻遮罩係本技術中已知 者。而後’該光阻遮罩便會從該等互連線路中被移除。 於一具體實施例中’會對該等互連線路、該等觸點22、 φ 以及該等導電支撐體24套用一無電終端，以防止氧化。 鎳、金、或是鎳金合金均可用於該無電終端中。不過，應 該瞭解的係，本發明並不僅限於該無電終端中所使用之金 屬或金屬合金類型。 圖5顯示出被電耦合至該基底基板1〇的至少一晶粒％。 晶粒26可能係一處理器，例如數位信號處理器（Dsp广一 特殊功能的電路，例如記憶體位址產生器；或是實施任何 /、匕類！的功尨。再者，晶粒26未限於特定技術（例如 籲 CMOS)或由任何特定晶圓技術衍生而來。另外，熟習本技 術的人士將會瞭解，本發明亦能涵蓋各種晶粒尺寸。典型 的範例A尺寸約7 mm乘7 mm的邏輯晶粒。雖然圖5僅顯 示三（3)個曰曰曰粒，不過，應該瞭解的係'，其實可於—基板上 附著更多或較少的晶粒，端視基板的尺寸、晶粒的尺寸、 以及該等最終裝置的必要功能而定。於此特殊範例中，該 等曰曰粒26曰透過複數個覆晶凸塊叫皮鶴合至該等基板焊接 觸點22。不過，應該瞭解的係，本發明並不僅限於覆晶應 用於替代的具體貫施例中，舉例來說，晶粒％亦可透過 116230.doc ozo 輝線被電竊合至該等基板焊接觸點22(參見圖7)β 導電支撐體24的目的係在埯孱—· 隹堆邊式封裝之間達成電連接的 目的。從圖5中可以看出，备一 ^母個導電支撐體24的高度均 和晶粒26的高度以及最終封梦 聚的间度有關。倘若晶粒係利 用凸塊28被麵合至該等觸點”的話，那麼，該等導電支標 體24的高度必須至少等於晶粒㈣高度加上覆晶凸㈣的 向度加上基板10的高度。雖然圖5顯示出，該等導電支撑 體24係延伸在晶粒26的頂端卜 耵員蚝上，不過，該等導電支撐體24 亦可與晶粒26的頂端齊平。倘若晶粒％係利用電線（參見 下文所述圖7中的電線46)被輕合至該等觸點22的話，那 麼’該專導電支揮體的高产插庙兮叾丨沾上 _ 门戾便應该延伸在晶粒26的頂端上 略高於該等電線迴路之弇译步 之间度處。於一示範具體實施例中， 對一高度約為200 μηι的晶物％ B古立^ μ ^日日拉26且鬲度約為100 μιη的覆晶凸 塊28來說’該等導電支禮體Μ的高度至少約為·㈣。 現在參考圖6，晶粒26會被一囊封材料％囊封，以便形 成圖中所示的第一可堆最 隹且、，且件32。本發明會實施一鑄模作 業(例如包覆鑄模)來囊封晶粒26，較佳的係、，讓每一導電 支撐體24的兩末端34保捭瞌· 番Α上丄丄 保得曝路。囊封材料30可能包括已知 的市售鑄模材料，例如朔跟―、塔# & 〗如塑膠或環氧樹脂。包覆鑄模無需用 到底膠填充製程，因而 J降低處理成本。省掉底膠填充還 可將封裝等級於260°C虛摆显s、H尸> 處提昇至濕氣敏感等級1 (MSL 1)。 現在參考圖7，—第—可堆疊組件4〇會被堆疊且被電耦 合至一第二可堆疊組件42上’用以形成-堆疊式組件44。 為闡述本發明之可堆疊組件的各種具體實施例，第一可堆 116230.doc 1325626 疊組件40具有利用複數個覆晶凸塊28被附著至複數個觸點 22的複數個晶粒26，而該等導電支撐體以則具有和該等晶 粒26之頂部表面齊平的頂端。第二可堆疊組件仏具有被附 著基板H)且透過複數條電線46被電耦合至該等觸點22的複 數個晶粒45’而導電支標體48則延伸在該等晶粒45之頂部 表面上方。熟習本技術者應該瞭解的係，該等可堆疊植件 40與42可利用相同的製程來形成（舉例來說，兩者均具有 覆晶附著晶粒）且具有相同的維度。 於此特殊範例中，該等第—與第二可堆疊組件_42會 對齊’俾使第-可堆疊組件侧導電支㈣24會對齊第二 可堆疊組件42的導電支禮體48，且該等導電支稽體24與48 會利用焊球50相互電連接，從而該等第一與第二可堆疊組 件40與42亦會利用焊球5〇相互電連接。該等焊球5〇可利用 已知的焊球附著製程被固至該等第—與第二可堆疊址件 4〇與42。不過，應該瞭解的係，本發明並不僅限於此堆疊 方法。舉例來說’亦可運用其它的堆疊方法，例如，焊膏 印刷與回焊4向異性的導電膜以及聚合物導電膏。於替 代具體實施例中，可於堆疊式組件44的選定部份上沉積由 導電材料(例如銅)製成的-第二導電層，且可將複數個離 散被動裝置附著至該第二導電層。雖然本具體實施例中僅 閣述兩個可堆疊組件4〇與42，不過，應該瞭解的係，根據 本發明，可將多個可堆疊組件以陣列(ΜΑρ)格 裝於另一者的頂端上。 Λ Ί 圖8顯示出由兩個可堆疊封裝62所構成的一堆疊式组件 H6230.doc 1325626 6〇。該等可堆疊封裝62會被形成—可堆疊封裝陣列的一部 份^堆疊、然後該堆疊式陣列便會被分離或切割，用以形 成该堆疊式組件60。該堆疊式組件6〇可被直接附著在一基 板上，例如以表面點著技術（SMT)來進行。，因為每一個堆 疊式組件60均包含複數個晶粒26，所以便可於單晶粒覆蓋 區内達到增加功能的目的。 本發明還提供-可堆疊組件’其包括：—基底基板，其 中會形成複數個穿透孔；於該基底 你φ低丞扳的至少第一側上形 成一導電材料，其中該導·雷jy·斗=, 也、 導電材#會至少部份填充該複數個 、透孔且會被圖案化與姓刻層’以形成複數條互連線路與 複數個觸點；以及形成於該複數個觸點上的複數個導電支 揮體，其中該複數個導電支樓體會穿過該等穿透孔中數個 個別穿透孔❶該可堆疊組件 進步包含一半導體積體 電路（1C)，其會透過覆晶 尾坪綠或直接晶片附著方 式被附著至該等觸點；且還 疋進步包含一覆盍該1(:與該等 觸點的囊封體，而較佳的係，命 ，、路出該等導電支撐體的該等 末端。接著，便可將額外的 1璀噓組件堆疊在另一者的頂 端上，其中該等可堆疊組件合蕤 干a猎由该專導電支撐體被電耦 合0 從前面的討論中便可以明白，本發明提供一種封裝半導 體裝置的方法，苴且有僖认π衣干守 八/、有優於既有製程的優點。舉 根據本發明之半導體裝置封 衣厂以map格式來進行，從而 達到尚產量的目的。此外 根據本發明亦可使用已知的良 好晶粒來封裝半導體裝置， U為5玄晶粒可於進行凸塊作業 116230.doc 之後且在進行囊封之前被測試。 故、s 亦可藉由直接探測該 4導電支撐體的該等露出的末端來對 個封裝進行最終 測试，而不會破壞該晶粒。再者，可被堆叠的封裝數量並 無任何關，因為本發明並未規定上層封裝必須小於下層 封裝。另夕卜，利用本發明還可製造很薄的可堆疊植件。 利用本發明可達到低製造成本的目的，因為^用到單層 基底基板’且不需要底膠填充，並且可利用既有設備與製 程來施行本發^本發明還可達到大量功能的目的，因為 該等互連線路係被放置在該基底基板上，允許於該堆疊中 具有f個功能性矽晶粒。本發明可達成的其它優點還包 含：高密度的輸入與輸出⑽堆4，因為該基底基板上的 精細線選路會擴充成超高密度封裝；可靠度非常高，因為 矽對印刷電路板（PCB)的熱失配已經消除’且所用的焊料 與基底基板類型具有相當高的彈性。 因此，可以明白的係，根據本發明已經提供一種封裝半 導體裝置的方法，其完全符合先前所提的優點。雖然本發 明已參考其特定具體實施例加以解說及闡明，但是並不希 望本發明限於該等闡明性具體實施例。熟習此項技術者應 明白’可進行修改與變更而不背離本發明之精神。舉例來 說’該等導電層與導電支撐體並不僅限於銅，確切地說， 可由本技術中所使用之任何導電材料所製成。如先前提出 的’本發明並不僅限於該基底基板、該導電層、該等導電 支撐體的維度’或是晶粒尺寸。裝置配置亦不僅限於覆晶 與焊線應用。應該瞭解的係，本發明可應用於系統級封裝 116230.doc 13 1325626 (SIP)技術中。此外，本發明並*限於本文所說明或解說的 半導體晶粒類型°所以，本發明希望涵蓋落在隨附申請專 利範圍之範疇内的所有此等變更與修正。
【圖式簡單說明】 當結合附圖閱讀時 實施例的詳細說明。 明並未限定在附圖内 件0 ，將會更佳瞭解本發明之一較佳具體 本發明已藉由範例予以闡明，但本發 ，其中相同的元件符號代表相同的元 圖1至6係放大剖面圖， 的一種形成複數個可堆疊 圖7係放大剖面圖，其 一種堆疊複數個半導體裝 其闡明根據本發明一具體實施例 半導體裝置的方法； 闡明根據本發明一具體實施例的 置的方法；以及 圖8為根據本發明一 的放大剖面圖。 八體實知例之一堆疊式半導體裝置 【主要元件符號說明】
10 基底基板 12 穿透孔 14 導電材料 16 基底基板10的第—彻J 18 導電層 20 基底基板1 0的第二側 22 (基板焊接）觸點 24 導電支撐體 26 晶粒 116230.doc 1325626 28 覆晶凸塊 30 囊封材料 32 第一可堆疊組件 34 導電支撐體24的末端 40 第一可堆疊組件 42 第二可堆疊組件 44 堆疊式組件 45 晶粒 46 電線 48 導電支撐體 50 焊球 60 堆疊式組件 62 可堆疊封裝 116230.doc . 15 -

Claims (1)

1325626第〇951425〇7號專利申請案 V Ί 崎正脊換買I 該方法包括 中文t請專利範圍替換本(98年10月） 十、申請專利範圍： 1. 一種用以封裝一可堆疊半導體裝置的方法， 下面的步驟： 於一基底基板t形成複數個穿透孔； 於該基底基板的至少一第一側上沉積一導電材料，用 、形成導電層，其中δ亥導電材料會至少部份填充該複 數個穿透孔； 圖案化且姓刻該導電層，以便形成複數條互連線路以 及複數個觸點； 於該複數個觸點上形成複數個導電支撐體，其中該複 數個導電支撐體以—第—向下的方向穿過該複數個穿透 孔中數個個別穿透孔，且以一第二向上的方向在該等穿 透孔上方穿過至一遠高於該導電層高度之預定高度； 將至少-晶粒電耦合至該複數個觸點，其中該 撑體同時穿過該晶粒之上方及下方；以及 實施-鑄模作業’用以囊封該晶粒，其中會露出每一 個導電支撐體的至少一末端。 2·如清求項1之封裝一可堆疊半導體裝置的方法，其進一 :包括遮蔽該基底基板的一第二側，用以阻隔該導電材 3. 如-月求項1之封裝—可堆疊半導體裝置的方 基底基板包含—聚醯亞胺膠帶。 4. 如請求項1之封裝_ 導電材料為銅。 可堆疊半導體裝置的方 法，其中該 法，其中該 116230-981007.doc 嶸正替換; 5. 如請求項4之封裝一可堆疊半導體裝置的方法，里中该 複數個導電支樓體係由銅所製成。 '、 6. 如明求項1之封裝一可堆疊半導體裝置的方法，其進〆 步匕括對該複數條互連線路 '該複數個觸點、以及該複 數個導電支樓體套用—無電終端。 7. 如請求項6之封裂一可堆疊半導體裝置的方法，其中该 無電終端包括鎳、金、以及鎳金合金中其中—者。 8. 如明求項1之封裝一可堆疊半導體裝置的方法，其中香 個導電支擇體的寬度約200微米。 9. 如明求項8之封裝一可堆疊半導體裝置的方法，其中该 複數個導電支樓體實質上彼此平行。 ’、 10. 如清求項9之封裝一可堆疊半導體裝置的方法，其个该 複數個導電支揮體實質上垂直於該基底基板。、 11·如晴求項1之封裝_可堆疊半導體裝置的方法，其中该 晶粒會透過料被電柄合至基板焊接觸點。 12.如凊求項1之封裝一可堆疊半導體裝置的方法，其中该 曰曰粒會透覆晶凸塊被電耗合至該等基板焊接觸點。 13·如請求項1之封裝一可堆疊半導體裝置的方法，其^有 複數個aa粒被電_合至該等互連線路與觸點且係被囊封 ;^、上從而會形成一第一可堆疊組件，該方法進〆少 包括： 將第一可堆豐組件堆疊於該第一可堆疊組件上，其 中°玄等第與第二可堆疊組件中其中一者會被電耦合至 另一者，以便形成一堆疊式組件；以及 116230-98 丨 007.doc 58年1m正替換頁 將該堆疊式組件分離成複數個堆疊式封裝。 14·:=項13之封裝-可堆疊半導體裝置的方法，其進-二於該堆疊式組件上沉積一第二導電層，一 離散被動式裝置附著於該第二導電層上。 15·如請求項13之封裝—可堆疊半導體裝置的方法，其中可 ，用下面其中—者來堆疊該複數個可堆疊組件：谭球附 者、焊W卩刷與㈣、各向錢的導電m聚 電膏。 16.-種用以封裝—半導體裝置的方法#包括下面的步 驟： 於一基底基板中形成複數個穿透孔； 於該基底基板的至少一第一侧上沉積一導電材料，用 以形成-導電層’其中料電材料會至少部份填充該複 數個穿透孔； 圖案化且餘刻該導電層，以便形成複數條互連線路以 及複數個觸點； 於該複數個觸點上形成複數個實質平行的導電支撐 體，其中該複數個導電支#體實f上垂直於該基底基板 且以一第一向下的方向穿過該複數個穿透孔中數個個別 穿透孔，且以一第二向上的方向在該等穿透孔上方穿過 至一遠高於該導電層高度之預定高度；以及 將至少一晶粒電耦合至該等互連線路與觸點，其中該 導電支撐體同時穿過該晶粒之上方及下方；以及 囊封該複數個晶粒及該導電層，其中會露出該導電支 116230-981007.doc
樓體的至少一末端，藉此形成一第一可堆疊組件。 17.如請求項16之封裝—可堆疊半導電裝置的方法，里中有 複數個晶粒被_合至料互連線路與觸點，該方法進 一步包括： 形成一實質上和該第一可堆疊組件雷同的第二可堆疊 組件； 藉由將該第二可堆疊組件堆疊於該第一可堆疊組件上 以便形成-堆疊式組件，其中該等第一與第二可堆疊组 件中其中-者會藉由該等導電支樓體被電耗合至另一 者；以及 將該堆疊式組件分離成複數個堆疊式封裝。 A -種用以封裝-半導體裝置的Μ，以括下面的步 驟· 於-基底基板中形成複數個穿透孔，其中該基底基板 包含一聚醢亞胺膠帶； 於該基底基板的至少一第一側上沉積一導電材料，用 乂形成導電層’其中該導電材料會至少部份填充該複 數個穿透孔； 圖案化且银刻該導電層，以便形成複數條互連線路以 及複數個觸點； 於該複數個觸點上形成複數個實質平行的導電支撐 體’其中該複數個導電支標體實質上垂直於該基底基板 且以一第一向下的方向穿過該複數個穿透孔中數個個別 穿透孔，且以一第二向上的方向在該等穿透孔上方穿過 116230-981007.doc -4- 1325626 至-遠高於該導電層高度之預定高度；[_-- 對δ亥複數條互連線路、該複數個觸點、以及該複數個 導電支撐體套用一無電終端； 將複數個晶粒電輕合至該等互連線路與觸點，其令該 導電支撐體同時穿過該複數個晶粒之上方及下方； 貫施-鎮模作業’用以囊封該複數個晶粒，其中會露 出每-個導電支撑體的至少一末端，從而形成一第一可 堆疊組件；
形成一實質上和該第一可堆疊組件雷同的第二属 組件； ι 藉由將該第二可堆疊組件堆疊於該第一可堆疊組件 以便形成—堆疊式組件，其中該等第-與第二可堆疊; 件中其中一者會藉由該等導電支撐體被電耦合至 者，以及 將忒堆疊式組件分離成複數個堆疊式封裝。
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TW200735325A (en) 2007-09-16
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CN1983533A (zh) 2007-06-20
CN1983533B (zh) 2010-11-03
JP2007158331A (ja) 2007-06-21
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KR20070057038A (ko) 2007-06-04
KR101349985B1 (ko) 2014-01-13

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