CN1983533B - 用于封装半导体器件的方法 - Google Patents

用于封装半导体器件的方法 Download PDF

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CN1983533B
CN1983533B CN2006101630757A CN200610163075A CN1983533B CN 1983533 B CN1983533 B CN 1983533B CN 2006101630757 A CN2006101630757 A CN 2006101630757A CN 200610163075 A CN200610163075 A CN 200610163075A CN 1983533 B CN1983533 B CN 1983533B
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stack assemblies
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semiconductor device
encapsulate
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CN1983533A (zh
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维斯万纳达姆·高萨姆
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NXP USA Inc
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Abstract

一种用于封装半导体器件的方法包括在基础衬底(10)中形成通孔(12)并且在所述基础衬底(10)的第一面(16)上沉积导电材料(14)来形成导电层(18)使得所述导电材料(14)填入所述通孔(12)。所述导电层(18)被图案化并蚀刻以便形成互连轨迹和焊盘(22)。在所述焊盘(22)上形成导电支柱(24)使得所述导电支柱(24)延伸通过各自的通孔(12)。

Description

用于封装半导体器件的方法
技术领域
本发明总体上涉及半导体器件的封装，并且尤其涉及一种用于形成堆叠封装(stacked package)的方法。
背景技术
伴随电子设备变得复杂化，需要在较小的封装中实现较多的功能。堆叠小片和堆叠封装三维(3D)封装已经被开发出来用以满足此要求。典型情况下，通过将多个芯片相互堆叠来形成堆叠小片封装。堆叠小片封装中的芯片可以借助丝焊连接或倒装芯片连接来电耦合。另一方面，通过将多个封装相互堆叠来形成堆叠封装，其中每个封装包含单个芯片。
然而，形成堆叠小片封装存在多个问题。例如，当形成具有丝焊连接的堆叠封装时，通常上面的芯片最好小于下面的芯片一定量，以用于进行丝焊连接所要求的区域。因此，每个相继的上面芯片的安装区域最好逐渐变小，由此对可以堆叠的封装数目带来限制。
此外，通常并不依照阵列(MAP)格式来处理堆叠封装；通常使用圆顶封装(glob top encapsulation)或中心浇口制模来处理堆叠封装并且只在分离之后才进行堆叠。为此，要求较长的制造周期时间来形成堆叠封装。与形成堆叠封装相关联的其它问题包括在堆叠之前很难查明小片是否工作正常，以及对于相同数目的小片堆叠来说会带来较大的整体封装厚度。
考虑到上述情况，需要一种用于以低成本形成具有增加的功能的可靠的堆叠封装。因此，本发明的目的是提供一种用于制造可靠的、低成本、高功能的堆叠封装。
发明内容
为了实现上述目的和优点等，本发明提供了一种用于封装半导体器件的方法。所述方法包括步骤：在基础衬底中形成多个通孔并且在所述基础衬底的第一面上沉积导电材料以便形成导电层。导电材料填入多个通孔。导电层被图案化并蚀刻以便形成多个互连轨迹和多个焊盘(pad)。在多个焊盘上形成多个导电支柱(support)。导电支柱延伸到多个通孔中相应的通孔。
本发明还提供了一种用于封装半导体器件的方法，包括步骤：在基础衬底中形成多个通孔，在所述基础衬底的第一面上沉积导电材料以便形成导电层，并且图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘。导电材料至少部分填入所述多个通孔。在焊盘上形成多个导电支柱。所述导电支柱基本上彼此平行，基本上垂直于基础衬底，并且延伸到多个通孔中的相应通孔。至少一个半导体小片电耦合到所述互连轨迹和焊盘。
本发明进一步提供了一种用于封装半导体器件的方法，包括步骤：在基础衬底中形成多个通孔，在所述基础衬底的第一面上沉积导电材料以便形成导电层，其中所述导电材料填入所述通孔，并且图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘。在多个焊盘上形成多个基本上平行的导电支柱。所述导电支柱基本上垂直于基础衬底，并且延伸到多个通孔中相应的通孔。向互连轨迹、焊盘和导电支柱施加无电抛光(electroless finish)。多个小片电耦合到互连轨迹和焊盘，并且执行模制操作以便封装所述小片，其中露出每个导电支柱的至少一端。依照这种方式形成第一可堆叠组件。形成与第一可堆叠组件基本上类似的第二可堆叠组件。通过在第一可堆叠组件上堆叠第二可堆叠组件来形成堆叠组件。第一和第二可堆叠组件借助导电支柱相互电耦合。然后堆叠组件被切割或分离为多个堆叠封装。
附图说明
当结合附图阅读时可以更好地理解本发明优选实施例的以下详细说明。本发明以举例形式来说明并且不受附图的限制，其中相似的附图标记表示类似的部件。
图1到6是图示用于依照本发明实施例形成多个可堆叠半导体器件的方法的放大剖面图；
图7是图示用于依照本发明实施例堆叠多个半导体器件的方法的放大剖视图；和
图8是依照本发明实施例的堆叠半导体器件的放大剖视图。
具体实施方式
下面结合附图所阐明的详细说明意在为本发明优选实施例的描述，而并不意在表示可以实施本发明的唯一形式。应当理解，相同的或等同的功能可以由本发明的精神和范围内所包含的不同实施例来实现。
图1-8图示了用于依照本发明实施例来封装半导体器件的方法。现在参照图1，示出了厚度至少大约为1.0mil的基础衬底10。尽管在此特定的例子中指定了基础衬底10的厚度，然而应当理解，本发明并不受所述基础衬底10厚度的限制。如本领域技术人员所知，基础衬底10可以由聚酰亚胺(Polyimide PI)条带或其它非导电材料制成。
现在参照图2，示出在基础衬底10中形成多个通孔12。可以通过钻孔或本领域技术人员所知的其它适当方法来形成通孔12。通孔12的尺寸从大约200μm到大约600μm，并且所述通孔12位于或处于每个衬底10的周边。
图3示出了导电材料14，例如沉积在基础衬底10的第一面16上以用于形成导电层18的铜。如同所见，通孔12填充有导电材料14。在沉积导电材料14期间，优选地屏蔽基础衬底10的第二面20。在此特定的例子中，导电层18大约有5微米(μm)厚。然而应当理解，本发明并不受导电层18厚度的限制。
现在参照图4，导电层18被图案化并蚀刻以便形成多个互连轨迹和多个焊盘22。如同所示，在焊盘22上形成多个导电支柱24，每个导电支柱24延伸通过相应的通孔12。导电支柱24基本上彼此平行并且基本上垂直于基础衬底10。
导电支柱24由诸如铜之类的导电材料形成，并且可以通过诸如电镀之类的附加工艺形成。在此特定的例子中，每个导电支柱24具有大约200μm的宽度。然而应当理解，本发明并不受导电支柱24的宽度或材料类型或者用于形成所述导电支柱24的方法的限制。
使用在本领域中已知的标准平版印刷技术(例如光刻)来图案化并蚀刻互连轨迹和焊盘22。在焊盘22上形成导电支柱24之前使用抗蚀剂掩模来遮盖互连轨迹。这种抗蚀剂掩模在本领域中是已知的。此后从互连轨迹移除所述抗蚀剂掩模。
在一个实施例中，向互连轨迹、焊盘22和导电支柱24施加无电抛光以便防止氧化作用。镍、金或镍金合金可以用于无电抛光。然而应当理解，本发明并不受用于无电抛光的金属或金属合金类型的限制。
图5示出了电耦合到基础衬底10的至少一个小片26。所述小片26可以是诸如数字信号处理器(DSP)之类的处理器、诸如存储器地址发生器之类的特定功能电路或执行任何其它类型的功能。此外，所述小片26不局限于诸如CMOS之类的特定技术，或根据任何特定的晶片技术得出。此外，本领域技术人员可以理解，本发明可以适应各种小片尺寸。典型例子是具有大约为7mm×7mm的尺寸的逻辑小片。尽管图5只示出了三个小片，然而应当理解，根据衬底尺寸、小片的尺寸和所产生器件所要求的功能，可以把更多或更少的小片附着到所述衬底。在此特定的例子中，小片26经由多个倒装芯片凸点28耦合到衬底接合焊盘(bonding pad)22。然而应当理解，本发明不局限于倒装芯片应用。在替换实施例中，小片26例如可以经由丝焊电耦合到衬底接合焊盘22(参见图7)。
导电支柱24的目的是实现堆叠封装之间的电连接。如从图5中可以看出，每个导电支柱24的高度与小片26的高度和最终封装的高度相关。如果小片利用倒装芯片凸点28耦合到所述焊盘22，那么导电支柱24必须具有至少等于小片26的高度加上所述倒装芯片凸点28的高度再加上衬底10的高度的高度。尽管图5示出了导电支柱24延伸到小片26的顶部之外，然而导电支柱24可以与所述小片26的顶部齐平。如果小片26利用线路(参见图7中的线路27，下面将要描述)耦合到焊盘22，那么导电支柱的高度应当延伸到所述小片26的顶部之外略微超出线环的高度。在一个示例性实施例中，对于具有高度大约为200μm的小片26以及具有高度大约为100μm的倒装芯片凸点28来说，导电支柱24具有至少大约400μm的高度。
现在参照图6，如同所示，利用密封剂材料30来封装小片26以便形成第一可堆叠组件32。执行诸如过模制(over moulding)之类的模制操作来封装小片26，最好使每个导电支柱24的两端34暴露出来。密封剂材料30可以包括公知的可买到的模制材料，诸如塑料或环氧树脂。过模制消除了对未充满(under fill)工艺的需要，由此降低了处理成本。未充满的消除还在260℃把封装级别增加到湿度敏感性级别1(Moisture Sensitivity Level1 MSL1)。
现在参照图7，第一可堆叠组件40被堆叠在第二可堆叠组件42上并与其电耦合以便形成堆叠组件44。为了图示本发明的可堆叠组件的各种实施例，第一可堆叠组件40具有利用倒装芯片凸点28附着于焊盘22的小片26，并且导电支柱24具有与所述小片26的顶表面齐平的顶端。第二可堆叠组件42具有小片45和导电支柱48，所述小片45附着于所述衬底10并且经由线路46与焊盘22电耦合，并且所述导电支柱48延伸到所述小片45的顶表面之外。本领域技术人员应当理解，可以使用相同的工艺来形成可堆叠组件40和42(例如，都具有倒装芯片附着的小片)并且它们都具有相同的维数。
在此特定的例子中，第一和第二可堆叠组件40和42被对准，使得第一可堆叠组件40的导电支柱24与第二可堆叠组件42的导电支柱48对准，并且所述导电支柱24和48以及因而所述第一和第二可堆叠组件40和42与焊球50电连接。可以使用已知的焊球附着工艺来把焊球50固定到第一和第二可堆叠组件40和42。不过应当理解，本发明不局限于这种堆叠方法。也可以使用其它堆叠方法，诸如粘贴膏印刷和回流；非均匀性导电薄膜和聚合物导线粘贴。在替换实施例中，可以把由导电材料(例如铜)制成的第二导电层沉积在堆叠组件44的选择性部分上并且可以把分立的无源器件附着到所述第二导电层。尽管在此实施例中只图示了两个可堆叠组件40和42，然而应当理解，依照本发明可以把依照阵列(MAP)格式的多个可堆叠组件组装为一个在另一个上面。
图8示出了由两个可堆叠封装62形成的堆叠组件60。可堆叠封装62使用作为可堆叠封装阵列的一部分来形成、堆叠，继而堆叠阵列被分离或切割以便形成堆叠组件60。堆叠组件60可以被直接附着到诸如表面安装技术(Surface Mount Technology SMT)中的板衬底上。因为每个堆叠组件60包括多个小片26，所以在单个小片足迹(footprint)区域内实现了增加的功能。
本发明还提供了一种可堆叠组件，包括其中形成有多个通孔的基础衬底；至少在所述基础衬底的第一面上形成的导电材料，用于形成导电层，其中所述导电材料至少部分地填充所述多个通孔并且作为图案化和蚀刻层以用于形成多个互连轨迹和多个焊盘；和在所述多个焊盘上形成的多个导电支柱，其中所述多个导电支柱延伸通过多个通孔中相应的通孔。可堆叠组件可以进一步包括半导体集成电路(IC)，所述半导体集成电路诸如经由倒装芯片凸点、丝焊或直接芯片附着而附着于焊盘，还包括用于覆盖所述IC和焊盘的密封剂，同时优选使导电支柱的端部露出。然后，可以堆叠附加的可堆叠组件，一个在另一个上面，其中通过导电支柱来电耦合所述可堆叠组件。
如从上述显然可以看出，本发明提供了一种用于封装半导体器件的方法，所述方法与现有工艺相比更有益处。作为一个例子，可以依照MAP格式来进行依照本发明的半导体器件的封装，由此实现了高生产量。另外，依照本发明，因为可以在凸点形成之后并且在封装之前测试小片，所以可以把已知良好的小片用于封装半导体器件。另外，通过直接地探测导电支柱的暴露端还可以在不损坏小片的情况下实施对每个封装的最后测试。此外，由于在本发明中不要求上面的封装一定小于下面的封装，所以不会限制可以堆叠的封装数目。此外，利用本发明可以制作薄的可堆叠组件。
由于只使用单层基础衬底，不要求未充满，并且可以使用现有设备和工艺来实现本发明，所以利用本发明可以实现低制造成本。因为互连轨迹位于基础衬底上，允许多功能硅小片处于堆叠中，所以本发明还实现了高功能。利用本发明可实现的其它优点包括高密度的输入和输出(IO)堆叠因为在基础衬底上迂回的细线延伸到非常高密度的封装，由于消除了硅对印刷电路板(PCB)的热失配而增加了可靠性，以及所使用的焊料和基础衬底类型的灵活性。
因而，依照本发明很明显提供了一种用于封装半导体器件的方法，其完全满足先前所阐述的优点。尽管已经参考其具体实施例描述并图示了本发明，然而并不意在将本发明限于这些说明性实施例。本领域技术人员认识到在不脱离本发明精神的情况下可以进行修改和变化。例如，导电层和导电支柱不局限于铜，而是可以由在本领域中所使用的任何导电材料制成。如先前所阐述，本发明不受基础衬底维数、导电层、导电支柱或小片尺寸的限制。器件配置也不限于倒装芯片和丝焊应用。应当理解，本发明可以应用于封装中的系统(System InPackage SIP)技术。此外，本发明不局限于这里所描述或图示的那些半导体小片类型。因此，本发明意在包含属于所附权利要求范围内的所有这些变化和修改。

Claims (18)

1.一种用于封装可堆叠半导体器件的方法，包括步骤：
在基础衬底中形成多个通孔；
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层，其中所述导电材料至少部分填充所述多个通孔；
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘；
在所述多个焊盘上形成多个导电支柱，其中所述多个导电支柱以向下的第一方向延伸通过所述多个通孔中的相应通孔并以向上的第二方向在通孔上方延伸到远远大于导电层高度的预定高度；
将至少一个小片电耦合到所述多个焊盘，其中，所述导电支柱延伸到高于和低于所述小片；以及
执行用于封装所述小片的模制操作，其中露出每个导电支柱的至少一端。
2.如权利要求1所述的用于封装可堆叠半导体器件的方法，还包括把所述基础衬底的第二面与所述导电材料相屏蔽。
3.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中所述基础衬底包括聚酰亚胺条带。
4.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中所述导电材料为铜。
5.如权利要求4所述的用于封装可堆叠半导体器件的方法，其中所述多个导电支柱用铜制成。
6.如权利要求1所述的用于封装可堆叠半导体器件的方法，还包括向所述多个互连轨迹、多个焊盘和多个导电支柱施加无电抛光。
7.如权利要求6所述的用于封装可堆叠半导体器件的方法，其中所述无电抛光包括镍、金和镍金合金之一。
8.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中每个导电支柱具有大约200微米的宽度。
9.如权利要求8所述的用于封装可堆叠半导体器件的方法，其中所述多个导电支柱基本上彼此平行。
10.如权利要求9所述的用于封装可堆叠半导体器件的方法，其中所述多个导电支柱基本上垂直于所述基础衬底。
11.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中所述小片经由丝焊电耦合到衬底接合焊盘。
12.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中所述小片经由倒装芯片凸点电耦合到衬底接合焊盘。
13.如权利要求1所述的用于封装可堆叠半导体器件的方法，其中多个小片被电耦合到所述互连轨迹和焊盘并且封装在其上，由此形成第一可堆叠组件，所述方法还包括：
在所述第一可堆叠组件上堆叠第二可堆叠组件，其中所述第一和第二可堆叠组件彼此电耦合以便形成堆叠组件；以及
把所述堆叠组件分离为多个堆叠封装。
14.如权利要求13所述的用于封装可堆叠半导体器件的方法，还包括在所述堆叠组件上沉积第二导电层，并且在所述第二导电层上附着分立的无源器件。
15.如权利要求13所述的用于封装可堆叠半导体器件的方法，其中使用焊球附着、粘贴膏印刷和回流、非均匀性导电薄膜和聚合物导体粘贴之一来堆叠多个可堆叠组件。
16.一种用于封装半导体器件的方法，包括步骤：
在基础衬底中形成多个通孔；
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层，其中所述导电材料至少部分填充所述多个通孔；
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘；
在所述多个焊盘上形成多个基本上平行的导电支柱，其中所述多个导电支柱基本上垂直于所述基础衬底，并且以向下的第一方向延伸通过多个通孔中相应的通孔并以向上的第二方向在通孔上方延伸到远远大于导电层高度的预定高度；
把至少一个小片电耦合到所述互连轨迹和焊盘，其中，所述导电支柱延伸到高于和低于所述小片；以及
封装所述多个小片和导电支柱，其中露出导电支柱的至少一端，由此形成第一可堆叠组件。
17.如权利要求16所述的用于封装可堆叠半导体器件的方法，其中多个小片被电耦合到所述互连轨迹和焊盘，所述方法还包括：
形成基本上类似于所述第一可堆叠组件的第二可堆叠组件；
通过在所述第一可堆叠组件上形成第二可堆叠组件来形成堆叠组件，其中所述第一和第二可堆叠组件通过所述导电支柱彼此电耦合；并且
把所述堆叠组件分离为多个堆叠封装。
18.一种用于封装半导体器件的方法，包括步骤：
在基础衬底中形成多个通孔，其中所述基础衬底包括聚酰亚胺条带；
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层，其中所述导电材料至少部分填充所述多个通孔；
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘；
在所述多个焊盘上形成多个基本上平行的导电支柱，其中所述多个导电支柱基本上垂直于所述基础衬底并且以向下的第一方向延伸通过多个通孔中相应的通孔并以向上的第二方向在通孔上方延伸到远远大于导电层高度的预定高度；
向所述多个互连轨迹、多个焊盘和多个导电支柱施加无电抛光；
把多个小片电耦合到所述互连轨迹和焊盘，其中，所述导电支柱延伸到高于和低于所述多个小片；
执行用于封装所述多个小片的模制操作，其中露出每个导电支柱的至少一端，由此形成第一可堆叠组件；
形成基本上类似于所述第一可堆叠组件的第二可堆叠组件；
通过在所述第一可堆叠组件上形成第二可堆叠组件来形成堆叠组件，其中所述第一和第二可堆叠组件通过所述导电支柱彼此电耦合；及
把所述堆叠组件分离为多个堆叠封装。
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