TW201911979A - 電路板以及封裝後晶片 - Google Patents

電路板以及封裝後晶片 Download PDF

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TW201911979A
TW201911979A TW106125479A TW106125479A TW201911979A TW 201911979 A TW201911979 A TW 201911979A TW 106125479 A TW106125479 A TW 106125479A TW 106125479 A TW106125479 A TW 106125479A TW 201911979 A TW201911979 A TW 201911979A
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Taiwan
Prior art keywords
pads
heat
heat dissipation
circuit board
wafer
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TW106125479A
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English (en)
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林宥緯
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晨星半導體股份有限公司
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Priority to TW106125479A priority Critical patent/TW201911979A/zh
Priority to US15/850,376 priority patent/US10559513B2/en
Publication of TW201911979A publication Critical patent/TW201911979A/zh
Priority to US16/725,511 priority patent/US11296006B2/en

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Abstract

本發明提供一種電路板，其包括彼此相對的一上表面以及一下表面、複數個散熱接墊以及複數個散熱導電墊。散熱接墊設置在上表面上，用以電連接散熱元件，其中散熱接墊彼此電性絕緣。散熱導電墊設置在下表面上，散熱導電墊彼此電性絕緣，且散熱導電墊分別電連接散熱接墊。

Description

電路板以及封裝後晶片
本發明係關於一種電路板以及封裝後晶片，尤指一種可透過電訊號測試散熱元件與電路板之間的電連接的電路板以及封裝後晶片。
隨著電子產品的演進與發展，電子產品在現今社會中已成為不可或缺的物品，其中晶片更是廣泛應用於電子產品中。在晶片的運作過程中，不可避免的會產生高熱而造成晶片溫度上升，因此為了避免晶片受到高溫而影響其運作，封裝後晶片中通常會設置例如散熱片。然而，若散熱元件的黏著狀況不佳，可能會導致所謂的天線效應，也就是說散熱元件黏著狀況不佳的一端，會接收外界的電磁訊號而干擾晶片運作，或是由此端發出電磁訊號而影響其他元件。
本發明之目的之一在於提供一種電路板與封裝後晶片，透過電路板中彼此絕緣的散熱走線分別連接複數個散熱接墊與複數個散熱導電墊，使具有黏著狀況不佳之散熱元件的封裝後晶片可被找出。
本發明之一實施例提供一種電路板，其包括彼此相對的一上表面以及一下表面、複數個散熱接墊以及複數個散熱導電墊。散熱接墊設置在上表面上，散熱接墊用以電連接散熱元件，其中散熱接墊彼此電性絕緣。散熱導電墊設置在下表面上，散熱導電墊彼此電性絕緣，且散熱導電墊分別電連接至散熱接墊。
本發明之另一實施例提供一種封裝後晶片，其包括電路板以及散熱元件。散熱元件黏著在電路板的散熱接墊上，散熱元件與散熱接墊電連接，且散熱接墊透過散熱元件彼此電連接。
為使熟悉本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明的精神下進行各種修飾與變更。另須注意的是，以下圖式均為簡化之示意圖式，而僅以示意方式說明本發明之基本構想，遂圖式中僅顯示與本發明有關之元件而非按照實際實施時之元件數目、形狀與尺寸繪製，其實際實施時各元件之型態、數量及比例可隨需求作變更，且元件布局型態可更為複雜。
第1圖繪示本發明一實施例之電路板之剖面示意圖。如第1圖所示，本實施例的電路板100包括彼此相對的上表面100a以及下表面100b、一電路層110、設置於電路板100的上表面100a上之複數個散熱接墊HBP與複數個晶片接墊CBP1、CBP2、以及設置於電路板100的下表面100b上之複數個散熱導電墊HP與複數個晶片導電墊CP1、CP2。
電路層110可包括一絕緣層112、複數條散熱走線TRH以及複數條晶片走線TRC1、TRC2。散熱走線TRH與晶片走線TRC1、TRC2設置在絕緣層112中，使得各散熱走線TRH與晶片走線TRC1、TRC2可透過絕緣層112分隔而使彼此電性絕緣。由於本領域熟知該項技藝者應知散熱走線TRH與晶片走線TRC1、TRC2可透過多層絕緣層以及多層導線層形成，並可透過絕緣層的開口將不同導電層的導線進行垂直方向的電連接，因此在此不多贅述。
散熱接墊HBP用以電連接散熱元件(例如散熱片)，散熱接墊HBP彼此電性絕緣，且各散熱接墊HBP均與晶片接墊CBP1、CBP2電性絕緣，亦即在電路板100上尚未設置有電子元件或散熱元件的情況下，各散熱接墊HBP不與其他散熱接墊HBP或任何晶片接墊CBP1、CBP2電連接。散熱接墊HBP可分別透過電路層110中的散熱走線TRH電連接至散熱導電墊HP，亦即在電路板100上未設置有電子元件或散熱元件的情況下，一個散熱接墊HBP僅透過一條散熱走線TRH與一個散熱導電墊HP電連接，而不與晶片導電墊CP1、CP2電連接。散熱導電墊HP彼此電性絕緣，且各散熱導電墊HP均與晶片導電墊CP1、CP2電性絕緣，亦即在電路板100上尚未設置有電子元件或散熱元件的情況下，各散熱導電墊HP不與其他導電墊HP或任何晶片導電墊CP1、CP2電連接。散熱導電墊HP用以電連接至外部的接地端。
晶片接墊CBP1、CBP2用以電連接電子元件(例如晶片)。晶片接墊CBP1可用以電連接至電子元件的接地端，並可透過電路層110中的晶片走線TRC1電連接至至少一晶片導電墊CP1，且不與散熱導電墊HP電連接。舉例而言，晶片接墊CBP1可電連接至兩個晶片導電墊CP1。晶片導電墊CP1用以電連接至外部的接地端。晶片接墊CBP2可用以電連接至電子元件的非接地端（例如：其他電壓訊號端），並可透過電路層110中的晶片走線TRC2電連接至一晶片導電墊CP2。晶片導電墊CP2用以電連接至外部的非接地端（例如：電壓訊號）。請注意，晶片接墊CBP1、CBP2與晶片導電墊CP1、CP2之間的電連接方式並不限於此。在其他實施例中，晶片接墊CBP1、CBP2與晶片導電墊CP1、CP2之間的電連接方式可依據需求來設計。
第2圖繪示本發明一實施例之封裝後晶片200的俯視圖，第3圖繪示封裝後晶片200沿著第2圖剖線A-A’之剖面示意圖，第4圖繪示封裝後晶片200沿著第2圖剖線B-B’之剖面示意圖。如第2圖與第3圖所示，本實施例的封裝後晶片200包括電路板100、散熱片210、晶片220、金屬線230、封裝膠體240以及錫球(solder ball)250，其中電路板100的結構可參酌上文的說明，不再重複贅述。
散熱片210透過黏著劑（例如導電膠）與電路板100的散熱接墊HBP電連接。散熱片210在電路板100的俯視方向Z上覆蓋晶片220，散熱片210的上表面暴露出封裝膠體240外，藉此可將晶片220在運作時所產生的熱量散出。由於散熱片210包括導熱性佳的導電材料（例如金屬），因此散熱片210還具有電磁干擾(electromagnetic interference, EMI)防護的效果，可屏蔽晶片220受到外界訊號的干擾。
第5圖繪示本發明一實施例之散熱片210的俯視圖，散熱片210包括4個引腳210b。散熱片210的4個引腳210b分別黏著於電路板100上的4個散熱接墊HBP上，如第2圖與第3圖所示，以使散熱片210透過4個散熱導電墊HP電連接至接地端。此外，各引腳210b可具有一開口212，藉此可降低引腳210b在經過多次膨脹收縮之後產生斷裂的可能性。請注意，本發明中在引腳210b的數量不限於4，在另一實施例中，引腳210b的數量為8，在此情況下，電路板100亦對應具有8個散熱接墊HBP與8個散熱導電墊HP。請注意，本發明中在引腳210b的數量亦不限於偶數。
晶片220可透過金屬線230與電路板100上的晶片接墊CBP電連接。在本實施例中，晶片220的銲墊係藉由打線接合(wire bonding)的方式電連接至晶片接墊CBP1、CBP2，但不以此為限。在變化實施例中，銲墊亦可藉由覆晶技術(flip-chip)或其他方式電連接至晶片接墊CBP1、CBP2。
散熱片210內外均設置有封裝膠體240，且封裝膠體240覆蓋晶片220。在另一實施例中，可僅在散熱片內設置封裝膠體。在另一實施例中，封裝後晶片亦可不具有封裝膠體。
錫球250分別與散熱導電墊HP與晶片導電墊CP1、CP2接合，以提高封裝後晶片200與其他電路板接合的成功率。在另一實施例中，封裝後晶片亦可不具有錫球。
值得說明的是，在傳統的封裝後晶片中，連接到散熱導電墊的接地走線係互相電連接。在此情況下，即使散熱片的引腳與散熱接墊間有黏合不佳的情形，散熱導電墊亦可透過接地走線與其他散熱導電墊電連接，因此無法藉由量測兩散熱導電墊間的電阻值，來判斷散熱片的引腳與散熱接墊間是否有黏合不佳的情形，以找出具有天線效應的封裝後晶片。
然而，於本發明中，散熱片210尚未黏著至電路板100的情況下，散熱導電墊HP彼此電性絕緣。當散熱片210黏著至電路板100後，原本在電路板100中彼此絕緣的散熱導電墊HP，可經由各自的散熱走線TRH電連接至散熱片210，進而透過散熱片210彼此電連接。因此，當散熱片210的引腳210b與散熱接墊HBP之間有黏合不佳的情形時，對應的散熱導電墊HP與其他散熱導電墊HP之間的電阻值會大幅增加，如此一來，便可藉由量測兩散熱導電墊HP間的電阻值，來判斷散熱片的引腳210b與散熱接墊HBP間是否有黏合不佳的情形，以找出具有天線效應的封裝後晶片。舉例來說，當有任兩散熱導電墊間的電阻值未落在一預定範圍內時，便代表散熱片的引腳與散熱接墊間有黏合不佳的情況，該封裝後晶片會有天線效應而應被判定成不良品。 以上所述僅為本發明之實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧電路板
100a‧‧‧上表面
100b‧‧‧下表面
110‧‧‧電路層
112‧‧‧絕緣層
200‧‧‧封裝後晶片
210‧‧‧散熱片
210a‧‧‧遮蔽主體
210b‧‧‧引腳
212‧‧‧開口
220‧‧‧晶片
230‧‧‧金屬線
240‧‧‧封裝膠體
250‧‧‧錫球
CBP1、CBP2‧‧‧晶片接墊
HP‧‧‧散熱導電墊
CP1、CP2‧‧‧晶片導電墊
HBP‧‧‧散熱接墊
TRH‧‧‧散熱走線
TRC1、TRC2‧‧‧晶片走線
Z‧‧‧俯視方向
第1圖繪示本發明一實施例之電路板之剖面示意圖。 第2圖繪示本發明一實施例之封裝後晶片之俯視圖。 第3圖繪示封裝後晶片沿著第2圖剖線A-A’之剖面示意圖。 第4圖繪示封裝後晶片沿著第2圖剖線B-B’之剖面示意圖。 第5圖繪示本發明一實施例之散熱片之俯視示意圖。

Claims (12)

  1. 一種電路板，包括： 彼此相對的一上表面以及一下表面； 複數個散熱接墊，設置在該上表面上，用以電連接一散熱元件，其中該等散熱接墊彼此電性絕緣；以及 複數個散熱導電墊，設置在該下表面上，其中該等散熱導電墊彼此電性絕緣，且該等散熱導電墊分別電連接至該等散熱接墊。
  2. 如請求項1所述之電路板，另包括： 一電路層，包括複數條散熱走線，其中該等散熱導電墊分別透過該等散熱走線電連接至該等散熱接墊，且該等散熱走線彼此電性絕緣。
  3. 如請求項2所述之電路板，另包括： 複數個晶片接墊，設置在該上表面上，用以電連接一電子元件，其中各該散熱接墊均與該等晶片接墊電性絕緣。
  4. 如請求項3所述之電路板，另包括： 複數個晶片導電墊，設置在該下表面上，其中各該散熱導電墊均與該等晶片導電墊電性絕緣。
  5. 如請求項4所述之電路板，其中該電路層另包括： 複數條晶片走線，其中該等晶片導電墊中的至少一者透過該等晶片走線中至少之一者電連接至該等晶片接墊中的至少一者，且該等散熱走線電性絕緣於該等晶片走線。
  6. 一種封裝後晶片，包括： 如請求項1所述之該電路板；以及 一散熱元件，黏著在該電路板的該等散熱接墊上，該散熱元件與該等散熱接墊電連接，且該等散熱接墊透過該散熱元件彼此電連接。
  7. 如請求項6所述之封裝後晶片，其中該電路層另包括： 複數條散熱走線，其中該等散熱導電墊分別透過該等散熱走線電連接至該等散熱接墊。
  8. 如請求項7所述之封裝後晶片，另包括： 一電子元件，設置在該電路板與該散熱元件之間； 其中該電路板另包括複數個晶片接墊，設置在該上表面上，電連接該電子元件，且各該散熱接墊均與該等晶片接墊電性絕緣。
  9. 如請求項8所述之封裝後晶片，其中該電路板另包括： 複數個晶片導電墊，設置在該電路板之該下表面上，且各該散熱導電墊均與該等晶片導電墊電性絕緣。
  10. 如請求項9所述之封裝後晶片，其中該電路層另包括： 複數條晶片走線，其中該等晶片導電墊中的至少一者透過該等晶片走線中至少之一者電連接至該等晶片接墊中的至少一者，且該等散熱走線電性絕緣於該等晶片走線。
  11. 如請求項6所述之封裝後晶片，還包括一封裝膠體，設置於該電路板上。
  12. 如請求項6所述之封裝後晶片，還包括複數個錫球(solder ball)，分別與該等散熱導電墊接合。
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