TWI628775B - 半導體封裝、半導體設備及半導體封裝的製造方法 - Google Patents

半導體封裝、半導體設備及半導體封裝的製造方法 Download PDF

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TWI628775B
TWI628775B TW105120334A TW105120334A TWI628775B TW I628775 B TWI628775 B TW I628775B TW 105120334 A TW105120334 A TW 105120334A TW 105120334 A TW105120334 A TW 105120334A TW I628775 B TWI628775 B TW I628775B
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package
conductive layer
layer
semiconductor package
electronic component
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TW105120334A
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TW201707181A (zh
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許文松
林世欽
鄭道
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聯發科技股份有限公司
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種半導體封裝包括：一基底，一第一電子元件，一第一導電層，一第一柱層及一第一封裝體。該第一電子元件設置在該基底上。該第一柱層連接該第一導電層及該基底。該第一封裝體封裝該第一導電層，該第一柱層及該第一電子元件。該第一導電層嵌入於該第一封裝體中。

Description

半導體封裝、半導體設備及半導體封裝的製造方法
本發明涉及封裝領域，特別係涉及一種薄的半導體封裝、半導體設備及半導體封裝的製造方法。
於電子產業中，具有高性能的高整合度(integration)及多功能性成為新產品的基本。同時，由於產品的製造成本與其尺寸成正比，因此高整合度會導致更高的製造成本。因此，對IC(Integrated Circuit，積體電路)封裝的小型化要求已變得越來越重要。
由於對於單個封裝中的高密度系統整合，PoP(Package-on-package，封裝上封裝)係成本划算的解決方案，因此PoP為目前發展最快的半導體封裝技術。於PoP結構中，可以將各式各樣的封裝整合於單個半導體封裝中以降低其尺寸。因此，存在提供一種半導體封裝來克服或者至少緩解上述問題的需要。
因此，增加3D(三維)圖像處理電路的性能的同時，降低電源消耗並延長行動設備的工作時間係重要的。
因此，本發明之主要目的即在於提供一種半導體封裝、半導體設備及半導體封裝的製造方法，可以降低半導體封裝的厚度。
根據本發明至少一個實施例一種半導體封裝，包括：一基底；一第一電子元件，設置在該基底上；一第一導電層；一第一柱層，連接該第一導電層及該基底；以及一第一封裝體，封裝該第一導電層，該第一柱層及該第一電子元件；其中，該第一導電層嵌入於該第一封裝體中。
根據本發明至少一個實施例的一種半導體設備，包括：一半導體封裝及一第二電子元件；該半導體封裝包括：一基底；一第一電子元件，設置在該基底上；一第一導電層；一第一柱層，連接該第一導電層及該基底；以及一第一封裝體，封裝該第一導電層，該第一柱層及該第一電子元件；其中，該第一導電層嵌入於該第一封裝體中；其中，該第二電子元件設置在該第一導電層上。
根據本發明至少一個實施例的一種半導體設備，包括：一半導體封裝及一第二電子元件；該半導體封裝包括：一基底；一第一電子元件，設置在該基底上；一第一導電層；一第一柱層，連接該第一導電層及該基底；一第一封裝體，封裝該第一導電層，該第一柱層及該第一電子元件；一第二導電層；一第二柱層，連接該第一導電層及該第二導電層；以及一第二封裝體，封裝該第二導電層及該第二柱層；其中，該第一導電層嵌入於該第一封裝體中；其中，該第二電子元件設置在該第二導電層上。
根據本發明至少一個實施例的一種半導體封裝的製造方法，包括：提供一載體；在該載體上形成一第一導電層；在該第一導電層上形成一第一柱層；在一基底上設置一第一電子元件；將該第一柱層連接至 該基底；形成一第一封裝體以封裝該第一電子元件，該第一導電層及該第一柱層；以及移除該載體。
根據本發明至少一個實施例的一種半導體封裝的製造方法，包括：在該載體上形成一第二導電層；形成一第二封裝體以封裝該第二導電層；形成一穿過該第二封裝體的一第二柱層，其中該第二柱層電性連接至該第二導電層；在該第二柱層及該第二封裝體上形成一第一導電層；在該第一導電層上形成一第一柱層；在一基底上設置一第一電子元件；將該第一柱層連接至該基底；形成一第一封裝體以封裝該第一電子元件，該第一導電層及該第一柱層；以及移除該載體。
本發明實施例，將第一導電層嵌入於第一封裝體中，從而可以降低半導體封裝的厚度。
100、200‧‧‧半導體封裝
110‧‧‧基底
120‧‧‧第一電子元件
130、121‧‧‧導電接頭
140‧‧‧第一柱層
150‧‧‧第一導電層
160‧‧‧第一封裝體
111‧‧‧接墊
110u‧‧‧上表面
110b‧‧‧下表面
141、241‧‧‧柱形物
151、251‧‧‧元件
151’、251’‧‧‧第一元件
151”、251”‧‧‧第二元件
1511、2511‧‧‧第一層
1512、2512‧‧‧第二層
151s‧‧‧第一側面
151u‧‧‧第一上表面
160u‧‧‧第二上表面
t1、t2、t3、t4、t5‧‧‧厚度
240‧‧‧第二柱層
250‧‧‧第二導電層
260‧‧‧第二封裝體
251s‧‧‧第二側面
251u‧‧‧第三上表面
260u‧‧‧第四上表面
11‧‧‧第二電子元件
10、20‧‧‧半導體設備
170‧‧‧載體
260a‧‧‧開口
在閱讀了下述細節描述及所附圖式之後，本發明之目的及優點對發明所屬領域具有通常知識者將更顯而易見，其中：第1圖為根據本發明實施例的半導體封裝的結構示意圖；第2圖為根據本發明另一實施例的半導體封裝的結構示意圖；第3圖為根據本發明實施例的半導體設備的結構示意圖；第4圖為根據本發明另一實施例的半導體設備的結構示意圖；第5A至5H圖示意了第1圖的半導體封裝的製造製程；以及第6A至6K圖示意了第2圖的半導體封裝的製造製程。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
第1圖為根據本發明實施例的半導體封裝100的結構示意圖。該半導體封裝100包括：一基底110，至少一個第一電子元件120，至少一個導電接頭(conductive contact)130，一第一柱層(pillar layer)140，一第一導電層150及一第一封裝體160。
該基底110例如為多層結構或者單層結構。該基底110可以為有機基底，陶瓷基底，矽基底，金屬基底，等等。該基底110包括：複數個接墊(pad)111，用於電性連接該第一柱層140。
在本實施例中，第一電子元件120係以“正面向下”的方向耦接至基底110的一上表面110u，並且經由複數個導電接頭121電性連接至基底110。該組態有時被稱為“覆晶(flip-chip)”。導電接頭121可以為焊球(solder ball)、導電柱，等等。
在其他一些實施例中，第一電子元件120係以“正面向上”的方向耦接至基底110，並且經由複數條導電接合線(未示出)電性連接至 基底110。第一電子元件120可以為一主動晶片或者一被動元件，諸如一電阻、一電感或一電容。在另一實施例中，第一電子元件120的數量可以為複數個。
另外，第一電子元件120例如為一晶片或一被動元件，諸如電阻、電感或電容。在另一實施例中，第一電子元件120的數量可以為複數個。
導電接頭130設置在基底110的下表面110b上。半導體封裝100可以通過該導電接頭130來設置在外部電路上及電性連接至該外部電路，諸如電路板。導電接頭130可以為焊球，導電柱，等等。
第一柱層140連接第一導電層150及基底110，以電性地連接該第一導電層150及該基底110。在本實施例中，第一柱層140包括：複數個柱形物(pilliar)141。該等柱形物141可以由諸如銅等材料形成。
第一導電層150包括：複數個元件151，諸如接墊、走線(trace)或者他們的組合。在本實施例中，元件151可以包括：複數個第一元件151’及複數個第二元件151”，其中第一元件151’為第一走線，第二元件151”為第一接墊。可選地，所有元件151均可以為第一接墊或者第一走線。儘管沒有示出，但是至少一個第一元件151’可以連接至少一個第二元件151”。
第一元件151’形成於第一電子元件120的上方，並且在第一元件151’與第一電子元件120之間沒有柱形物。但是，這樣的範例並不意味著限制。
每個元件151可以為多層結構或者單層結構。例如，每個元件151可以包括：一第一層1511及一第二層1512。該第一層1511及第二層1512可以為鎳，金，銅或者他們的組合。在實施例中，第一層1511包括：表面處理(surface finishing)層及/或晶種層(seed layer)。
每個元件151(走線或接墊)具有一第一側面151s及一第一上表面151u，該第一上表面151u從第一封裝體160的一第二上表面160u露出，並且第一封裝體160封裝(encapsulate)第一導電層150的第一側面151s。
第一導電層150具有範圍在10μm(微米)~20μm之間的厚度t1。相比於插入層(interposer)，第一導電層150的厚度t1非常地小。一般地，插入層具有大於100μm的厚度。在本實施例中，半導體封裝100可以省略插入層，因此可以降低半導體封裝100的厚度t2。
第一封裝體160封裝第一導電層150，第一柱層140及第一電子元件120。該第一封裝體160可以由相同材料製成。例如，第一封裝體160為成型材料(molding compound)，該成型材料例如可以由如下材料製成：酚酫基樹脂(novolac-based resin)，環氧基樹脂，矽基樹脂(silicone-based resin)，或者另一合適的封裝物。該成型材料也可以包含合適的填充物，諸如粉未狀的SiO2。
在一個實施例中，第一封裝體160具有厚度t3。第一導電層150嵌入於第一封裝體160中，因此無需增加第一封裝體160的厚度t3。
另外，第一導電層150的第一上表面151u及第一封裝體160的第二上表面160u係彼此對齊的。例如，第一上表面151u及第二上表面160u共平面。
第2圖為根據本發明另一實施例的半導體封裝200的結構示意圖。該半導體封裝200包括：上述的基底110，上述的至少一個第一電子元件120，上述的至少一個導電接頭130，上述的第一柱層140，上述的第一導電層150，上述的第一封裝體160，一第二柱層240，一第二導電層250及一第二封裝體260。
在本實施例中，第二柱層240，第二導電層250及第二封裝體260可以形成一封裝基底，該封裝基底通過第一柱層140及第一導電層150來電性連接至基底110。
第一導電層150包括：複數個元件151，諸如接墊、走線或者他們的組合。在本實施例中，元件151可以包括：複數個第一元件151’及複數個第二元件151”，其中第一元件151’為第一走線，第二元件151”為第一接墊。另外，在本實施例中，每個元件151均為單層結構。例如，每個元件151僅包括上述的第二層1512，如前所描述。
第二柱層240連接第一導電層150及第二導電層250，從而電性地連接第一導電層150及第二導電層250。在本實施例中，第二柱層240包括：複數個柱形物241，連接第一導電層150及第二導電層250。
第二導電層250具有類似於第1圖中的第一導電層150的結構。
例如，第二導電層250包括：複數個元件251，諸如接墊、走線或者他們的組合。在本實施例中，元件251可以包括：複數個第一元件251’及複數個第二元件251”，其中第一元件251’及第二元件251”均為第二接墊。儘管沒有示出，但是至少一個第一元件251’可以連接至少一個第二元件251”。
第一元件251’形成於第一電子元件120及第一元件151’的上方，並且沒有柱形物位於該第一元件151’及該第一元件251’之間。但是，此範例並不意味著限制。在另一實施例中，至少一個柱形物可以穿過第二封裝體260來連接該第一元件151’及該第一元件251’。
每個元件251可以為多層結構或者單層結構。例如，每個元件251可以包括：一第一層2511及一第二層2512。第一層2511及第二層2512可以為鎳，金，銅或者他們的組合。在實施例中，第一層2511包括：表面處理層及/或晶種層。
每個元件251(走線或接墊)具有一第二側面251s及一第三上表面251u，該第三上表面251u從第二封裝體260的一第四上表面260u露出，並且第二封裝體260封裝該第二側面251s。
第二封裝體260封裝第二導電層250及第二柱層240。第二封裝體260可以由相同材料製成。例如，第二封裝體260可以由層壓板(lamination)製成。
第二封裝體260具有厚度t4。相比於插入層，第二封裝體260的厚度t4係非常地小。一般地，插入層具有大於100μm的厚度。在本 實施例中，半導體封裝200可以省略插入層，因此可以降低半導體封裝200的厚度t2。
另外，第二導電層250的第三上表面251u及第二封裝體260的第四上表面260u係彼此對齊的。例如，第三上表面251u及第四上表面260u共平面。
第3圖為根據本發明實施例的一半導體設備10的結構示意圖。該半導體設備10包括：上述的半導體封裝100及至少一個第二電子元件11。
該半導體封裝100包括：基底110，至少一個第一電子元件120，至少一個導電接頭130，第一柱層140，第一導電層150及第一封裝體160。第二電子元件11以“正面向下”的方向設置在半導體封裝100的第一導電層150上，並且經由複數個導電接頭112來電性連接至第一導電層150。導電接頭112可以為焊球，導電柱，等等。在另一實施例中，第二電子元件11以“正面向上”的方向設置在半導體封裝100的第一導電層150上，並且經由複數個導電接線(未示出)來電性連接至第一導電層150。
第二電子元件11例如可以為記憶體，除了記憶體以外的半導體元件，另一半導體封裝，主動元件，被動元件，等等。在另一實施例中，第二電子元件11可以為含有複數個晶粒的半導體封裝，諸如彼此堆疊的複數個DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)晶粒。
在本實施例中，由於降低了半導體封裝100的厚度t2，因此半導體設備10的厚度t5可以等於或小於1.2mm(毫米)。
第4圖為根據本發明另一實施例的半導體設備20的結構示意圖。該半導體設備20包括：上述的半導體封裝200及至少一個第二電子元件11。
該半導體封裝200包括：基底110，至少一個第一電子元件120，至少一個導電接頭130，第一柱層140，第一導電層150，第一封裝體160，第二柱層240，第二導電層250及第二封裝體260。第二電子元件11以“正面向下”或“正面向上”的方向設置在半導體封裝200的第二導電層250上。
在本實施例中，由於降低了半導體封裝200的厚度t2，因此半導體設備20的厚度t5可以等於或小於1.2mm。
第5A至5H圖示意了第1圖的半導體封裝100的製造製程。
參考第5A圖，提供了一載體170。該載體170可以由包含銅、鐵或鋼的金屬板製成。
參考第5A圖，例如使用微影(photolithography)、化學鍍(electroless plating)，電鍍，印刷，濺射(sputtering)，真空沉積(vacuum deposition)等在載體170上形成第一導電層150。
第一導電層150包括：複數個元件151，諸如接墊、走線或者他們的組合。在本實施例中，元件151可以包括：複數個第一元件151’及複數個第二元件151”，其中第一元件151’為第一走線，第二元件151”為第一接墊。可選地，所有元件151均可以為第一接墊或者第一走線。儘管沒有示出，但是至少一個第一元件151’可以連接至少一個第二元件151”。
參考第5B圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等在第一導電層150上形成第一柱層140。第一柱層140包括：多個柱形物141，設置在第一導電層150中的第二元件151”上。
參考第5C圖，翻轉載體170，諸如將第一柱層140面向下。
參考第5D圖，例如使用SMT(Surface Mount Technology，表面貼裝技術)來將第一電子元件120設置在基底110上。
參考第5E圖，例如使用SMT來將第一柱層140連接至基底110。該第一導電層150可以通過第一柱層140和基底110來電性連接第一電子元件120。
參考第5F圖，形成封裝第一導電層150及第一柱層140的第一封裝體160。第一封裝體160可以由各式的封裝技術形成，諸如壓縮成型(compression molding)，注射成型(injection molding)，傳遞模塑(transfer molding)或者點膠技術(dispensing technology)。
參考第5G圖，例如使用蝕刻，剝離等方式來移除載體170。在移除了載體170之後，露出第一導電層150的第一上表面151u及第一封裝體160的第二上表面160u，其中第一上表面151u及第二上表面160u彼此對齊。例如，第一上表面151u及第二上表面160u共平面。
參考第5H圖，例如使用球安裝技術來在基底110的下表面110b上形成導電接頭130，從而形成第1圖的半導體封裝100。
在另一實施例中，將第二電子元件11設置在第5H圖的第一導電層150上以形成第3圖的半導體設備10。
需要說明的是，發明所屬領域具有通常知識者，可以靈活安排第第5A至5H圖所涉及的製程的順序，這些本發明均不限制。
第6A~6K圖示意了第2圖所示的半導體封裝200的製造製程。
參考第6A圖，提供了一載體170。該載體170可以由包含銅、鐵或鋼的金屬板製成。
參考第6A圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等在載體170上形成第二導電層250。
第二導電層250包括：複數個元件251，諸如接墊、走線或者他們的組合。在本實施例中，元件251可以包括：複數個第一元件251’及複數個第二元件251”，其中例如第一元件251’及第二元件251”均為第二接墊。儘管沒有示出，但是至少一個第一元件251’可以連接至少一個第二元件251”。
參考第6B圖，例如使用層壓(laminating)技術來在載體170上形成封裝第二導電層250的第二封裝體260。在本實施例中，第二封裝體260例如為層壓板。
參考第6C圖，例如使用顯影，化學蝕刻，鐳射鑽孔，機械鑽孔等方式在第二封裝體260上形成複數個開口260a，以露出第二導電層250的第二元件251”。
參考第6D圖，通過第二封裝體260的開口260a來形成連接第二元件251”的第二柱層240。
參考第6D圖，在第二柱層240及第二封裝體260上形成第一導電層150。在本實施例中，第一導電層150通過第二柱層240及第二封裝體260間接地形成在載體170上。
在本實施例中，第一導電層150包括：複數個元件151，諸如接墊，走線或者他們的組合。在本實施例中，元件151可以包括：複數個第一元件151’及複數個第二元件151”。其中第一元件151’為第一走線，以及第二元件151”為第一接墊。
另外，第二柱層240及第一導電層240可以在相同製程或者兩個獨立的製程中形成，諸如無電鍍，電鍍，印刷，濺射，真空沉積，等等。
參考第6E圖，例如使用化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第一導電層150上形成第一柱層140。第一柱層140包括：多個柱形物141，設置在第一導電層150中的第二元件151”上。
參考第6F圖，翻轉載體170，諸如將第一柱層140朝向下。
參考第6G圖，例如使用SMT來將第一電子元件120設置在基底110上。
參考第6H圖，第二柱層240，第二導電層250及第二封裝體260可以形成一封裝基底。該封裝基底例如通過使用SMT來通過第一柱層140及第一導電層150連接基底110。
參考第6I圖，形成封裝第一電子元件120，第一導電層150及第一柱層140的第一封裝體160。第一封裝體160可以由各種各樣的封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
參考第6J圖，例如使用蝕刻，剝離等方式移除載體170。在移除了載體170之後，露出第二導電層250的第三上表面251u及第二封裝體260的第四上表面260u，其中第三上表面251u及第四上表面260u彼此對齊。例如，第三上表面251u及第四上表面260u共平面。
參考第6K圖，例如使用球安裝技術來在基底110的底面(即下表面)110b上形成第二導電接頭130，以形成第2圖的半導體封裝200。
在另一實施例中，可以將第二電子元件11設置在第6K圖的第二導電層250上以形成第4圖的半導體設備20。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。

Claims (16)

  1. 一種半導體封裝，包括：一基底；一第一電子元件，設置在該基底上；一第一導電層；一第一柱層，連接該第一導電層及該基底；以及一第一封裝體，封裝該第一導電層，該第一柱層及該第一電子元件；其中，該第一導電層嵌入於該第一封裝體中；其中該第一導電層包括：一第一走線。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，該第一導電層包括：一第一接墊，從該第一封裝體中露出；其中該第一走線連接至該第一接墊。
  3. 如申請專利範圍第2項所述的半導體封裝，其中，該第一接墊及該第一走線中的每一個均具有一第一側面及一第一上表面，該第一上表面從該第一封裝體露出，該第一側面由該第一封裝體封裝。
  4. 如申請專利範圍第1項所述的半導體封裝，其中，該第一導電層包括：複數個該第一走線，形成在該第一電子元件的上方。
  5. 如申請專利範圍第1項所述的半導體封裝，其中，該第一導電層的厚度在10μm~20μm的範圍內。
  6. 如申請專利範圍第1項所述的半導體封裝，其中，該第一封裝體為成型材料。
  7. 如申請專利範圍第1項所述的半導體封裝，其中，該第一導電層具有一第一上表面，該第一封裝體具有一第二上表面，該第一上表面與該第二上表面對齊。
  8. 如申請專利範圍第1~7項中任一項所述的半導體封裝，其中，還包括：一第二導電層；一第二柱層，連接該第一導電層及該第二導電層；以及一第二封裝體，封裝該第二導電層及該第二柱層。
  9. 如申請專利範圍第8項所述的半導體封裝，其中，該第二導電層包括：一第二接墊，從該第二封裝體露出。
  10. 如申請專利範圍第9項所述的半導體封裝，其中，該第二接墊具有一第二側面及一第三上表面，該第三上表面從該第二封裝體中露出，該第二側面由該第二封裝體封裝。
  11. 如申請專利範圍第8項所述的半導體封裝，其中，該第二封裝體為層壓層。
  12. 如申請專利範圍第8項所述的半導體封裝，其中，該第二導電層具有一第三上表面，該第二封裝體具有一第四上表面，該第三上表面與該第四上表面對齊。
  13. 一種半導體設備，包括：如申請專利範圍第1~7項中任一項所述的半導體封裝；以及第二電子元件，設置在該半導體封裝的該第一導電層上。
  14. 一種半導體設備，包括：如申請專利範圍第8~12項中任一項所述的半導體封裝；以及 第二電子元件，設置在該半導體封裝的該第二導電層上。
  15. 一種半導體封裝的製造方法，包括：提供一載體；在該載體上形成一第一導電層；在該第一導電層上形成一第一柱層；在一基底上設置一第一電子元件；將該第一柱層連接至該基底；形成一第一封裝體以封裝該第一電子元件，該第一導電層及該第一柱層；以及移除該載體。
  16. 一種半導體封裝的製造方法，包括：在一載體上形成一第二導電層；形成一第二封裝體以封裝該第二導電層；形成一穿過該第二封裝體的一第二柱層，其中該第二柱層電性連接至該第二導電層；在該第二柱層及該第二封裝體上形成一第一導電層；在該第一導電層上形成一第一柱層；在一基底上設置一第一電子元件；將該第一柱層連接至該基底；形成一第一封裝體以封裝該第一電子元件，該第一導電層及該第一柱層；以及移除該載體。
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