TWI625838B - 複合焊球、半導體封裝、半導體裝置及制造方法 - Google Patents
複合焊球、半導體封裝、半導體裝置及制造方法 Download PDFInfo
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- TWI625838B TWI625838B TW105101119A TW105101119A TWI625838B TW I625838 B TWI625838 B TW I625838B TW 105101119 A TW105101119 A TW 105101119A TW 105101119 A TW105101119 A TW 105101119A TW I625838 B TWI625838 B TW I625838B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0244—Powders, particles or spheres; Preforms made therefrom
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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- B23K35/264—Bi as the principal constituent
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract
本發明提供了一種複合焊球、半導體封裝、半導體裝置及制造方法。其中,該半導體封裝包括:一第一基底,一第二基底,一複合焊球以及一第一半導體元件。該複合焊球包括:一核心、一包封層以及一阻擋層。該複合焊球設置在該第一基底和該第二基底之間,以電性連接該第一基底和該第二基底。該阻擋層設置在該核心和該包封層之間。其中,該阻擋層的熔點高於該核心的熔點,該核心的熔點高於該包封層的熔點。該第一半導體元件設置在該第一基底和該第二基底之間。
Description
本發明涉及半導體領域,尤其涉及一種複合焊球,使用該複合焊球的半導體封裝,使用該複合焊球的半導體裝置以及該半導體封裝的制造方法。
在電子工業中,具有高性能的高集成度和多功能成為新產品之基本。與此同時,由於制造成本正比於產品之尺寸,因此高集成度可能導致更高之製造成本。因此,對積體電路(Integrated Circuit;IC)封裝之小型化的需求已變得越來越關鍵。
由於封裝上封裝(Package-on-Package;PoP)是單個封裝中之高密度系統集成的划算的解決方案,因此封裝上封裝是目前發展最快的半導體封裝技術。在封裝上封裝結構中,各種各樣的封裝集成在單個半導體封裝中,以降低尺寸。相應地,存在提供一種半導體封裝來克服或者至少降低上述問題的需要。
因此,在增加3D圖形處理電路的性能的同時,降低電子功率的消耗以及延長行動設備的運行時間是重要的。
因此,本發明之主要目的即在於提供一種複合焊球、半導體封裝、半導體裝置及制造方法。
在本發明的一個實施例中,提供了一種複合焊球。該複合焊球包含:一核心,一包封層以及一阻擋層。該阻擋層設置在該核心與該包封層之間。其中,該阻擋層的熔點高於該核心的熔點,該核心的熔點高於該包封層的熔點。
在本發明的另一實施例中,提供了一種半導體封裝。該半導體封裝包含:一第一基底,一第二基底,一複合焊球以及一第一半導體元件。該複合焊球包含:一核心,一包封層以及一阻擋層。該複合焊球設置在該第一基底和該第二基底之間,以電性連接至該第一基底和該第二基底。該阻擋層設置在該核心與該包封層之間。其中,該阻擋層的熔點高於該核心的熔點,該核心的熔點高於該包封層的熔點。該第一半導體元件設置在該第一基底和該第二基底之間。
在本發明另一個實施例中,提供了一種半導體裝置。該半導體裝置包含一半導體封裝以及一第二半導體元件。該半導體封裝包含:一第一基底,一第二基底,複合焊球以及一第一半導體元件。該複合焊球包含:一核心,一包封層以及一阻擋層。該複合焊球設置在該第一基底和該第二基底之間,以電性連接至該第一基底和該第二基底。該阻擋層設置在該核心與該包封層之間。其中,該阻擋層的熔點高於該核心的熔點,該核心的熔點高於該包封層的熔點。該第一半導體元件設置在該第一基底和該第二基底之間。該第二半導體元件設置在該半導體封裝之第二基底之上。
在本發明另一實施例中,提供了一種半導體封裝的制造方法。該制造方法包含如下步驟:提供一半導體基底;在該半導體基底上設置一第一半導體元件;提供一第二基底;在該第二基底上設置複數個複合
焊球;以該等複合焊球面向該第一基底的方式,連接該第一基底和該第二基底,其中,該複合焊球設置在該第一基底和該第二基底之間。
本發明實施例之複合焊球,其中核心的熔點高於包封層的熔點,而阻擋層的熔點又高於該核心的熔點。因此可以在回流製程期間,可以阻止核心熔化和變形,從而防止複合焊球變形。
100、200‧‧‧半導體封裝
110‧‧‧第一基底
120‧‧‧第二基底
130‧‧‧第一半導體元件
140‧‧‧複合焊球
150‧‧‧封裝體
160、131、361‧‧‧導電接觸結構
111‧‧‧接墊
110u‧‧‧上表面
141‧‧‧核心
142‧‧‧阻擋層
143‧‧‧包封層
250‧‧‧底部填充物
110b‧‧‧底面
300‧‧‧半導體裝置
360‧‧‧第二半導體元件
D1、D2‧‧‧外徑
P1‧‧‧間隔
第1圖示出了根據本發明實施例之半導體封裝之示意圖。
第2圖示出了根據本發明另一實施例之半導體封裝之示意圖。
第3圖示出了根據本發明另一實施例之半導體裝置之示意圖。
第4A圖至第4F圖示出了第1圖之半導體封裝之製造過程之示意圖。
第5圖示出了第2圖之半導體封裝之製造過程之示意圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解,電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。以外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接到一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
第1圖示出了根據本發明實施例之半導體封裝100的示意圖。該半導體封裝100包括:第一基底110、第二基底120、第一半導體元
件130、複數個複合焊球(composite solder ball)140、封裝體150和複數個導電接觸結構(conductive contact)160。
第一基底110例如為多層無核心基底。該第一基底110包括:複數個接墊111,用於電性連接至複合焊球140。該第二基底120例如為插入層。
該第一半導體元件130可以通過導電接觸結構131設置在第一基底110之上並電性連接至第一基底110。第二基底120可以通過複合焊球140和第一基底110電性連接至第一半導體元件130。
在本實施例中,第一半導體元件130以面向下(face-down)的方向耦接至第一基底110的上表面110u並且經由複數個導電接觸結構131電性連接至第一基底110。此種配置有時被稱為“覆晶”。導電接觸結構131可以是焊球、導電柱,等等。
在其他實施例中,第一半導體元件130以面向上(face-up)的方向耦接至第一基底110,並經由複數個導電接合線(未示出)電性連接至第一基底110。第一半導體元件130可以是主動芯片或者被動元件,例如電阻器、電感器或電容器。在另一實施例中,第一半導體元件130的數量可以是幾個。
每個複合焊球140包括:核心141、阻擋層(barrier layer)142和包封層(encapsulating layer)143。阻擋層142設置在核心141和包封層143之間。例如,阻擋層142直接或間接地包覆核心141,以及包封層143直接或間接地包覆阻擋層142。
核心141的熔點可以高於包封層143的熔點,如此可以在回流(reflow)製程期間,阻止核心141熔化和變形。如此,可能阻止核心141的外徑D1擴大,以及相應地相鄰兩個複合焊球140之間的最小間隔P1不
會變窄,如此相鄰兩個複合焊球140可以避免互相電性短路,並且可以增加複合焊球140的密度。
在一個實施例中,核心141可以由含錫、鉍或者它們的組合之材料製成。在另一個實施例中,核心141可以由不含銅之材料製成。因此,核心141的外徑D1可以降低,從而包封核心141的包封層143的外徑D2可以降低以及/或半導體封裝100的厚度可以降低。在一個實施例中,在回流之後,包封層143具有介於120μm~130μm之間的外徑D2。
另外,阻擋層142的熔點可以高於核心141的熔點,從而阻擋層142可以限制核心141的外徑D1,以及相應地可以阻止核心141在回流製程期間過變形(over-deforrming)。另外,由於阻擋層142可以限制核心141的外徑D1,因此核心141可以由硬度(hardness)和/或強度(strength)低於阻擋層142的硬度和/或強度的材料製成。例如,阻擋層142可以由含鎳的材料製成,其中該含鎳的材料之硬度和/或強度大於核心141的硬度和/或強度。
另外,包封層143可以是預焊接。在如此設計下,半導體封裝100可以省略額外的預應用在第一基底110和/或第二基底120上的預焊接。在一個實施例中,包封層143可以由含錫、銀和銅中至少兩者的合金材料製成。
封裝體150形成在第一基底110和第二基底120之間,並且包封第一半導體元件130和複合焊球140。
封裝體150例如可以包括:酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、硅基樹脂(silicone-based resin)或者另一合適的包封材料。合適的填充物也可以被包含,例如粉狀的SiO2。
導電接觸結構160可以設置在第一基底110的底面110b之上。半導體封裝100設置在外部電路上並且電性連接至該外部電路,例如電路板。導電接觸結構160可以是焊球、導電柱,等等。
第2圖示出了根據本發明另一實施例之半導體封裝200之結構示意圖。半導體封裝200包括:第一基底110、第二基底120、第一半導體元件130、複合焊球140、底部填充物250和複數個導電接觸結構160。
底部填充物250形成在第一半導體元件130和第一基底110之間,並且包封第一半導體元件130的複數個導電接觸結構131。
在本發明中,半導體封裝200省略了封裝體150。在另一實施例中,半導體封裝200可以進一步包括:封裝體150,包封第一半導體元件130、複合焊球140和底部填充物250。
第3圖示出了根據本發明另一實施例之半導體裝置300的示意圖。該半導體裝置300包括:半導體封裝100以及第二半導元件360。第二半導體元件360例如是記憶體、非記憶體的半導體元件、另一半導體封裝、主動元件、被動元件,等等。第二半導體元件360通過複數個導電接觸結構361設置在半導體封裝100的第二基底120之上,並且電性連接至該第二基底120。導電接觸結構361可以是焊球、柱,等等。
第4A至第4F圖示出了第1圖的半導體封裝100的制造過程的示意圖。
參考第4A圖,提供了第一基底110。
參考第4B圖,例如使用表面安裝技術(surface mount technology;SMT)將第一半導體元件130設置在第一基底110上。
參考第4C圖,提供了第二基底120。
參考第4D圖,例如使用球安裝技術(ball mounting technology)將複數個複合焊球140設置在第二基底120上。每個複合焊球140包括:核心141、阻擋層142和包封層143。阻擋層142設置在核心141和包封層143之間。例如,阻擋層142直接或間接包封核心141,以及包封層143直接或間接地包封阻擋層142。
參考第4E圖,通過複合焊球140面向第一基底110的方式將第一基底110連接至第二基底120,其中複合焊球140設置在第一基底110和第二基底120之間,以電性連接第一基底110和第二基底120。
在回流製程之後,複合焊球140的包封層143熔化以與第一基底110的接墊111焊接。由於核心141的熔點高於包封層143的熔點,所以回流溫度可以足夠高。例如,回流溫度可以達到245。℃或者更高,從而包封層143可以牢固地形成在第一基底110的接墊111之上,並且可以阻止核心141熔化和/或過變形。在另一實施例中,回流溫度可以接近或超過核心141的熔點。
另外,阻擋層142的熔點大於核心141的熔點,如此,在回流製程期間,阻擋層142可以限制核心141的外徑D1並且相應地阻止核心141過變形。
參考第4F圖,封裝體150設置在第一基底110的上表面110u上並且包封第一半導體元件130。封裝體150可以由各種各樣的封裝技術所形成,例如壓縮成型(compression molding)、射出成型(injection molding)、注塑成型(transfer molding)或者點膠技術。
然後,第1圖的導電接觸結構160可以設置在第1圖的第一基底110的底面110b,以便於形成第1圖所示的半導體封裝100。
第5圖示出了第2圖的半導體封裝200的製造過程之示意圖。底部填充物250例如使用點膠技術形成於第一基底110和第一半導體元件130之間,並且包封導電接觸結構131。另外,半導體封裝200之其它形成步驟類似於第1圖的半導體封裝100的對應步驟,並且不再重復類似之步驟。
以上所述僅為本發明的較佳實施例而已,並不用以限制本發明,凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等,均應包含在本發明的保護範圍之內。
Claims (12)
- 一種複合焊球,包含:一核心;一包封層;以及一阻擋層,設置在該核心與該包封層之間;其中,該阻擋層的熔點高於該核心的熔點,從而限制該核心的外徑以及相應地阻止該核心在回流製程期間過變形;其中,該核心的熔點高於該包封層的熔點。
- 如申請專利範圍第1項所述之複合焊球,其中,該包封層具有介於120μm至130μm之間的外徑。
- 如申請專利範圍第1項所述之複合焊球,其中,該核心由錫、鉍或者它們的組合製成。
- 如申請專利範圍第1項所述之複合焊球,其中,該核心由不含銅的材料製成。
- 如申請專利範圍第1項所述之複合焊球,其中,該包封層由含錫、銀和銅中的至少兩種的合金材料製成。
- 一種半導體封裝,包含:一第一基底;一第二基底;如申請專利範圍第1項至第5項中任一項所述之複合焊球,設置在該第一基底和該第二基底之間,用以電性連接該第一基底和該第二基底;以及一第一半導體元件,設置在該第一基底和該第二基底之間。
- 如申請專利範圍第6項所述之半導體封裝,其中,該第二基底為插入層。
- 一種半導體裝置,包含:如申請專利範圍第6項所述之半導體封裝;以及第二半導體元件,設置在該半導體封裝之該第二基底之上。
- 如申請專利範圍第8項所述之半導體裝置,其中,該第二基底為插入層。
- 如申請專利範圍第8項所述之半導體裝置,其中,該第二半導體元件為記憶體裝置。
- 一種半導體封裝的制造方法,包含:提供一第一基底;在該第一基底上設置一第一半導體元件;提供一第二基底;在該第二基底上設置複數個如申請專利範圍第1項至第5項中任一項所述之複合焊球;以該等複合焊球面向該第一基底的方式,連接該第一基底和該第二基底,其中,該等複合焊球設置在該第一基底和該第二基底之間。
- 如申請專利範圍第11項所述之制造方法,其中,該第二基底為插入層。
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