TWI595605B - 半導體封裝、半導體元件及其製造方法 - Google Patents

半導體封裝、半導體元件及其製造方法 Download PDF

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TWI595605B
TWI595605B TW105120336A TW105120336A TWI595605B TW I595605 B TWI595605 B TW I595605B TW 105120336 A TW105120336 A TW 105120336A TW 105120336 A TW105120336 A TW 105120336A TW I595605 B TWI595605 B TW I595605B
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package
conductive layer
layer
pillar
electronic component
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TW105120336A
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TW201712813A (zh
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許文松
林世欽
鄭道
張垂弘
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聯發科技股份有限公司
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

半導體封裝、半導體元件及其製造方法
本發明涉及封裝技術領域，特別係涉及一種薄的半導體封裝、半導體元件及其製造方法。
於電子產業中，具有高性能的高整合度(integration)及多功能性成為新產品的基本。同時，由於產品的製造成本與其尺寸成正比，因此高整合度會導致更高的製造成本。因此，對IC(Integrated Circuit，積體電路)封裝的小型化要求已變得越來越重要。
由於對於單個封裝中的高密度系統整合，PoP(Package-on-package，封裝上封裝)係成本划算的解決方案，因此PoP為目前發展最快的半導體封裝技術。於PoP結構中，可以將各式各樣的封裝整合於單個半導體封裝中以降低其尺寸。因此，存在提供一種半導體封裝來克服或者至少緩解上述問題的需要。
因此，增加3D(三維)圖像處理電路的性能的同時，降低電源消耗並延長行動設備的工作時間係重要的。
因此，本發明之主要目的即在於提供一種半導體封裝、半導體元件及其製造方法，可以降低其尺寸。
根據本發明至少一個實施例的一種半導體封裝，包括：一封裝基底、一第一電子元件以及一第二封裝體；其中，該封裝基底包括：一第一導電層；一第一柱層，形成於該第一導電層上；一第一封裝體，封裝該第一導電層及該第一柱層；以及一第二導電層，電性連接該第一柱層；其中，該第一電子元件設置在該封裝基底的該第二導電層的上方；該第二封裝體封裝該第一電子元件及該第二導電層。
根據本發明至少一個實施例的一種半導體元件，包括：上述的半導體封裝；一第二柱層，形成於該第二導電層上；以及一第三電子元件，設置在該第二封裝體上方並且通過該第二柱層電性連接該封裝基底；其中，該第二封裝體進一步封裝該第二柱層。
根據本發明至少一個實施例的一種半導體封裝的製造方法，包括：提供一載體；形成一封裝體，包括：於該載體上形成一第一導電層；於該第一導電層上形成一第一柱層；形成第一封裝體來封裝該第一導電層及該第一柱層；以及於該第一柱層上形成一第二導電層；在該封裝基底的該第二導電層的上方設置一第一電子元件；形成一第二封裝體來封裝該第一電子元件及該第二導電層；以及移除該載體。
根據本發明至少一個實施例的一種半導體元件的製造方法，包括：提供一載體；形成一封裝體，包括：於該載體上形成一第一導電層；於該第一導電層上形成一第一柱層；形成第一封裝體來封裝該第一導電層及該第一柱層；以及於該第一柱層上形成一第二導電層；將一第一電 子元件設置在該封裝基底的該第二導電層的上方；將一第二柱層連接至該封裝基底；形成一第二封裝體來封裝該第一電子元件，該第二導電層及該第二柱層；移除該載體；於該第二封裝體上方設置一第三電子元件，其中該第三電子元件通過該第二柱層來電性連接該封裝基底。
以上的半導體封裝、半導體元件及其製造方法，其中的封裝基底係由封裝體來封裝導電層及柱層而形成，由於採用封裝體來形成封裝基底，因此可以降低封裝基底的厚度，從而降低半導體封裝、半導體元件的厚度。
100、200、300、400、500‧‧‧半導體封裝
10、20‧‧‧半導體元件
110、410‧‧‧封裝基底
120‧‧‧第一電子元件
140‧‧‧第二電子元件
11‧‧‧第三電子元件
113‧‧‧第一封裝體
130‧‧‧第二封裝體
413‧‧‧第三封裝體
150、121、115‧‧‧導電接頭
111‧‧‧第一導電層
114‧‧‧第二導電層
411‧‧‧第三導電層
370‧‧‧第四導電層
112‧‧‧第一柱層
260‧‧‧第二柱層
412‧‧‧第三柱層
1111、1141、371‧‧‧元件
1111b‧‧‧第一下表面
113b‧‧‧第二下表面
1111s‧‧‧第一側面
371s‧‧‧第二側面
1121、261‧‧‧柱形物
1121u‧‧‧第一上表面
113u‧‧‧第二上表面
261u‧‧‧第三上表面
130u‧‧‧第四上表面
371u‧‧‧第五上表面
413u‧‧‧第六上表面
t1、t2、t3‧‧‧厚度
270‧‧‧插入層
180、190‧‧‧載體
180u、412u‧‧‧上表面
在閱讀了下述細節描述及所附圖式之後，本發明之目的及優點對發明所屬領域具有通常知識者將更顯而易見，其中：第1圖為根據本發明一實施例的半導體封裝的結構示意圖；第2圖為根據本發明另一實施例的半導體封裝的結構示意圖；第3圖為根據本發明另一實施例的半導體封裝的結構示意圖；第4圖為根據本發明另一實施例的半導體封裝的結構示意圖；第5圖為根據本發明另一實施例的半導體封裝的結構示意圖；第6圖為根據本發明一實施例的半導體元件的結構示意圖；第7圖為根據本發明另一實施例的半導體元件的結構示意圖；第8A至8H圖示意了第1圖的半導體封裝的製造製程；第9A至9B圖示意了第2圖的半導體封裝的製造製程；第10A至10C圖示意了第3圖的半導體封裝的製造製程； 第11A至11H圖示意了第4圖的半導體封裝的製造製程；以及第12A至12C圖示意了第5圖的半導體封裝的製造製程。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
第1圖為根據本發明一實施例的一半導體封裝100的結構示意圖。該半導體封裝100包括：一封裝基底110，一第一電子元件120，一第二封裝體130，一第二電子元件140及至少一個導電接頭(conductive contact)150。
該封裝基底110包括：一第一導電層111，一第一柱層112，一第一封裝體113及一第二導電層114。
該第一導電層111包括：複數個元件1111，諸如接墊，走線(trace)或者他們的組合。每個元件1111均具有一第一下表面1111b及一第一側面1111s，以及該第一封裝體113具有一第二下表面113b。該第一下表面1111b自該第二下表面113b露出，以及該第一下表面1111b與該第 二下表面113b對齊。每個元件1111可以為多層結構或者單層結構。例如，每個元件1111包括：鎳層，金層，鈀層，銅層或他們的組合。
該第一柱層112將該第一導電層111連接至該第二導電層114。在本發明實施例中，第一柱層112包括：複數個柱形物(pillar)1121。柱形物1121可以由諸如銅等材料形成。每個柱形物1121具有一第一上表面1121u，以及該第一封裝體113具有一第二上表面113u，其中該第一上表面1121u自該第二上表面113u露出並且與該第二上表面113u對齊。
第一封裝體113封裝第一導電層111及第一柱層112。例如，該第一封裝體113封裝該第一導電層111的該第一側面1111s以及每個柱形物1121的側面。
第一封裝體113可以為成型材料(molding compound)，該成型材料例如可以由如下材料製成：酚酫基樹脂(novolac-based resin)，環氧基樹脂，矽基樹脂(silicone-based resin)，或者另一合適的封裝物。第一封裝體113也可以包含合適的填充物，諸如粉未狀的SiO2。
由於第一封裝體113可以為成型材料，因此該封裝基底110可以具有薄的厚度t1。相比於矽基底，封裝基底110的厚度t1係非常小。一般地，矽基底具有大於100μm(微米)的厚度。在本實施例中，由於封裝基底110的厚度t1變小，因此降低了半導體封裝100的厚度。
第二導電層114可以包括：複數個元件1141，諸如接墊，走線或者他們的組合。每個元件1141可以為多層結構或者單層結構。例如，元件1141可以為鎳層，金層，銅層，鈀層或者他們的組合。
在本實施例中，第一電子元件120係以“正面向下”的方向耦接至封裝基底110的第二導電層114，並且經由複數個導電接頭121來電性連接至第二導電層114。導電接頭121可以為錫球，導電柱，等等。
在其他實施例中，第一電子元件120係以“正面向上”的方向耦接至封裝基底110，並且經由複數條導電接合線(未示出)來電性連接封裝基底110。第一電子元件120可以為主動晶片或者被動元件，諸如電阻，電感或者電容。在另一實施例中，第一電子元件120的數量可以為複數個。另外，第一電子元件120例如可以為晶片，被動元件，等等。
第二封裝體130形成於封裝基底110的第二上表面113u上，並且封裝第二導電層114及第一電子元件120。第二封裝體130可以由相同於第一封裝體113的材料形成。
第二電子元件140設置在第一基底110的第一下表面1111b上，並且電性連接第一導電層111。在一個實施例中，第二電子元件140例如為被動元件，諸如電阻，電感或電容。
導電接頭150設置在第一基底110的第一下表面1111b上。半導體封裝100通過導電接頭150設置於一外部電路上並且電性連接該外部電路，諸如電路板。導電接頭150可以為錫球，導電柱，等等。
第2圖為根據本發明另一實施例的一半導體封裝200的結構示意圖。該半導體封裝200包括：上述的封裝基底110，上述的第一電子元件120，上述的第二封裝體130，上述的第二電子元件140，至少一個導電接頭150，一第二柱層260及一插入層270。
該第二封裝體130進一步包括：該第二柱層260。該第二柱層260包括：複數個柱形物261，將該第二導電層114連接至該插入層270。
該插入層270設置在第二封裝體130上並且通過第二柱層260電性連接該封裝基底110，其中該第二柱層260封裝於該第二封裝體130中。該插入層270通過第二柱層260及封裝基底110電性連接該第一電子元件120。
每個柱形物261均具有一第三上表面261u，以及該第二封裝體130具有一第四上表面130u，其中該第三上表面261u自該第四上表面130u露出，並且對齊該第四上表面130u。
第3圖為根據本發明另一實施例的一半導體封裝300的結構示意圖。該半導體封裝300包括：上述的封裝基底110，上述的第一電子元件120，上述的第二封裝體130，上述的第二電子元件140，至少一個導電接頭150，上述的第二柱層260及一第四導電層370。
該第二封裝體130封裝該第二導電層114，該第二柱層260及該第四導電層370。
該第二柱層260將該第二導電層114電性連接至該第四導電層370，使得第一電子元件120可以通過封裝基底110及第二柱層260來電性連接第四導電層370。
該第四導電層370包括：複數個元件371，諸如接墊，走線或者他們的組合。每個元件371均具有一第五上表面371u，以及該第二封裝體130具有第四上表面130u，其中該第五上表面371u自該第四上表面130u中露出，並且對齊該第四上表面130u。
每個元件371可以為多層結構或者單層結構。例如，每個元件371包括：鎳層，金層，鈀層，銅層或者他們的組合。
第四導電層370嵌入於第二封裝體130中。例如，每個元件371(走線或者接墊)具有一第二側面371s，該第二側面371s由第二封裝體130封裝。由於第四導電層370嵌入於第二封裝體130中，因此第二封裝體130具有薄的厚度t3。
第4圖為根據本發明另一實施方式的一半導體封裝400的結構示意圖。該半導體封裝400包括：一封裝基底410，上述的第一電子元件120，上述的第二封裝體130，上述的第二電子元件140，至少一個導電接頭150，上述的第二柱層260及上述的插入層270。
在本實施例中，封裝基底410為多層封裝結構。例如，封裝基底410包括：上述的第一導電層111，上述的第一柱層112，上述的第一封裝體113，上述的第二導電層114，一第三導電層411，一第三柱層412及一第三封裝體413。該第一導電層111，第一柱層112及第一封裝體113共同形成一第一單層封裝結構，以及該第三導電層411，第三柱層412及第三封裝體413形成一第二單層封裝結構。在另一實施例中，封裝基底410的層數可以大於2層。
第三導電層411形成於第一封裝體113的第二上表面113u上並且電性連接該第一柱層112。第三柱層412將該第三導電層411連接至第二導電層114。第三封裝體413封裝第三柱層412及第三導電層411。在本實施例中，第二導電層114形成於第三封裝體413的一第六上表面413u 上並且通過第三導電層411，第三柱層412及第一柱層112來電性連接該第一導電層111。
另外，第三封裝體413可以由與第一封裝體113相同的材料形成。
由於第一封裝體113及第三封裝體413為成型材料，因此封裝基底410具有薄的厚度。相比於矽基底，封裝基底410的厚度t1更小。一般地，矽基底具有大於100μm的厚度。在本實施例中，由於封裝基底410的厚度t1較小，因此降低了半導體封裝100的厚度t2。
第5圖為根據本發明另一實施例的一半導體封裝500的結構示意圖。該半導體封裝500包括：上述的封裝基底410，上述的第一電子元件120，上述的第二封裝體130，上述的第二電子元件140，至少一個導電接頭150，上述的第二柱層260及上述的第四導電層370。
在本實施例中，由於第四導電層370嵌入於第二封裝體130中，因此第二封裝體130具有薄的厚度t3。第二柱層260將第二導電層114電性連接至第四導電層370，使得第一電子元件120可以通過封裝基底410及第二柱層260來電性連接第四導電層370。
第6圖為根據本發明一個實施例的一半導體元件10的結構示意圖。該半導體元件10包括：上述的半導體封裝200及一第三電子元件11。在另一實施例中，該第三電子元件11可以為含有複數個晶粒的半導體封裝，例如複數個彼此堆疊的DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)晶粒。
該第三電子元件11係以“正面向下”的方向設置在半導體封裝200的插入層270上，並且經由複數個導電接頭115電性連接插入層270。導電接頭115可以為錫球，導電柱，等等。在另一實施例中，第三電子元件11係以“正面向上”的方向設置在插入層270上，並且經由複數條導電接合線(未示出)電性連接插入層270。第三電子元件11通過插入層270，第二柱層260及封裝基底110來電性連接第一電子元件120。另外，第三電子元件11通過插入層270，第二柱層260及封裝基底110來電性連接導電接頭150。
第7圖為根據本發明另一實施例的一半導體元件20的結構示意圖。該半導體元件20包括：上述的半導體封裝300及一第三電子元件11。
該第三電子元件11係以“正面向下”或“正面向上”的方向設置在半導體封裝300的第四導電層370上。第三電子元件11通過第四導電層370，第二柱層260及封裝基底110來電性連接第一電子元件120。另外，第三電子元件11通過第四導電層370，第二柱層260及封裝基底110來電性連接導電接頭150。
在另一實施例中，第三電子元件11可以設置在第4圖所示的半導體封裝400的插入層270上，以形成另一半導體元件。在其他實施例中，第三電子元件11可以設置在第5圖的半導體封裝500的第四導電層370上，以形成另一半導體元件。
第8A~8H圖示意了第1圖中的半導體封裝100的製造製程。
參考第8A圖，提供一載體180。該載體180可以由含有銅、鐵或鋼的金屬板形成。
參考第8A圖，例如使用微影(photolithography)、化學鍍(electroless plating)，電鍍，印刷，濺射(sputtering)，真空沉積(vacuum deposition)等方式於第一載體180上形成第一導電層111。
參考第8B圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第一導電層111上形成第一柱層112。
參考第8C圖，於載體180的一上表面180u上形成封裝第一導電層111及第一柱層112的第一封裝體113。第一封裝體113可以由各式封裝技術形成，諸如壓縮成型(compression molding)，注射成型(injection molding)，傳遞模塑(transfer molding)或者點膠技術(dispensing technology)。
在本實施例中，研磨第一封裝體113，使得每個柱形物1121的第一上表面1121u自第一封裝體113的第二上表面113u露出，其中第一上表面1121u對齊第二上表面113u。
參考第8D圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第一柱層112上形成第二導電層114。第一導電層111，第一柱層112，第一封裝體113及第二封裝體114形成封裝基底110。
參考第8E圖，例如通過使用SMT(Surface Mount Technology，表面貼裝技術)來將第一電子元件120通過導電接頭121設置在封裝基底110的第二導電層114上。
參考第8F圖，於封裝基底110上形成第二封裝體130，該第二封裝體130封裝第一電子元件120及第二導電層114。第二封裝體130可以由各式封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
參考第8G圖，例如使用蝕刻，剝離等方式來移除載體180。在移除了載體180之後，露出第一導電層111的第一下表面1111b以及第一封裝體113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此對齊。例如，第一下表面1111b及第二下表面113b共平面。
參考第8H圖，例如使用球安裝技術來在第一導電層111的第一下表面1111b上形成導電接頭150。另外，使用SMT來將第二電子元件140設置於第一導電層111的第一下表面1111b上。
第9A~9B圖示意了第2圖的半導體封裝200的製造製程。
參考第9A圖，插入層270通過第二柱層260連接封裝基底110。插入層270可以通過第二柱層260及封裝基底110電性連接第一電子元件120。
參考第9B圖，第二封裝體130封裝第一電子元件120，第二導電層114及第二柱層260，並且該第二封裝體130形成於封裝基底110及插入層270之間。第二封裝體130可以由各式封裝技術來形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
接著，參考第9B圖，移除載體180。在載體180移除之後，露出第一導電層111的第一下表面1111b及第一封裝體113的第二下表面 113b，其中第一下表面1111b及第二下表面113b彼此對齊。例如，第一下表面1111b及第二下表面113b共平面。
接著，於第一導電層111的第一下表面1111b上形成導電接頭150及第二電子元件140，從而形成第2圖所示的半導體封裝200。
在另一實施例中，將第6圖所示的第一電子元件11設置在第9B圖的插入層270上，從而形成第6圖的半導體元件10。
第10A~10C圖示意了第3圖中的半導體封裝300的製造製程。
參考第10A圖，於載體190上形成第四導電層370，該第四導電層370通過第二柱層260連接封裝基底110。第四導電層370通過第二柱層260及封裝基底110電性連接第一電子元件120。
參考第10B圖，第二封裝體130封裝第一電子元件120，第二導電層114，第二柱層260及第四導電層370，並且第二封裝體130形成於封裝基底110及載體190之間。第二封裝體130可以由各式封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
參考第10C圖，移除載體190以露出第二封裝體130的第四上表面130u及第四導電層370的第五上表面371u，其中第四上表面130u及第五上表面371u彼此對齊。
參考第10C圖，移除載體180。在移除了載體180之後，露出第一導電層111的第一下表面1111b及第一封裝體113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此對齊。例如，第一下表面1111b及第二下表面113b係共平面。
接著，在第一導電層111的第一下表面1111b上形成導電接頭150及第二電子元件140，從而形成第3圖的半導體封裝300。
在另一實施例中，第7圖中的第三電子元件11可以設置在第10C圖的第四導電層370上，以形成第7圖所示的半導體元件20。
第11A~11H圖示意了第4圖的半導體封裝400的製造製程。
參考第11A圖，提供了一載體180。該載體180可以由含銅、鐵或鋼的金屬板形成。
參考第11A圖，使用如上所提及的製程在載體180上形成第一導電層111，第一柱層112及第一封裝體113。
參考第11B圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第一柱層112上形成第三導電層411。
參考第11B圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第三導電層411上形成第三柱層412。
參考第11C圖，第三封裝體413封裝第三導電層411及第三柱層412，並且第三封裝體413形成於第一封裝體113的第二上表面113u上。第三封裝體413可以由各式封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
在本實施例中，研磨第三封裝體413，使得第三柱層412的上表面412u從第三封裝體413的第六上表面413u露出，其中上表面412u對齊第六上表面413u。
參考第11D圖，例如使用微影、化學鍍，電鍍，印刷，濺射，真空沉積等方式來在第三柱層412上形成第二導電層114。第一導電層111，第一柱層112，第一封裝體113，第二導電層114，第三導電層411，第三柱層412及第三封裝體413形成封裝基底410。
參考第11E圖，通過使用SMT來使第一電子元件120通過導電接頭121設置在封裝基底410的第二導電層114上。
參考第11F圖，插入層270通過第二柱層260來連接封裝基底410。插入層270可以通過第二柱層260及封裝基底410來電性連接第一電子元件120。
參考第11G圖，第二封裝體130封裝第一電子元件120，第二導電層114及第二柱層260，並且第二封裝體130形成於封裝基底410及插入層270之間。第二封裝體130可以由各式封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
參考第11H圖，使用蝕刻，剝離等方式來移除載體180。在移除了載體180之後，露出第一導電層111的第一下表面1111b及第一封裝體113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此對齊。例如，第一下表面1111b及第二下表面113b共平面。
接著，在第一導電層111的第一下表面1111b上形成導電接頭150及第二電子元件140，以形成第4圖所示的半導體封裝400。
在另一實施例中，將第6圖的第三電子元件11設置在第11H圖中的插入層270上，以形成另一半導體元件。
第12A~12C圖示意了第5圖的半導體封裝500的製造製程。
參考第12A圖，於載體190上形成第四導電層370，該第四導電層370通過第二柱層260連接封裝基底410。第四導電層370可以通過第二柱層260及封裝基底410電性連接第一電子元件120。
參考第12B圖，第二封裝體130封裝第一電子元件120，第二導電層114，第二柱層260及第四導電層370，其中第二封裝體130形成於封裝基底410及載體190之間。第二封裝體130可以由各式封裝技術形成，諸如壓縮成型，注射成型，傳遞模塑或者點膠技術。
參考第12C圖，移除載體190以露出第二封裝裝體130的第四上表面130u及第四導電層370的第五上表面371u，其中第四上表面130u及第五上表面371u彼此對齊。例如，其中第四上表面130u及第五上表面371u共平面。
參考第12C圖，移除載體180。在載體180被移除之後，露出第一導電層111的第一下表面1111b及第一封裝體113的第二下表面113b，其中第一下表面1111b及第二下表面113b係彼此對齊。例如，第一下表面1111b及第二下表面113b共平面。
接著，於第一導電層111中的第一下表面1111b上形成導電接頭150及第二電子元件140，以形成第5圖的半導體封裝500。
在另一實施例中，第7圖中的第三電子元件11設置在第12C圖中的第四導電層370上，以形成另一半導體元件。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
100‧‧‧半導體封裝
110‧‧‧封裝基底
120‧‧‧第一電子元件
130‧‧‧第二封裝體
140‧‧‧第二電子元件
150、121‧‧‧導電接頭
111‧‧‧第一導電層
112‧‧‧第一柱層
113‧‧‧第一封裝體
114‧‧‧第二導電層
1111、1141‧‧‧元件
1111b‧‧‧第一下表面
1111s‧‧‧第一側面
113b‧‧‧第二下表面
1121‧‧‧柱形物
1121u‧‧‧第一上表面
113u‧‧‧第二上表面
t1、t2‧‧‧厚度

Claims (13)

  1. 一種半導體封裝，包括：一封裝基底、一第一電子元件以及一第二封裝體；其中，該封裝基底包括：一第一導電層；一第一柱層，形成於該第一導電層上；一第一封裝體，封裝該第一導電層及該第一柱層；以及一第二導電層，電性連接該第一柱層；其中，該第一電子元件設置在該封裝基底的該第二導電層的上方；該第二封裝體封裝該第一電子元件及該第二導電層；其中，該第一封裝體為一成型材料；其中，進一步包括：一第二柱層，形成於該第二導電層上；其中，該第二封裝體進一步封裝該第二柱層。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，該封裝基底進一步包括：一第三導電層，形成於該第一封裝體上；一第三柱層，將該第三導電層連接至該第二導電層；以及一第三封裝體，封裝該第三柱層及該第三導電層；其中，該第二導電層形成於該第三封裝體上。
  3. 如申請專利範圍第2項所述的半導體封裝，其中，該第三封裝體為一成型材料。
  4. 如申請專利範圍第1項所述的半導體封裝，其中，該第一導電層具有一第一下表面，該第一封裝體具有一第二下表面，該第一下表面從該第二下表面露出；以及該半導體封裝進一步包括：一第二電子元件，設置在該第一導電層的該第一下表面上。
  5. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一插入層，設置在該第二封裝體上並且電性連接該封裝基底。
  6. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一第四導電層；該第二柱層，將該第四導電層連接至該第二導電層；其中，該第二封裝體封裝該第二柱層及該第四導電層。
  7. 如申請專利範圍第1項所述的半導體封裝，其中，該第一柱層具有一第一上表面，該第一封裝體具有一第二上表面，以及該第一上表面對齊該第二上表面，及/或，該第一導電層具有一第一下表面，該第一封裝體具有一第二下表面，以及該第一下表面與該第二下表面對齊。
  8. 一種半導體元件，包括：如申請專利範圍第1項、第2項、第3項、第4項或第7項所述的半導體封裝；以及一第三電子元件，設置在該第二封裝體上方並且通過該第二柱層電性連接該封裝基底；其中，該第二封裝體進一步封裝該第二柱層。
  9. 如申請專利範圍第8項所述的半導體元件，其中，進一步包括： 一插入層，設置在該第二封裝體上並且通過該第二柱層電性連接該封裝基底。
  10. 如申請專利範圍第9項所述的半導體元件，其中，該第三電子元件設置該插入層上並電性連接至該插入層。
  11. 如申請專利範圍第8項所述的半導體元件，其中，進一步包括：一第四導電層；該第二柱層將該第四導電層連接至該第二導電層；並且，該第二封裝體封裝該第二柱層及該第四導電層。
  12. 如申請專利範圍第11項所述的半導體元件，其中，該第三電子元件設置在該第四導電層上並電性連接至該第四導電層。
  13. 一種半導體元件的製造方法，其中，包括：提供一載體；形成一封裝基底，包括：於該載體上形成一第一導電層；於該第一導電層上形成一第一柱層；形成第一封裝體來封裝該第一導電層及該第一柱層；以及於該第一柱層上形成一第二導電層；將一第一電子元件設置在該封裝基底的該第二導電層的上方；將一第二柱層連接至該封裝基底；形成一第二封裝體來封裝該第一電子元件，該第二導電層及該第二柱層；移除該載體； 於該第二封裝體上方設置一第三電子元件，其中該第三電子元件通過該第二柱層來電性連接該封裝基底；其中，該第一封裝體為一成型材料。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US9761534B2 (en) 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US10784206B2 (en) 2015-09-21 2020-09-22 Mediatek Inc. Semiconductor package
US10062626B2 (en) 2016-07-26 2018-08-28 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10256114B2 (en) 2017-03-23 2019-04-09 Amkor Technology, Inc. Semiconductor device with tiered pillar and manufacturing method thereof
EP3486943A1 (en) * 2017-11-17 2019-05-22 MediaTek Inc Semiconductor package
US11430739B2 (en) * 2018-10-30 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of package structure with fan-out structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140227832A1 (en) * 2010-07-01 2014-08-14 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US20150044819A1 (en) * 2011-09-09 2015-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures for Semiconductor Devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4787559B2 (ja) * 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8080445B1 (en) * 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9049791B2 (en) * 2013-06-07 2015-06-02 Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd. Terminations and couplings between chips and substrates
TWI534963B (zh) * 2014-02-14 2016-05-21 恆勁科技股份有限公司 封裝裝置及其製作方法
US9034694B1 (en) * 2014-02-27 2015-05-19 Freescale Semiconductor, Inc. Embedded die ball grid array package
KR102198858B1 (ko) * 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US10354974B2 (en) 2014-12-11 2019-07-16 Mediatek Inc. Structure and formation method of chip package structure
US9761534B2 (en) 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140227832A1 (en) * 2010-07-01 2014-08-14 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US20150044819A1 (en) * 2011-09-09 2015-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures for Semiconductor Devices

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