CN106548991A - 半导体封装、半导体元件及其制造方法 - Google Patents

半导体封装、半导体元件及其制造方法 Download PDF

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Publication number
CN106548991A
CN106548991A CN201610614954.0A CN201610614954A CN106548991A CN 106548991 A CN106548991 A CN 106548991A CN 201610614954 A CN201610614954 A CN 201610614954A CN 106548991 A CN106548991 A CN 106548991A
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China
Prior art keywords
layer
conductive layer
packaging body
post
electronic component
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CN201610614954.0A
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Inventor
许文松
林世钦
郑道
张垂弘
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明实施例公开了一种半导体封装、半导体元件及其制造方法。其中该半导体封装包括：封装基底，该封装基底具有第一导电层、柱层、第一封装体和第二导电层。其中，该柱层形成于该第一导电层上。该第一封装体封装该第一导电层及该柱层。其中，该第二导电层电性连接该柱层。另外，该半导体封装还包括：电子元件和第二封装体，该电子元件设置在该封装基底的该第二导电层的上方，并且该第二封装体封装该电子元件及该第二导电层。在本发明实施例中，由于采用封装体来形成封装基底，因此可以降低半导体封装的尺寸。

Description

半导体封装、半导体元件及其制造方法
技术领域
本发明涉及封装技术领域，尤其涉及一种半导体封装、半导体元件及其形成方法。
背景技术
在电子产业中，具有高性能的高整合度(integration)及多功能性已成为新产品的基本要求。同时，由于产品的制造成本与其尺寸成正比，因此高整合度会导致更高的制造成本。因此，对IC(Integrated Circuit，集成电路)封装的小型化要求已变得越来越重要。
因为对于单个封装中的高密度系统整合，PoP(Package-on-package，封装上封装)为成本划算的解决方案，因此PoP为目前发展最快的半导体封装技术。在PoP结构中，可以将各式各样的封装整合于单个半导体封装中以降低其尺寸。因此，业界存在提供一种半导体封装来克服或者至少缓解上述问题的需要。
因此，在增加3D(三维)图像处理电路的性能的同时，降低电源消耗并延长移动设备的工作时间是重要的。
发明内容
有鉴于此，本发明实施例提供一种半导体封装、半导体元件及其制造方法，可以降低其尺寸。
本发明实施例提供了一种半导体封装，包括：封装基底、第一电子元件和第二封装体；其中，该封装基底包括：第一导电层；第一柱层，形成于该第一导电层上；第一封装体，封装该第一导电层及该第一柱层；以及第二导电层，电性连接该第一柱层；其中，该第一电子元件设置在该封装基底的该第二导电层的上方，且该第二封装体封装该第一电子元件及该第二导电层。
其中，该第一封装体和/或该第二封装体为成型材料。
其中，该半导体封装进一步包括：第二柱层，形成于该第二导电层上；并且，该第二封装体进一步封装该第二柱层。
其中，该封装基底进一步包括：第三导电层，形成于该第一封装体上；第三柱层，将该第三导电层连接至该第二导电层；以及第三封装体，封装该第三柱层及该第三导电层；其中，该第二导电层形成于该第三封装体上。
其中，该第三封装体为成型材料。
其中，该第一导电层具有第一下表面，该第一封装体具有第二下表面，该第一下表面从该第二下表面露出；以及该半导体封装进一步包括：第二电子元件，设置在该第一导电层的该第一下表面上。
其中，该半导体封装进一步包括：插入层，设置在该第二封装体上并且电性连接该封装基底。
其中，该半导体封装进一步包括：第四导电层以及第二柱层，该第二柱层将该第四导电层连接至该第二导电层；其中，该第二封装体封装该第二柱层及该第四导电层。
其中，该第一柱层的上表面和该第一封装体的上表面对齐，和/或，该第一导电层的下表面和该第一封装体的下表面对齐。
本发明实施例公开了一种半导体元件，包括：如上所述的半导体封装；第二柱层，形成于该第二导电层上；以及第三电子元件，设置在该第二封装体上方并且通过该第二柱层电性连接该封装基底；其中，该第二封装体进一步封装该第二柱层。
其中，该半导体元件进一步包括：插入层，设置在该第二封装体上并且通过该第二柱层电性连接该封装基底。
其中，该第三电子元件设置该插入层上且电性连接至该插入层。
其中，该半导体元件进一步包括：第四导电层；该第二柱层将该第四导电层连接至该第二导电层；并且，该第二封装体封装该第二柱层及该第四导电层。
其中，该第三电子元件设置在该第四导电层上且电性连接至该第四导电层。
本发明实施例公开了一种半导体封装的制造方法，包括：提供载体；形成封装基底，包括：于该载体上形成第一导电层；于该第一导电层上形成第一柱层；形成第一封装体来封装该第一导电层及该第一柱层；以及于该第一柱层上形成一第二导电层；在该封装基底的该第二导电层的上方设置第一电子元件；形成第二封装体来封装该第一电子元件及该第二导电层；以及移除该载体。
其中，该第一封装体和/或该第二封装体为成型材料。
本发明实施例提供了一种半导体元件的制造方法，包括：提供载体；形成封装基底，包括：于该载体上形成第一导电层；于该第一导电层上形成第一柱层；形成第一封装体来封装该第一导电层及该第一柱层；以及于该第一柱层上形成第二导电层；将第一电子元件设置在该封装基底的该第二导电层的上方；将第二柱层连接至该封装基底；形成第二封装体来封装该第一电子元件、该第二导电层及该第二柱层；移除该载体；以及于该第二封装体上方设置第三电子元件，其中该第三电子元件通过该第二柱层来电性连接该封装基底。
其中，该第一封装体和/或该第二封装体为成型材料。
本发明实施例的有益效果是：
以上的半导体封装、半导体元件及其制造方法，由于采用封装体来形成封装基底，因此可以降低封装基底的厚度，从而降低半导体封装、半导体元件的尺寸。
附图说明
在阅读了下述细节描述及所附的附图之后，本发明的目的和优点对本领域技术人员将更显而易见，其中：
图1为根据本发明实施例的半导体封装的结构示意图；
图2为根据本发明另一实施例的半导体封装的结构示意图；
图3为根据本发明另一实施例的半导体封装的结构示意图；
图4为根据本发明另一实施例的半导体封装的结构示意图；
图5为根据本发明另一实施例的半导体封装的结构示意图；
图6为根据本发明实施例的半导体元件的结构示意图；
图7为根据本发明另一实施例的半导体元件的结构示意图；
图8A至8H示意了图1的半导体封装的制造过程；
图9A至9B示意了图2的半导体封装的制造过程；
图10A至10C示意了图3的半导体封装的制造过程；
图11A至11H示意了图4的半导体封装的制造过程；以及
图12A至12C示意了图5的半导体封装的制造过程。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
图1为根据本发明实施例的半导体封装100的结构示意图。该半导体封装100包括：封装基底110，第一电子元件120，第二封装体130，第二电子元件140及至少一个导电接头(conductive contact)150。
该封装基底110包括：第一导电层111，第一柱层112，第一封装体113及第二导电层114。
该第一导电层111包括：多个元件1111，诸如接垫，走线(trace)或者他们的组合。每个元件1111均具有第一下表面1111b及第一侧面1111s，以及该第一封装体113具有第二下表面113b。该第一下表面1111b自该第二下表面113b露出，以及该第一下表面1111b与该第二下表面113b对齐。每个元件1111可以为多层结构或者单层结构。例如，每个元件1111包括：镍层，金层，钯层，铜层或他们的组合。
该第一柱层112将该第一导电层111连接至该第二导电层114。在本发明实施例中，第一柱层112包括：多个柱形物(pillar)1121。柱形物1121可以由诸或铜等材料形成。每个柱形物1121具有第一上表面1121u，以及该第一封装体113具有第二上表面113u，其中该第一上表面1121u自该第二上表面113u露出并且与该第二上表面113u对齐。
第一封装体113封装第一导电层111及第一柱层112。例如，该第一封装体113封装该第一导电层111的该第一侧面1111s及每个柱形物1121的侧面。
第一封装体113可以为成型材料(molding compound，也可称为“模塑料”)，该成型材料例如可以由如下材料制成：酚酫基树脂(novolac-based resin)，环氧基树脂，硅基树脂(silicone-based resin)，或者另一合适的封装物。第一封装体113也可以包含合适的填充物，诸如粉未状的SiO2。
由于第一封装体113可以为成型材料，因此该封装基底110可以具有薄的厚度t1。相比于硅基底，封装基底110的厚度t1非常小。一般地，硅基底具有大于100μm(微米)的厚度。在本实施例中，由于封装基底110的厚度t1变小，因此降低了半导体封装100的厚度。
第二导电层114可以包括：多个元件1141，诸如接垫，走线或者他们的组合。每个元件1141可以为多层结构或者单层结构。例如，元件1141可以包括：镍层，金层，铜层，钯层或者他们的组合。
在本实施例中，第一电子元件120以“正面向下”的方向耦接至封装基底110的第二导电层114，并且经由多个导电接头121来电性连接至第二导电层114。导电接头121可以为焊球，导电柱，等等。
在其他实施例中，第一电子元件120以“正面向上”的方向耦接至封装基底110，并且通过多条导电接合线(未示出)来电性连接封装基底110。第一电子元件120可以为有源元件(如有源芯片)或者无源元件，诸如电阻，电感或者电容。在另一实施例中，第一电子元件120的数量可以为多个。另外，第一电子元件120例如可以为芯片，无源元件，等等。
第二封装体130形成于封装基底110的第二上表面113u上，并且封装第二导电层114及第一电子元件120。第二封装体130可以由相同于第一封装体113的材料形成，例如第二封装体130可以由成型材料形成。
第二电子元件140设置在第一基底110的第一下表面1111b上，并且电性连接第一导电层111。在一个实施例中，第二电子元件140例如为无源元件，诸如电阻，电感或电容。
导电接头150设置在第一基底110的第一下表面1111b上。半导体封装100通过导电接头150设置于外部电路上并且电性连接该外部电路，诸如电路板。导电接头150可以为焊球(solder ball)，导电柱，等等。
图2为根据本发明另一实施例的半导体封装200的结构示意图。该半导体封装200包括：上述的封装基底110，上述的第一电子元件120，上述的第二封装体130，上述的第二电子元件140，上述的至少一个导电接头150，第二柱层260及插入层270。
该第二封装体130进一步包括：该第二柱层260。该第二柱层260包括：多个柱形物261，将该第二导电层114连接至该插入层270。
该插入层270设置在第二封装体130上并且通过第二柱层260电性连接该封装基底110，其中该第二柱层260封装于该第二封装体130中。该插入层270通过第二柱层260及封装基底110电性连接该第一电子元件120。
每个柱形物261均具有第三上表面261u，以及该第二封装体130具有第四上表面130u，其中该第三上表面261u自该第四上表面130u露出，并且对齐该第四上表面130u。
图3为根据本发明另一实施例的半导体封装300的结构示意图。该半导体封装300包括：上述的封装基底110，上述的第一电子元件120，上述的第二封装体130，上述的第二电子元件140，上述至少一个导电接头150，上述的第二柱层260，及第四导电层370。
该第二封装体130封装该第二导电层114，该第二柱层260及该第四导电层370。
该第二柱层260将该第二导电层114电性连接至该第四导电层370，使得第一电子元件120可以通过封装基底110及第二柱层260来电性连接第四导电层370。
该第四导电层370包括：多个元件371，诸如接垫，走线或者他们的组合。每个元件371均具有第五上表面371u，以及该第二封装体130具有第四上表面130u，其中该第五上表面371u自该第四上表面130u中露出，并且对齐该第四上表面130u。
每个元件371可以为多层结构或者单层结构。例如，每个元件371包括：镍层，金层，钯层，铜层或者他们的组合。
第四导电层370嵌入于第二封装体130中。例如，每个元件371(走线或者接垫)具有第二侧面371s，该第二侧面371s由第二封装体130封装。由于第四导电层370嵌入于第二封装体130中，因此第二封装体130具有薄的厚度t3。
图4为根据本发明另一实施方式的半导体封装400的结构示意图。该半导体封装400包括：封装基底410，上述的第一电子元件120，上述的第二封装体130，上述的第二电子元件140，上述的至少一个导电接头150，上述的第二柱层260及上述的插入层270。
在本实施例中，封装基底410为多层封装结构。例如，封装基底410包括：上述的第一导电层111，上述的第一柱层112，上述的第一封装体113，上述的第二导电层114，第三导电层411，第三柱层412及第三封装体413。该第一导电层111，第一柱层112及第一封装体113共同形成第一单层封装结构，以及该第三导电层411，第三柱层412及第三封装体413形成第二单层封装结构。在另一实施例中，封装基底410的层数可以大于2层。
第三导电层411形成于第一封装体113的第二上表面113u上并且电性连接该第一柱层112。第三柱层412将该第三导电层411连接至第二导电层114。第三封装体413封装第三柱层412及第三导电层411。在本实施例中，第二导电层114形成于第三封装体413的第六上表面413u上并且通过第三导电层411，第三柱层412及第一柱层112来电性连接该第一导电层111。
另外，第三封装体413可以由与第一封装体113相同的材料形成。
由于第一封装体113及第三封装体413可以为成型材料，因此封装基底410具有薄的厚度。相比于硅基底，封装基底410的厚度t1更小。一般地，硅基底具有大于100μm的厚度。在本实施例中，由于封装基底410的厚度t1较小，因此降低了半导体封装100的厚度t2。
图5为根据本发明另一实施例的半导体封装500的结构示意图。该半导体封装500包括：上述的封装基底410，上述的第一电子元件120，上述的第二封装体130，上述的第二电子元件140，上述的至少一个导电接头150，上述的第二柱层260及上述的第四导电层370。
在本实施例中，由于第四导电层370嵌入于第二封装体130中，因此第二封装体130具有薄的厚度t3。第二柱层260将第二导电层114电性连接至第四导电层370，使得第一电子元件120可以通过封装基底410及第二柱层260来电性连接第四导电层370。
图6为根据本发明一个实施例的半导体元件10的结构示意图。该半导体元件10包括：上述的半导体封装200及第三电子元件11。在另一实施例中，该第三电子元件11可以为含有多个晶粒的半导体封装，例如多个彼此堆叠的DRAM(Dynamic Random Access Memory，动态随机存取存储器)晶粒。
该第三电子元件11以“正面向下”的方向设置在半导体封装200的插入层270上，并且经由多个导电接头115电性连接插入层270。导电接头115可以为焊球，导电柱等。在另一实施例中，第三电子元件11以“正面向上”的方向设置在插入层270上，并且经由多条导电接合线(未示出)电性连接插入层270。第三电子元件11通过插入层270，第二柱层260及封装基底110来电性连接第一电子元件120。另外，第三电子元件11通过插入层270，第二柱层260及封装基底110来电性连接导电接头150。
图7为根据本发明另一实施例的半导体元件20的结构示意图。该半导体元件20包括：上述的半导体封装300及第三电子元件11。
该第三电子元件11以“正面向下”或“正面向上”的方向设置在半导体封装300的第四导电层370上。第三电子元件11通过第四导电层370，第二柱层260及封装基底110来电性连接第一电子元件120。另外，第三电子元件11通过第四导电层370，第二柱层260及封装基底110来电性连接导电接头150。
在另一实施例中，第三电子元件11可以设置在图4所示的半导体封装400的插入层270上，以形成另一半导体元件。在其他实施例中，第三电子元件11可以设置在图5的半导体封装500的第四导电层370上，以形成另一半导体元件。
图8A～8H示意了图1中的半导体封装100的制造过程。
参考图8A，提供载体180。该载体180可以由含有铜、铁或钢的金属板形成。
参考图8A，例如使用光刻(photolithography)、化学镀(electroless plating)，电镀，印刷，溅射(sputtering)，真空沉积(vacuum deposition)等方式于第一载体180上形成第一导电层111。
参考图8B，例如使用光刻、化学镀，电镀，印刷，溅射，真空沉积等方式来在第一导电层111上形成第一柱层112。
参考图8C，于载体180的上表面180u上形成封装第一导电层111及第一柱层112的第一封装体113。第一封装体113可以由各式封装技术形成，诸如压缩成型(compressionmolding)，注射成型(injection molding)，传递模塑(transfer molding)或者点胶技术(dispensing technology)。
在本实施例中，研磨第一封装体113，使得每个柱形物1121的第一上表面1121u自第一封装体113的第二上表面113u露出，其中第一上表面1121u对齐第二上表面113u。
参考图8D，例如使用光刻、化学镀，电镀，印刷，溅射，真空沉积等方式来在第一柱层112上形成第二导电层114。第一导电层111，第一柱层112，第一封装体113及第二封装体114形成封装基底110。
参考图8E，例如通过使用SMT(Surface Mount Technology，表面粘贴技术)来将第一电子元件120通过导电接头121设置在封装基底110的第二导电层114上。
参考图8F，于封装基底110上形成第二封装体130，该第二封装体130封装第一电子元件120及第二导电层114。第二封装体130可以由各式封装技术形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
参考图8G，例如使用蚀刻，剥离等方式来移除载体180。在移除了载体180之后，露出第一导电层111的第一下表面1111b以及第一封装体113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此对齐。例如，第一下表面1111b及第二下表面113b共平面。
参考图8H，例如使用球安装(ball mounting)技术来在第一导电层111的第一下表面1111b上形成导电接头150。另外，使用SMT来将第二电子元件140设置于第一导电层111的第一下表面1111b上。
图9A～9B示意了图2的半导体封装200的制造过程。
参考图9A，插入层270通过第二柱层260连接封装基底110。插入层270可以通过第二柱层260及封装基底110电性连接第一电子元件120。
参考图9B，第二封装体130封装第一电子元件120，第二导电层114及第二柱层260，并且该第二封装体130形成于封装基底110及插入层270之间。第二封装体130可以由各式封装技术来形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
接着，参考图9B，移除载体180。在载体180移除之后，露出第一导电层111的第一下表面1111b及第一封装体113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此对齐。例如，第一下表面1111b及第二下表面113b共平面。
接着，于第一导电层111的第一下表面1111b上形成导电接头150及第二电子元件140，从而形成图2所示的半导体封装200。
在另一实施例中，将图6所示的第一电子元件11设置在图9B的插入层270上，从而形成图6的半导体元件10。
图10A～10C示意了图3中的半导体封装300的制造过程。
参考图10A，于载体190上形成第四导电层370，该第四导电层370通过第二柱层260连接封装基底110。第四导电层370通过第二柱层260及封装基底110电性连接第一电子元件120。
参考图10B，第二封装体130封装第一电子元件120，第二导电层114，第二柱层260及第四导电层370，并且第二封装体130形成于封装基底110及载体190之间。第二封装体130可以由各式封装技术形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
参考图10C，移除载体190以露出第二封装体130的第四上表面130u及第四导电层370的第五上表面371u，其中第四上表面130u及第五上表面371u彼此对齐。
继续参考图10C，移除载体180。在移除了载体180之后，露出第一导电层111的第一下表面1111b及第一封装体113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此对齐。例如，第一下表面1111b及第二下表面113b系共平面。
接着，在第一导电层111的第一下表面1111b上形成导电接头150及第二电子元件140，从而形成图3的半导体封装300。
在另一实施例中，图7中的第三电子元件11可以设置在图10C的第四导电层370上，以形成图7所示的半导体元件20。
图11A～11H示意了图4的半导体封装400的制造过程。
参考图11A，提供了载体180。该载体180可以由含铜、铁或钢的金属板形成。
参考图11A，使用如上所提及的工艺在载体180上形成第一导电层111，第一柱层112及第一封装体113。
参考图11B，例如使用光刻、化学镀，电镀，印刷，溅射，真空沉积等方式来在第一柱层112上形成第三导电层411。
参考图11B，例如使用光刻、化学镀，电镀，印刷，溅射，真空沉积等方式来在第三导电层411上形成第三柱层412。
参考图11C，第三封装体413封装第三导电层411及第三柱层412，并且第三封装体413形成于第一封装体113的第二上表面113u上。第三封装体413可以由各式封装技术形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
在本实施例中，研磨第三封装体413，使得第三柱层412的上表面412u从第三封装体413的第六上表面413u露出，其中上表面412u对齐第六上表面413u。
参考图11D，例如使用光刻、化学镀，电镀，印刷，溅射，真空沉积等方式来在第三柱层412上形成第二导电层114。第一导电层111，第一柱层112，第一封装体113，第二导电层114，第三导电层411，第三柱层412及第三封装体413形成封装基底410。
参考图11E，通过使用SMT来使第一电子元件120通过导电接头121设置在封装基底410的第二导电层114上。
参考图11F，插入层270通过第二柱层260来连接封装基底410。插入层270可以通过第二柱层260及封装基底410来电性连接第一电子元件120。
参考图11G，第二封装体130封装第一电子元件120，第二导电层114及第二柱层260，并且第二封装体130形成于封装基底410及插入层270之间。第二封装体130可以由各式封装技术形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
参考图11H，使用蚀刻，剥离等方式来移除载体180。在移除了载体180之后，露出第一导电层111的第一下表面1111b及第一封装体113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此对齐。例如，第一下表面1111b及第二下表面113b共平面。
接着，在第一导电层111的第一下表面1111b上形成导电接头150及第二电子元件140，以形成图4所示的半导体封装400。
在另一实施例中，将图6的第三电子元件11设置在图11H中的插入层270上，以形成另一半导体元件。
图12A～12C示意了图5的半导体封装500的制造过程。
参考图12A，于载体190上形成第四导电层370，该第四导电层370通过第二柱层260连接封装基底410。第四导电层370可以通过第二柱层260及封装基底410电性连接第一电子元件120。
参考图12B，第二封装体130封装第一电子元件120，第二导电层114，第二柱层260及第四导电层370，其中第二封装体130形成于封装基底410及载体190之间。第二封装体130可以由各式封装技术形成，诸如压缩成型，注射成型，传递模塑或者点胶技术。
参考图12C，移除载体190以露出第二封装装体130的第四上表面130u及第四导电层370的第五上表面371u，其中第四上表面130u及第五上表面371u彼此对齐。例如，其中第四上表面130u及第五上表面371u共平面。
参考图12C，移除载体180。在载体180被移除之后，露出第一导电层111的第一下表面1111b及第一封装体113的第二下表面113b，其中第一下表面1111b及第二下表面113b彼此对齐。例如，第一下表面1111b及第二下表面113b共平面。
接着，于第一导电层111中的第一下表面1111b上形成导电接头150及第二电子元件140，以形成图5的半导体封装500。
在另一实施例中，图7中的第三电子元件11设置在图12C中的第四导电层370上，以形成另一半导体元件。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (18)

1.一种半导体封装，其特征在于，包括：封装基底、第一电子元件和第二封装体；
其中，该封装基底包括：第一导电层；第一柱层，形成于该第一导电层上；第一封装体，封装该第一导电层及该第一柱层；以及第二导电层，电性连接该第一柱层；
其中，该第一电子元件设置在该封装基底的该第二导电层的上方，且该第二封装体封装该第一电子元件及该第二导电层。
2.如权利要求1所述的半导体封装，其特征在于，该第一封装体和/或该第二封装体为成型材料。
3.如权利要求1所述的半导体封装，其特征在于，进一步包括：第二柱层，形成于该第二导电层上；其中，该第二封装体进一步封装该第二柱层。
4.如权利要求1所述的半导体封装，其特征在于，该封装基底进一步包括：第三导电层，形成于该第一封装体上；第三柱层，将该第三导电层连接至该第二导电层；以及第三封装体，封装该第三柱层及该第三导电层；其中，该第二导电层形成于该第三封装体上。
5.如权利要求4所述的半导体封装，其特征在于，该第三封装体为成型材料。
6.如权利要求1所述的半导体封装，其特征在于，该第一导电层具有第一下表面，该第一封装体具有第二下表面，该第一下表面从该第二下表面露出；以及该半导体封装进一步包括：第二电子元件，设置在该第一导电层的该第一下表面上。
7.如权利要求1所述的半导体封装，其特征在于，进一步包括：插入层，设置在该第二封装体上并且电性连接该封装基底。
8.如权利要求1所述的半导体封装，其特征在于，进一步包括：第四导电层以及第二柱层，该第二柱层将该第四导电层连接至该第二导电层；其中，该第二封装体封装该第二柱层及该第四导电层。
9.如权利要求1所述的半导体封装，其特征在于，该第一柱层的上表面和该第一封装体的上表面对齐，和/或，该第一导电层的下表面和该第一封装体的下表面对齐。
10.一种半导体元件，其特征在于，包括：
如权利要求1、2、4、5、6或9所述的半导体封装；
第二柱层，形成于该第二导电层上；以及
第三电子元件，设置在该第二封装体上方并且通过该第二柱层电性连接该封装基底；
其中，该第二封装体进一步封装该第二柱层。
11.如权利要求10所述的半导体元件，其特征在于，进一步包括：插入层，设置在该第二封装体上并且通过该第二柱层电性连接该封装基底。
12.如权利要求11所述的半导体元件，其特征在于，该第三电子元件设置该插入层上且电性连接至该插入层。
13.如权利要求10所述的半导体元件，其特征在于，进一步包括：第四导电层；该第二柱层将该第四导电层连接至该第二导电层；并且，该第二封装体封装该第二柱层及该第四导电层。
14.如权利要求13所述的半导体元件，其特征在于，该第三电子元件设置在该第四导电层上且电性连接至该第四导电层。
15.一种半导体封装的制造方法，其特征在于，包括：
提供载体；
形成封装基底，包括：于该载体上形成第一导电层；于该第一导电层上形成第一柱层；形成第一封装体来封装该第一导电层及该第一柱层；以及于该第一柱层上形成一第二导电层；
在该封装基底的该第二导电层的上方设置第一电子元件；
形成第二封装体来封装该第一电子元件及该第二导电层；以及
移除该载体。
16.如权利要求15所述的制造方法，其特征在于，该第一封装体和/或该第二封装体为成型材料。
17.一种半导体元件的制造方法，其特征在于，包括：
提供载体；
形成封装基底，包括：于该载体上形成第一导电层；于该第一导电层上形成第一柱层；形成第一封装体来封装该第一导电层及该第一柱层；以及于该第一柱层上形成第二导电层；
将第一电子元件设置在该封装基底的该第二导电层的上方；
将第二柱层连接至该封装基底；
形成第二封装体来封装该第一电子元件、该第二导电层及该第二柱层；
移除该载体；以及
于该第二封装体上方设置第三电子元件，其中该第三电子元件通过该第二柱层来电性连接该封装基底。
18.如权利要求17所述的制造方法，其特征在于，该第一封装体和/或该第二封装体为成型材料。
CN201610614954.0A 2015-09-21 2016-07-29 半导体封装、半导体元件及其制造方法 Pending CN106548991A (zh)

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