TW201530714A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201530714A
TW201530714A TW103101561A TW103101561A TW201530714A TW 201530714 A TW201530714 A TW 201530714A TW 103101561 A TW103101561 A TW 103101561A TW 103101561 A TW103101561 A TW 103101561A TW 201530714 A TW201530714 A TW 201530714A
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Taiwan
Prior art keywords
substrate
semiconductor package
metal
layer
manufacturing
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TW103101561A
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English (en)
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TWI550791B (zh
Inventor
王隆源
江政嘉
徐逐崎
施嘉凱
黃淑惠
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103101561A priority Critical patent/TWI550791B/zh
Priority to CN201410039516.7A priority patent/CN104795356A/zh
Priority to US14/309,119 priority patent/US9343421B2/en
Publication of TW201530714A publication Critical patent/TW201530714A/zh
Priority to US15/134,037 priority patent/US20160233205A1/en
Application granted granted Critical
Publication of TWI550791B publication Critical patent/TWI550791B/zh

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    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract

一種半導體封裝件及其製法，該製法係包括：接置第一基板於第二基板上，該第一基板之一表面上設有複數第一金屬柱，該第二基板具有相對之第三表面與第四表面，該第三表面上設有晶片，該第一基板藉由該第一金屬柱連接該第二基板之第三表面；於該第一基板與第二基板間形成封裝膠體，令該封裝膠體具有面向該第一基板的第一表面及與其相對之第二表面；以及移除該第一基板。本發明能有效避免銲料橋接現象。

Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種用於堆疊式封裝件之半導體封裝件及其製法。
近年來，由於各種電子產品在尺寸上是日益要求輕、薄及小，因此可節省基板平面面積並可同時兼顧處理性能之堆疊式封裝件(package on package，PoP)愈來愈受到重視。
第1圖所示者係為習知的堆疊式封裝件，如圖所示，該堆疊式封裝件係使用銲球11來作為底層封裝基板12與頂層封裝基板13之間的電性連接用途之互連結構(interconnection)，然而，由於封裝件之輸入/輸出(I/O)的電性連接密度增加，在堆疊封裝件之尺寸不變的情況下，銲球11間的間距必須減小，使得銲球11容易於迴銲時橋接。
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：接置第一基板於第二基板上，其中，該第一基 板之一表面上設有複數第一金屬柱，該第二基板具有其上設有晶片之第三表面與相對於該第三表面之第四表面，供該第一基板藉由該第一金屬柱連接該第二基板之第三表面；於該第一基板與第二基板間形成封裝膠體，令該封裝膠體具有面向該第一基板的第一表面及與其相對之第二表面；以及移除該第一基板。
於前述之製法中，該第三表面上復具有複數電性連接墊，供該第一基板藉由該第一金屬柱對應電性連接該電性連接墊而接置於該第二基板上，該第一基板係包括依序層疊之介電層、第一金屬層與第二金屬層，且該第一金屬柱係設於該第二金屬層上。
依上所述之半導體封裝件之製法，移除該第一基板係包括先移除該介電層與第一金屬層，再移除該第二金屬層，該第一金屬柱之頂端上復設有導電元件，各該電性連接墊上復設有第二金屬柱，以對應電性連接該第一金屬柱。
於本發明之製法中，該第二金屬柱之頂端上復設有導電元件，於移除該第一基板後，復包括於該第一金屬柱上形成有機保焊劑，於移除該第一基板後，復包括於該第四表面上形成複數導電元件。
所述之製法中，該第二基板係包括依序層疊之第一承載板與黏著層，且該第一金屬柱係連接至該黏著層，且於移除該第一基板後，復包括移除該第二基板，並於該第二表面上形成第二線路重佈層，於移除該第一基板後，復包括於該第一表面上形成第一線路重佈層。
又依上所述之半導體封裝件之製法，於形成該第一線路重佈層後，復包括於該第一線路重佈層上接置第二承載板，並移除該 第二基板，於該第二表面上形成第二線路重佈層，移除該第二承載板，於形成該第二線路重佈層後，復包括於該第二線路重佈層上形成複數導電元件。
本發明復提供一種半導體封裝件，其係包括：封裝膠體，係具有相對之第一表面與第二表面；晶片，係嵌埋於該封裝膠體內，且外露於該封裝膠體之第二表面；複數金屬柱，係設於該封裝膠體中，且貫穿該第一表面與第二表面；第一線路重佈層，係形成於該第一表面上，且電性連接該金屬柱；以及第二線路重佈層，係形成於該第二表面上，且電性連接該晶片與金屬柱。
前述之半導體封裝件中，復包括形成於該第二線路重佈層上之複數導電元件。
由上可知，本發明之半導體封裝件及其製法係以金屬柱來電性連接上下基板，該金屬柱所佔的空間較習知技術之銲球小，因此可適用於細間距之封裝需求，並避免銲料橋接。
11‧‧‧銲球
12‧‧‧底層封裝基板
13‧‧‧頂層封裝基板
20‧‧‧第一基板
201‧‧‧介電層
202‧‧‧第一金屬層
203‧‧‧第二金屬層
204‧‧‧第一金屬柱
205、213、24‧‧‧導電元件
21、30‧‧‧第二基板
21a、30a‧‧‧第三表面
21b、30b‧‧‧第四表面
211‧‧‧電性連接墊
212‧‧‧第二金屬柱
22‧‧‧晶片
23‧‧‧封裝膠體
23a‧‧‧第一表面
23b‧‧‧第二表面
25‧‧‧電子元件
2、3‧‧‧半導體封裝件
301‧‧‧第一承載板
302、33‧‧‧黏著層
31‧‧‧第一線路重佈層
32‧‧‧第二承載板
34‧‧‧第二線路重佈層
第1圖係習知堆疊封裝結構之剖視圖；第2A至2I圖係本發明之半導體封裝件之製法的第一實施例及該半導體封裝件之應用例之剖視圖，其中，第2B’圖係第2B圖之另一實施態樣，第2C’與2C”圖係第2C圖之不同實施態樣，第2D’圖係第2D圖之另一實施態樣；以及第3A至3K圖係本發明之半導體封裝件之製法的第二實施例及該半導體封裝件之應用例之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此 技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
請參閱第2A至2I圖，係本發明之半導體封裝件之製法的第一實施例及該半導體封裝件之應用例之剖視圖。
首先，如第2A圖所示，提供一第一基板20，其可包括依序層疊之介電層201、第一金屬層202與第二金屬層203，形成該介電層201之材質可為FR4，該第一金屬層202可為銅層，該第二金屬層203可為銅箔。
如第2B圖所示，於該第一基板20之第二金屬層203上設有複數第一金屬柱204，形成該第一金屬柱204之材質可為銅，且該第一金屬柱204之頂端上復設有導電元件205，例如銲料；或者，如第2B’圖所示，不設有該導電元件205。
如第2C圖所示，提供一第二基板21，其材質例如為BT基板、FR-4基板或陶瓷基板，該第二基板21具有相對之第三表面21a 與第四表面21b，該第三表面21a上設有晶片22，該第三表面21a上復具有複數電性連接墊211；或者，如第2C’圖所示，各該電性連接墊211上復設有第二金屬柱212；或者，如第2C”圖所示，各該第二金屬柱212上復設有導電元件213，例如銲料。
如第2D圖所示，於該第二基板21上接置該第一基板20，該第一基板20藉由該第一金屬柱204對應電性連接該電性連接墊211；或者，如第2D’圖所示，該第一基板20藉由該第一金屬柱204對應電性連接該第二金屬柱212。
如第2E圖所示，其係延續自第2D圖，於該第一基板20與第二基板21間形成封裝膠體23，令該封裝膠體23具有面向該第一基板20的第一表面23a及與其相對之第二表面23b。
如第2F圖所示，以例如剝除的方式移除該介電層201與第一金屬層202。
如第2G圖所示，以例如蝕刻的方式移除該第二金屬層203，以外露該第一金屬柱204，並視需要於該第一金屬柱204上形成有機保焊劑(Organic Solderability Preservative，OSP)(未圖示)。
如第2H圖所示，於該第四表面21b上形成複數導電元件24，至此即完成本發明之半導體封裝件2。
如第2I圖所示，於該第一金屬柱204上接置另一電子元件25，例如封裝結構或其他半導體晶片。
第二實施例
請參閱第3A至3K圖，係本發明之半導體封裝件之製法的第二實施例及該半導體封裝件之應用例之剖視圖。
首先，如第3A圖所示，提供一第二基板30，該第二基板30 係包括依序層疊之第一承載板301與黏著層302，該第二基板30具有相對之第三表面30a與第四表面30b，該第三表面30a上設有晶片22，該第一承載板301之材質例如為玻璃或矽，其型態可為晶圓型(wafer form)或板型(pannel form)。
如第3B圖所示，提供一第一基板20，其可包括依序層疊之介電層201、第一金屬層202與第二金屬層203，形成該介電層201之材質可為FR4，該第一金屬層202可為銅層，該第二金屬層203可為銅箔，於該第一基板20之第二金屬層203上設有複數第一金屬柱204，於該第二基板30上接置該第一基板20，該第一基板20藉由該第一金屬柱204連接至該黏著層302。
如第3C圖所示，於該第一基板20與第二基板30間形成封裝膠體23，令該封裝膠體23具有面向該第一基板20的第一表面23a及與其相對之第二表面23b。
如第3D圖所示，以例如剝除的方式移除該介電層201與第一金屬層202。
如第3E圖所示，以例如蝕刻的方式移除該第二金屬層203，以外露該第一金屬柱204，並視需要於該第一金屬柱204上形成有機保焊劑(Organic Solderability Preservative，OSP)(未圖示)。
如第3F圖所示，於該第一表面23a上形成第一線路重佈層31。
如第3G圖所示，移除該第二基板30。
如第3H圖所示，視需要藉由黏著層33於該第一線路重佈層31上接置第二承載板32。
如第3I圖所示，於該第二表面23b上形成第二線路重佈層34。
如第3J圖所示，於該第二線路重佈層34上形成複數導電元 件24，至此即完成本發明之半導體封裝件3。
如第3K圖所示，於該第一金屬柱204上接置另一電子元件25，例如封裝結構或其他半導體晶片。
本發明復提供一種半導體封裝件，如第3J圖所示，其係包括：封裝膠體23，係具有相對之第一表面23a與第二表面23b；晶片22，係嵌埋於該封裝膠體23內，且外露於該封裝膠體23之第二表面23b；複數第一金屬柱204，係設於該封裝膠體23中，且貫穿該第一表面23a與第二表面23b；第一線路重佈層31，係形成於該第一表面23a上，且電性連接該第一金屬柱204；以及第二線路重佈層34，係形成於該第二表面23b上，且電性連接該晶片22與第一金屬柱204。
前述之半導體封裝件中，復包括形成於該第二線路重佈層34上之複數導電元件24。
綜上所述，相較於習知技術，本發明之半導體封裝件及其製法係以金屬柱來電性連接上下基板，並於形成封裝膠體後移除上基板，由於該金屬柱所佔的空間較銲球小，因此可適用於細間距(fine pitch)之封裝需求，並可避免銲料橋接，進而提高產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
204‧‧‧第一金屬柱
21‧‧‧第二基板
21a‧‧‧第三表面
21b‧‧‧第四表面
211‧‧‧電性連接墊
22‧‧‧晶片
23‧‧‧封裝膠體
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧導電元件
2‧‧‧半導體封裝件

Claims (15)

  1. 一種半導體封裝件之製法，係包括：接置第一基板於第二基板上，其中，該第一基板之一表面上設有複數第一金屬柱，該第二基板具有其上設有晶片之第三表面與相對於該第三表面之第四表面，供該第一基板藉由該第一金屬柱連接該第二基板之第三表面；於該第一基板與第二基板間形成封裝膠體，令該封裝膠體具有面向該第一基板的第一表面及與其相對之第二表面；以及移除該第一基板。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第三表面上復具有複數電性連接墊，供該第一基板藉由該第一金屬柱對應電性連接該電性連接墊而接置於該第二基板上。
  3. 如申請專利範圍第2項所述之半導體封裝件之製法，其中，各該電性連接墊上復設有第二金屬柱，以對應電性連接該第一金屬柱。
  4. 如申請專利範圍第3項所述之半導體封裝件之製法，其中，該第二金屬柱之頂端上復設有導電元件。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一金屬柱之頂端上復設有導電元件。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一基板係包括依序層疊之介電層、第一金屬層與第二金屬層，且該第一金屬柱係設於該第二金屬層上。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，移除該第一基板係包括先移除該介電層與第一金屬層，再移除該 第二金屬層。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除該第一基板後，復包括於該第一金屬柱上形成有機保焊劑。
  9. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除該第一基板後，復包括於該第四表面上形成複數導電元件。
  10. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第二基板係包括依序層疊之第一承載板與黏著層，且該第一金屬柱係連接至該黏著層，且於移除該第一基板後，復包括移除該第二基板，並於該第二表面上形成第二線路重佈層。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，於形成該第二線路重佈層後，復包括於該第二線路重佈層上形成複數導電元件。
  12. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除該第一基板後，復包括於該第一表面上形成第一線路重佈層。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，於形成該第一線路重佈層後，復包括於該第一線路重佈層上接置第二承載板，並移除該第二基板，於該第二表面上形成第二線路重佈層，移除該第二承載板。
  14. 一種半導體封裝件，係包括：封裝膠體，係具有相對之第一表面與第二表面；晶片，係嵌埋於該封裝膠體內，且外露於該封裝膠體之第二表面；複數金屬柱，係設於該封裝膠體中，且貫穿該第一表面與第二表面； 第一線路重佈層，係形成於該第一表面上，且電性連接該金屬柱；以及第二線路重佈層，係形成於該第二表面上，且電性連接該晶片與金屬柱。
  15. 如申請專利範圍第14項所述之半導體封裝件，復包括形成於該第二線路重佈層上之複數導電元件。
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