TW201501265A - 層疊式封裝件及其製法 - Google Patents

層疊式封裝件及其製法 Download PDF

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TW201501265A
TW201501265A TW102121483A TW102121483A TW201501265A TW 201501265 A TW201501265 A TW 201501265A TW 102121483 A TW102121483 A TW 102121483A TW 102121483 A TW102121483 A TW 102121483A TW 201501265 A TW201501265 A TW 201501265A
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package
layer
electrical connection
connection structure
encapsulant
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TW102121483A
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TWI555166B (zh
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王隆源
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矽品精密工業股份有限公司
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Priority to TW102121483A priority Critical patent/TWI555166B/zh
Priority to CN201310262813.3A priority patent/CN104241196B/zh
Priority to US14/077,771 priority patent/US20140367850A1/en
Publication of TW201501265A publication Critical patent/TW201501265A/zh
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Abstract

一種層疊式封裝件及其製法，該層疊式封裝件係包括：第一封裝件，係包括：第一封裝膠體層；第一電性連接結構，係形成於該第一封裝膠體層一側；複數第一導電柱，係形成於該第一封裝膠體層中；及第一半導體晶片，係設於該第一封裝膠體層中，且電性連接該第一電性連接結構；以及第二封裝件，係堆疊於該第一封裝件上，且包括：第二封裝膠體層；第二電性連接結構，係形成於該第二封裝膠體層上；第二半導體晶片，係設於該第二封裝膠體層中，且電性連接該第二電性連接結構；以及複數第二導電柱，係形成於該第二封裝膠體層中，該第一導電柱係電性連接該第二導電柱。本發明可容許較多的輸入輸出(I/O)。

Description

層疊式封裝件及其製法
本發明係有關於一種封裝件及其製法，尤指一種層疊式封裝件及其製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之要求。
第1圖所示者，係習知層疊式封裝件的剖視圖。如圖所示，該層疊式封裝件之上封裝件1的半導體晶片11之所有電極墊(未圖示)需與上封裝基板12四周之電性連接墊121相連接，再以上封裝基板12底面上的第一銲球13電性接合下封裝件2之下封裝基板21上四周之第二銲球22，然後再藉由下封裝基板21底面上之第三銲球23使得該層疊式封裝件可與外界電性接合。
惟，由於該上封裝件1的半導體晶片11之所有電極墊需與上封裝基板12四周之電性連接墊121相連接，且無法以一般印刷技術製作出尺寸在80微米(μm)以下之第一銲球13，因此，當上封裝件1之半導體晶片11係為具有 較多的電極墊的細線寬線距形式(例如28奈米或22奈米製程)之半導體晶片11時，則勢必要增加上封裝基板12四周之面積，且該上封裝件1的銲線14具有弧高與弧長之限制，致使該等電性連接墊121之佈設靈活性受限於該銲線14之打線範圍，且該層疊式封裝件的厚度亦難以降低，即使上封裝件1的半導體晶片11使用覆晶(flip chip)方式電性接合，亦必須透過該第一銲球13以電性連接下封裝件2，而同樣需要增加上封裝基板12四周之面積，簡而言之，上封裝件1與下封裝件2係藉由第一銲球13與第二銲球22相互電性連接，導致該上封裝基板12與下封裝基板21的尺寸受限於銲球直徑大小，進而無法滿足人們對於現今電子封裝產品的需求(即輕、薄、短、小)。
因此，如何克服上述習知技術的種種問題，實已成為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種層疊式封裝件之製法，係包括：提供一第一封裝件，其包括：第一封裝膠體層，係具有相對之第一表面與第二表面；第一電性連接結構，係形成於該第一表面；複數第一導電柱，係形成於該第一封裝膠體層中，且其兩端係分別連接該第一電性連接結構與外露於第二表面；及第一半導體晶片，係設於該第一封裝膠體層中，且電性連接該第一電性連接結構；以及於該第一封裝件上堆疊第二封裝件，該第二封裝件係包括：第二封裝膠體層，係具有相對之第三表 面與第四表面；第二電性連接結構，係形成於該第二封裝膠體層之第三表面或第四表面上；第二半導體晶片，係設於該第二封裝膠體層中，且電性連接該第二電性連接結構；及複數第二導電柱，係形成於該第二封裝膠體層中，且電性連接該第二電性連接結構；其中，該第一導電柱係電性連接該第二導電柱。
本發明復提供一種層疊式封裝件，係包括：第一封裝件，係包括：第一封裝膠體層，係具有相對之第一表面與第二表面；第一電性連接結構，係形成於該第一表面；複數第一導電柱，係形成於該第一封裝膠體層中，且其兩端係分別連接該第一電性連接結構與外露於第二表面；及第一半導體晶片，係設於該第一封裝膠體層中，且電性連接該第一電性連接結構；以及第二封裝件，係堆疊於該第一封裝件上，且包括：第二封裝膠體層，係具有相對之第三表面與第四表面；第二電性連接結構，係形成於該第二封裝膠體層之第三表面或第四表面；第二半導體晶片，係設於該第二封裝膠體層中，且電性連接該第二電性連接結構；及複數第二導電柱，係形成於該第二封裝膠體層中，且電性連接該第二電性連接結構，其中，該第一導電柱係電性連接該第二導電柱。
由上可知，由於本發明係採用導電柱來做為封裝件間的電性連接，且該導電柱的直經(約為50微米)遠小於習知銲球之直經(約為250至300微米)，所以本發明能將電性連接點之間距(pitch)從習知之300至400微米縮減 成約100微米，即本發明之封裝件能容許較多的輸入輸出(I/O)，並有利於整體層疊式封裝件的微小化。
1‧‧‧上封裝件
11‧‧‧半導體晶片
12‧‧‧上封裝基板
121‧‧‧電性連接墊
13‧‧‧第一銲球
14‧‧‧銲線
2‧‧‧下封裝件
21‧‧‧下封裝基板
22‧‧‧第二銲球
23‧‧‧第三銲球
30‧‧‧承載板
31‧‧‧金屬層
32‧‧‧第一線路增層
33‧‧‧第一線路層
34‧‧‧第一導電柱
34a‧‧‧第一金屬塊
34b‧‧‧第二金屬塊
35‧‧‧第一半導體晶片
36‧‧‧第一封裝膠體層
36a‧‧‧第一表面
36b‧‧‧第二表面
37‧‧‧第三電性連接結構
38‧‧‧第一電性連接結構
41‧‧‧第一乾膜
410‧‧‧第一開口
42‧‧‧第二乾膜
420‧‧‧第二開口
50‧‧‧第二封裝膠體層
50a‧‧‧第三表面
50b‧‧‧第四表面
51‧‧‧第二電性連接結構
52‧‧‧第二半導體晶片
53‧‧‧第二導電柱
54‧‧‧第二線路增層
62‧‧‧導電元件
第1圖所示者係習知層疊式封裝件的剖視圖；第2A至2F圖所示者係本發明之層疊式封裝件的第一封裝件之製法之第一實施例的剖視圖；第3A至3E圖所示者係本發明之層疊式封裝件的第一封裝件之製法之第二實施例的剖視圖；第4A至4H圖所示者係本發明之層疊式封裝件的第一封裝件的第一導電柱之製法的剖視圖；第5A至5C圖所示者係本發明之層疊式封裝件的第二封裝件之不同實施例的剖視圖；第6A至6C圖所示者係本發明之層疊式封裝件之不同實施例的剖視圖；以及第7圖所示者係本發明之具有三個封裝件的層疊式封裝件的剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「中」、「端」、「側」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖所示者，係本發明之層疊式封裝件的第一封裝件(下封裝件)之製法之第一實施例的剖視圖。
如第2A圖所示，於承載板30上形成金屬層31，形成該承載板30之材質係為玻璃，形成該金屬層31之材質係為銅。
如第2B圖所示，於該金屬層31上形成第一線路增層32，並於該第一線路增層32上形成第一線路層33。
如第2C圖所示，於該第一線路層33上形成複數第一導電柱34。
如第2D圖所示，於該第一線路層33上覆晶接置第一半導體晶片35，該第一半導體晶片35之數量可為複數，且該第一半導體晶片35亦可為堆疊式半導體晶片組。
如第2E圖所示，於該第一線路增層32上形成包覆該第一半導體晶片35與第一導電柱34的第一封裝膠體層36，且該第一導電柱34之一端係外露於該第一封裝膠體層36之表面。
如第2F圖所示，於該第一封裝膠體層36上電鍍形成 電性連接該第一導電柱34的第三電性連接結構37，該第三電性連接結構37係包括第三線路層，並移除該承載板30與金屬層31。
請參照第2F圖，本發明所揭露之第一封裝件係包括：第一封裝膠體層36，係具有相對之第一表面36a與第二表面36b；第一電性連接結構38，係形成於該第一表面36a，且該第一電性連接結構38係包括第一線路層33及形成於其上的第一線路增層32；複數第一導電柱34，係形成於該第一封裝膠體層36中，且其兩端係分別連接該第一電性連接結構38與外露於第二表面36b；第一半導體晶片35，係設於該第一封裝膠體層36中，且電性連接該第一電性連接結構38；以及第三電性連接結構37，係形成於該第二表面36b。
第3A至3E圖所示者，係本發明之層疊式封裝件的第一封裝件(下封裝件)之製法之第二實施例的剖視圖。
如第3A圖所示，提供一第一線路增層32，且於該第一線路增層32上形成有該第一線路層33，將該第一線路增層32形成有該第一線路層33之側的相對側接置於一承載板30上的金屬層31上。
至於第3B至3E圖之步驟係大致相同於第2C至2F圖，故不在此贅述。
第4A至4H圖所示者，係本發明之層疊式封裝件的第一封裝件的第一導電柱之製法的剖視圖。
若該第一導電柱34高度小於100微米，則僅需使用一 般之電鍍等方式來形成，但是若該第一導電柱34之高度大於200微米，則建議用以下之雙重電鍍(double plating)方式來形成。
如第4A圖所示，提供如第2B圖之結構。
如第4B圖所示，於該第一線路增層32與第一線路層33上形成第一乾膜41。
如第4C圖所示，以例如曝光、顯影等方式於該第一乾膜中形成複數外露部分該第一線路層33的第一開口410。
如第4D圖所示，於各該第一開口410中形成第一金屬塊34a。
如第4E圖所示，於該第一乾膜41上形成第二乾膜42。
如第4F圖所示，於該第二乾膜42中形成複數對應外露該第一金屬塊34a的第二開口420。
如第4G圖所示，於各該第二開口420中形成連接該第一金屬塊34a的第二金屬塊34b，且該第一金屬塊34a與第二金屬塊34b係構成該第一導電柱34。
如第4H圖所示，移除該第二乾膜42與第一乾膜41。
第5A至5C圖所示者，係本發明之層疊式封裝件的第二封裝件(上封裝件)之不同實施例的剖視圖，其製法與第一封裝件類似，故不在此贅述。
如圖所示，第二封裝件係包括：第二封裝膠體層50，係具有相對之第三表面50a與第四表面50b；第二電性連接結構51，係形成於該第二封裝膠體層50之第三表面50a 或第四表面50b，該第二電性連接結構51係包括第二線路層；第二半導體晶片52，係設於該第二封裝膠體層50中，且以例如覆晶或打線方式電性連接該第二電性連接結構51，該第二半導體晶片52之數量可為複數，且該第二半導體晶片52亦可為堆疊式半導體晶片組；以及複數第二導電柱53，係形成於該第二封裝膠體層50中，且電性連接該第二電性連接結構51。
於前述之第二封裝件中，該第二電性連接結構51係形成於該第二封裝膠體層50之第三表面50a上，復可包括形成於該第二封裝膠體層50之第四表面50b上的第二線路增層54。
第6A至6C圖所示者，係本發明之層疊式封裝件之不同實施例的剖視圖。
如圖所示，該第二封裝件係堆疊於該第一封裝件上，且該第一封裝件的第一導電柱34係電性連接該第二封裝件的第二導電柱53。
於前述之層疊式封裝件中，復可包括形成於該第一封裝件與第二封裝件之間的例如為錫膏的銲料膏(未圖示)，且該第一導電柱34係藉由該銲料膏電性連接該第二導電柱53。
所述之層疊式封裝件中，該第一線路增層32上復可設置複數例如銲球的導電元件62。
第7圖所示者，係本發明之具有三個封裝件的層疊式封裝件的剖視圖，亦即於該第二封裝件上可再堆疊另一封 裝件(第三封裝件)，且堆疊封裝件的數量並不以此為限。
綜上所述，由於本發明係採用導電柱來做為封裝件間的電性連接，且該導電柱的直經(約為50微米)遠小於習知銲球之直經(約為250至300微米)，所以本發明能將電性連接點之間距(pitch)從習知之300至400微米縮減成約100微米，即本發明之封裝件能容許較多的輸入輸出(I/O)，並有利於整體層疊式封裝件的微小化。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
32‧‧‧第一線路增層
33‧‧‧第一線路層
34‧‧‧第一導電柱
35‧‧‧第一半導體晶片
36‧‧‧第一封裝膠體層
37‧‧‧第三電性連接結構
38‧‧‧第一電性連接結構
50‧‧‧第二封裝膠體層
51‧‧‧第二電性連接結構
52‧‧‧第二半導體晶片
53‧‧‧第二導電柱
54‧‧‧第二線路增層
62‧‧‧導電元件

Claims (19)

  1. 一種層疊式封裝件之製法，係包括：提供一第一封裝件，其包括：第一封裝膠體層，係具有相對之第一表面與第二表面；第一電性連接結構，係形成於該第一表面；複數第一導電柱，係形成於該第一封裝膠體層中，且其兩端係分別連接該第一電性連接結構與外露於第二表面；及第一半導體晶片，係設於該第一封裝膠體層中，且電性連接該第一電性連接結構；以及於該第一封裝件上堆疊第二封裝件，該第二封裝件係包括：第二封裝膠體層，係具有相對之第三表面與第四表面；第二電性連接結構，係形成於該第二封裝膠體層之第三表面或第四表面上；第二半導體晶片，係設於該第二封裝膠體層中，且電性連接該第二電性連接結構；及複數第二導電柱，係形成於該第二封裝膠體層中，且電性連接該第二電性連接結構；其中，該第一導電柱係電性連接該第二導電柱。
  2. 如申請專利範圍第1項所述之層疊式封裝件之製法，其中，該第一電性連接結構係包括第一線路層及形成於其上的第一線路增層。
  3. 如申請專利範圍第1項所述之層疊式封裝件之製法，其中，該第二電性連接結構係包括第二線路層。
  4. 如申請專利範圍第1項所述之層疊式封裝件之製法，復包括於該第二封裝件上堆疊第三封裝件。
  5. 如申請專利範圍第2項所述之層疊式封裝件之製法，其中，該第一封裝件復包括第三電性連接結構，其係形成於該第二表面。
  6. 如申請專利範圍第5項所述之層疊式封裝件之製法，其中，該第三電性連接結構係包括第三線路層。
  7. 如申請專利範圍第5項所述之層疊式封裝件之製法，其中，形成該第一封裝件之步驟係包括：提供一具有金屬層之承載板；於該金屬層上形成該第一線路增層；於該第一線路增層上形成該第一線路層；於該第一線路層上形成該等第一導電柱；於該第一線路層上接置該第一半導體晶片；於該第一線路增層上形成包覆該第一半導體晶片與第一導電柱的該第一封裝膠體層，且該第一導電柱之一端係外露於該第一封裝膠體層之表面；於該第一封裝膠體層上形成電性連接該第一導電柱的該第三電性連接結構；以及 移除該承載板與金屬層。
  8. 如申請專利範圍第5項所述之層疊式封裝件之製法，其中，形成該第一封裝件之步驟係包括：提供一該第一線路增層，且於該第一線路增層上形成有該第一線路層；將該第一線路增層形成有該第一線路層之側的相對側接置於一承載板上的金屬層上；於該第一線路層上形成該等第一導電柱；於該第一線路層上接置該第一半導體晶片；於該第一線路增層上形成包覆該第一半導體晶片與第一導電柱的該第一封裝膠體層，且該第一導電柱之一端係外露於該第一封裝膠體層之表面；於該第一封裝膠體層上形成電性連接該第一導電柱的該第三電性連接結構；以及移除該承載板與金屬層。
  9. 如申請專利範圍第7或8項所述之層疊式封裝件之製法，其中，形成該第一導電柱之步驟係包括：於該第一線路增層與第一線路層上形成第一乾膜；於該第一乾膜中形成複數外露部分該第一線路層的第一開口；於各該第一開口中形成第一金屬塊；於該第一乾膜上形成第二乾膜；於該第二乾膜中形成複數對應外露該第一金屬塊 的第二開口；於各該第二開口中形成連接該第一金屬塊的第二金屬塊，且該第一金屬塊與第二金屬塊係構成該第一導電柱；以及移除該第二乾膜與第一乾膜。
  10. 如申請專利範圍第1項所述之層疊式封裝件之製法，其中，該第一導電柱係藉由形成於該第一封裝件與第二封裝件之間的銲料膏電性連接該第二導電柱。
  11. 如申請專利範圍第1項所述之層疊式封裝件之製法，其中，該第二電性連接結構係形成於該第二封裝膠體層之第三表面上，該第二封裝件復包括形成於該第二封裝膠體層之第四表面上的第二線路增層，且該第二封裝件藉由該第二線路增層電性連接該第一封裝件。
  12. 一種層疊式封裝件，係包括：第一封裝件，係包括：第一封裝膠體層，係具有相對之第一表面與第二表面；第一電性連接結構，係形成於該第一表面；複數第一導電柱，係形成於該第一封裝膠體層中，且其兩端係分別連接該第一電性連接結構與外露於第二表面；及第一半導體晶片，係設於該第一封裝膠體層中，且電性連接該第一電性連接結構；以及 第二封裝件，係堆疊於該第一封裝件上，且包括：第二封裝膠體層，係具有相對之第三表面與第四表面；第二電性連接結構，係形成於該第二封裝膠體層之第三表面或第四表面；第二半導體晶片，係設於該第二封裝膠體層中，且電性連接該第二電性連接結構；及複數第二導電柱，係形成於該第二封裝膠體層中，且電性連接該第二電性連接結構，其中，該第一導電柱係電性連接該第二導電柱。
  13. 如申請專利範圍第12項所述之層疊式封裝件，其中，該第一電性連接結構係包括第一線路層及形成於其上的第一線路增層。
  14. 如申請專利範圍第12項所述之層疊式封裝件，其中，該第二電性連接結構係包括第二線路層。
  15. 如申請專利範圍第12項所述之層疊式封裝件，復包括第三封裝件，係堆疊於該第二封裝件上。
  16. 如申請專利範圍第12項所述之層疊式封裝件，其中，該第一封裝件復包括第三電性連接結構，其係形成於該第二表面。
  17. 如申請專利範圍第12項所述之層疊式封裝件，復包括銲料膏，係形成於該第一封裝件與第二封裝件之間，且該第一導電柱係藉由該銲料膏電性連接該第二導電柱。
  18. 如申請專利範圍第14項所述之層疊式封裝件，其中，該第二線路層係形成於該第二封裝膠體層之第三表面上，該第二封裝件復包括形成於該第二封裝膠體層之第四表面上的第二線路增層，且該第二封裝件藉由該第二線路增層電性連接該第一封裝件。
  19. 如申請專利範圍第12項所述之層疊式封裝件，其中，該第一導電柱係由堆疊之第一金屬塊與第二金屬塊所構成。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566330B (zh) * 2015-01-06 2017-01-11 矽品精密工業股份有限公司 電子封裝結構之製法
TWI579984B (zh) * 2016-02-05 2017-04-21 Siliconware Precision Industries Co Ltd 電子封裝件及其製法
TWI830062B (zh) * 2021-06-10 2024-01-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI845129B (zh) * 2022-01-26 2024-06-11 精材科技股份有限公司 晶片封裝體及其製造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102192356B1 (ko) * 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
CN106486453A (zh) * 2015-08-25 2017-03-08 力成科技股份有限公司 一种柱顶互连型态半导体封装构造及其制造方法
TWI569390B (zh) * 2015-11-16 2017-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
WO2017189367A1 (en) * 2016-04-29 2017-11-02 Uniqarta, Inc. Connecting electronic components to substrates
DE102016110862B4 (de) * 2016-06-14 2022-06-30 Snaptrack, Inc. Modul und Verfahren zur Herstellung einer Vielzahl von Modulen
CN107768320A (zh) * 2016-08-18 2018-03-06 恒劲科技股份有限公司 电子封装件及其制法
US10290584B2 (en) * 2017-05-31 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
US10283474B2 (en) 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
TWI766192B (zh) * 2019-10-07 2022-06-01 矽品精密工業股份有限公司 電子封裝件及其製法
CN112768437B (zh) * 2021-04-08 2021-06-18 甬矽电子(宁波)股份有限公司 多层堆叠封装结构和多层堆叠封装结构的制备方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391220B1 (en) * 1999-08-18 2002-05-21 Fujitsu Limited, Inc. Methods for fabricating flexible circuit structures
JP4251421B2 (ja) * 2000-01-13 2009-04-08 新光電気工業株式会社 半導体装置の製造方法
WO2004040648A1 (ja) * 2002-10-30 2004-05-13 Semiconductor Energy Laboratory Co., Ltd. 半導体装置および半導体装置の作製方法
DE10348620A1 (de) * 2003-10-15 2005-06-02 Infineon Technologies Ag Halbleitermodul mit Gehäusedurchkontakten
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US8072059B2 (en) * 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US8133762B2 (en) * 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US20080157327A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package on package structure for semiconductor devices and method of the same
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
JP2008306105A (ja) * 2007-06-11 2008-12-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7799608B2 (en) * 2007-08-01 2010-09-21 Advanced Micro Devices, Inc. Die stacking apparatus and method
US7781877B2 (en) * 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7847382B2 (en) * 2009-03-26 2010-12-07 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8343810B2 (en) * 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US20120049334A1 (en) * 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
JP5462777B2 (ja) * 2010-12-09 2014-04-02 日本特殊陶業株式会社 多層配線基板の製造方法
US9230933B2 (en) * 2011-09-16 2016-01-05 STATS ChipPAC, Ltd Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
JP5902931B2 (ja) * 2011-12-06 2016-04-13 新光電気工業株式会社 配線基板の製造方法、及び、配線基板製造用の支持体
KR20130141927A (ko) * 2012-06-18 2013-12-27 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판 제조 방법
US9478485B2 (en) * 2013-06-28 2016-10-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566330B (zh) * 2015-01-06 2017-01-11 矽品精密工業股份有限公司 電子封裝結構之製法
TWI579984B (zh) * 2016-02-05 2017-04-21 Siliconware Precision Industries Co Ltd 電子封裝件及其製法
TWI830062B (zh) * 2021-06-10 2024-01-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI845129B (zh) * 2022-01-26 2024-06-11 精材科技股份有限公司 晶片封裝體及其製造方法

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