TWI642133B - 電子構件之置放製程及其應用之承載治具 - Google Patents

電子構件之置放製程及其應用之承載治具 Download PDF

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TWI642133B
TWI642133B TW105133869A TW105133869A TWI642133B TW I642133 B TWI642133 B TW I642133B TW 105133869 A TW105133869 A TW 105133869A TW 105133869 A TW105133869 A TW 105133869A TW I642133 B TWI642133 B TW I642133B
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TW201816914A (zh
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黃致明
劉仁超
李子明
張文獻
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矽品精密工業股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67772Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving removal of lid, door, cover
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67778Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers

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Abstract

一種電子構件之置放製程,係將基板設於一承載件上,再將一蓋件設於該承載件上,其中,該蓋件與該基板之間具有間隔,以於進行熱製程時,利用該間隔作為該基板之熱脹縮空間,以釋放熱脹縮的壓力,避免發生基板翹曲問題。本發明復提供一種承載治具。

Description

電子構件之置放製程及其應用之承載治具
本發明係有關一種電子構件之製法,尤指一種電子構件的置放製程及其應用之承載治具。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢,其主要係於同一電子產品上整合越來越多功能,但此同時亦要求電子產品體積輕薄,因此,為配合微小化發展的趨勢,業界遂藉由降低封裝基板之厚度,以達到電子產品多功能、小型化之目的。
然而,薄化後的封裝基板由於剛性較差且易受熱製程影響而變形,導致接置於該封裝基板上覆晶用之凸塊發生虛銲(non-wetting)的機率增加,故對於封裝基板於熱製程中之平整性及應力釋放的問題係藉由蓋件解決。
如第1圖所示,係為習知半導體封裝件4使用承載治具1於覆晶製程之剖面示意圖。首先,將一設有複數晶片41之封裝基板40設於一承載件10上,並將一蓋件11設於該承載件10上並壓蓋該封裝基板40,其中,該晶片41 係透過複數銲錫凸塊410覆晶接置於該封裝基板40上,接著,回銲(Reflow)該些銲錫凸塊410,其中,該封裝基板40雖於受熱後會產生形變,但藉由該蓋件11壓觸該封裝基板40,得以抑制該封裝基板40之外部變形。
惟,習知覆晶製程中,藉由該蓋件11接觸該封裝基板40而限制該封裝基板40變形之方式,亦同時抑制該封裝基板40熱脹縮的空間,使該封裝基板40無法釋放其內部壓力,因而增加該封裝基板40的潛在變形量,以致於當該封裝基板40從該承載治具1中取出時,該封裝基板40的潛在變形量會使該封裝基板40發生翹曲之現象,造成該封裝基板40無法與該銲錫凸塊410有效接觸或接觸結合性不佳。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種應用於電子構件之承載治具,係包括:承載件,係用以承載基板,其中,該基板定義有至少一置放區;以及蓋件,係設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開口。
本發明亦提供一種電子構件之置放製程,係包括:將一基板設於一承載件上,其中,該基板定義有至少一置放區;以及將一蓋件設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開 口。
前述之電子構件之置放製程及其應用之承載治具中,該基板具有複數該置放區,且該蓋件具有複數對應該置放區之開口。
前述之電子構件之置放製程及其應用之承載治具中,該置放區上係設置有電子元件。
前述之電子構件之置放製程及其應用之承載治具中,該電子元件係藉由複數導電元件設於該置放區上。例如,該間隔係大於該導電元件之高度。
前述之電子構件之置放製程及其應用之承載治具中,該蓋件復包含有用以接觸該基板的支撐部。例如,該基板復定義有對應該置放區周圍之切割道,該支撐部之位置係對應該切割道之位置,且該支撐部之寬度係小於或等於該切割道之寬度。
前述之電子構件之置放製程及其應用之承載治具中,該蓋件與該基板間之間隔中復形成有緩衝層。
由上可知,本發明之電子構件之置放製程及其應用之承載治具,主要藉由當該基板設於該承載件上時,該蓋件與該基板之間具有間隔,以於進行回銲作業時,該間隔可作為該基板之熱脹縮空間,使該基板能釋放熱脹縮的壓力,故相較於習知技術,當該基板從本發明之承載治具中取出時,該基板不會發生翹曲之現象,因而能避免該基板與用以接置電子元件之導電元件之間發生接觸不良之問題。
1,2‧‧‧承載治具
10,20‧‧‧承載件
11,21‧‧‧蓋件
210‧‧‧開口
211‧‧‧支撐部
212‧‧‧接腳
3‧‧‧電子構件
30‧‧‧基板
300‧‧‧置放區
31‧‧‧電子元件
310‧‧‧導電元件
32‧‧‧緩衝層
4‧‧‧半導體封裝件
40‧‧‧封裝基板
41‧‧‧晶片
410‧‧‧銲錫凸塊
t‧‧‧間隔
h‧‧‧高度
d,r‧‧‧寬度
S‧‧‧切割道
第1圖係為習知半導體封裝件之覆晶製程的剖面示意圖;第2A及2B圖係為本發明之電子構件之置放製程之剖面示意圖;以及第3A及3B圖係為對應第2B圖的不同實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A圖係為本發明之應用於電子構件之承載治具2的剖面示意圖。
如第2A圖所示,該承載治具2係包括一承載件20以及一蓋件21。
所述之承載件20係用以承載一基板30,且該基板30定義有複數置放區300。
所述之蓋件21係藉由至少一接腳212設於該承載件20上且具有分別對應該置放區300之複數開口210,並於該基板30設於該承載件20上時,該蓋件21與該基板30之間具有間隔t。
第2A至2B圖係為本發明之電子構件3之置放製程之剖面示意圖。
如第2A圖所示,以上述承載治具2為例,將一基板30設於該承載件20上,再將該蓋件21設於該承載件20上,且該蓋件21與該基板30之間具有間隔t。
於本實施例中,該基板30具線路層(未圖示),其係例如為線路結構、無核心層之線路板或具有核心層之線路板。
如第2B圖所示,對應該開口210將複數電子元件31設於該基板30之置放區300上,其中,該電子構件3係包括該基板30與該電子元件31。
於本實施例中,該電子元件31係為主動元件、被動元件或其二者組合等,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。具體地,該電子元件31係以複數如銲錫凸塊或銅柱之導電元件310覆晶結合該基板30之線路層上,且該間隔t係大於該導電元件310之高度h,再回銲該些導電元件310以將該電子元件31固 定於該基板30上。
然而,該電子元件31與該基板30之結合方式係依需求而定,並不限於上述覆晶方式,亦可為扇出方式、打線方式或其它方式。
由於本發明中該蓋件21與該基板30之間具有間隔t,故當該基板30設於該承載件20上,,並進行熱製程(如回銲製程)時,該間隔t可作為該基板30之熱脹縮空間,使該基板30能釋放熱脹縮的壓力,故相較於習知技術,當該基板30從本發明之承載治具2中取出時,該基板30不會發生翹曲之現象,因而能避免該基板30與該導電元件310之間發生接觸不良之問題。
再者,如第3A圖所示,該蓋件21復具有用以接觸該基板30的支撐部211。具體地,該基板30對應該置放區300周圍設有切割道S,該支撐部211之位置係對應該切割道S之位置,且該支撐部211之寬度r係小於或等於該切割道S之寬度d,例如,該切割道S之寬度d係為0.2mm至0.3mm。
又,如第3B圖所示,於該蓋件21與該基板30間之間隔t中亦可形成有緩衝層32,該緩衝層32係為絕緣層,其材質例如為聚亞醯胺(Polyimide,簡稱PI)、聚對二唑苯(Polybenzoxazole,簡稱PBO)或其它高分子材料。
後續,於進行熱製程(如回銲製程)時,該緩衝層32可配合該基板30之熱脹縮而變形,使該基板30能釋放熱脹縮的壓力,故當該基板30從本發明之承載治具2中取出 時,該基板30不會發生翹曲之現象。
綜上所述,本發明之電子構件置放製程及其應用之承載治具,主要藉由當基板設於承載件上時,利用蓋件與該基板之間具有間隔,以於進行熱製程時,該間隔可作為該基板之熱脹縮空間,故當該基板從承載治具中取出時,該基板不會發生翹曲之現象。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。

Claims (12)

  1. 一種應用於電子構件之承載治具,係包括:承載件,係用以承載基板,其中,該基板定義有至少一置放區;以及蓋件,係設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開口,該置放區係用以設置電子元件,以供該電子元件藉由複數導電元件設於該置放區上,且該間隔係大於該導電元件之高度。
  2. 如申請專利範圍第1項所述之承載治具,其中,該基板定義有複數置放區,且該蓋件具有複數對應該置放區之開口。
  3. 如申請專利範圍第1項所述之承載治具,其中,該蓋件復包含有用以接觸該基板的支撐部。
  4. 如申請專利範圍第3項所述之承載治具,其中,該基板復定義有位於該置放區周圍之切割道,其中,該支撐部之位置係對應該切割道之位置。
  5. 如申請專利範圍第4項所述之承載治具,其中,該支撐部之寬度係小於或等於該切割道之寬度。
  6. 如申請專利範圍第1項所述之承載治具,復包括形成於該間隔中的緩衝層。
  7. 一種電子構件之置放製程,係包括:將一基板設於一承載件上,其中,該基板定義有至少一置放區;以及將一蓋件設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開口,該置放區係用以設置電子元件,以供該電子元件藉由複數導電元件設於該置放區上,且該間隔係大於該導電元件之高度。
  8. 如申請專利範圍第7項所述之置放製程,其中,該基板具有複數該置放區,且該蓋件具有複數對應該置放區之開口。
  9. 如申請專利範圍第7項所述之置放製程,其中,該蓋件復包含有用以接觸該基板的支撐部。
  10. 如申請專利範圍第9項所述之置放製程,其中,該基板復定義有位於該置放區周圍之切割道,其中,該支撐部之位置係對應該切割道之位置。
  11. 如申請專利範圍第10項所述之置放製程,其中,該支撐部之寬度係小於或等於該切割道之寬度。
  12. 如申請專利範圍第7項所述之置放製程,其中,該間隔中形成有緩衝層。
TW105133869A 2016-10-20 2016-10-20 電子構件之置放製程及其應用之承載治具 TWI642133B (zh)

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CN201610957213.2A CN107968065A (zh) 2016-10-20 2016-11-03 电子构件的置放制程及其应用的承载治具

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW582083B (en) * 2003-04-17 2004-04-01 Advanced Semiconductor Eng Fixture for die-pull test
TWI247367B (en) * 2004-12-02 2006-01-11 Siliconware Precision Industries Co Ltd Semiconductor package free of carrier and fabrication method thereof
TWI257674B (en) * 2004-09-07 2006-07-01 Siliconware Precision Industries Co Ltd Fabrication method and carrier of semiconductor packages

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6581278B2 (en) * 2001-01-16 2003-06-24 St Assembly Test Service Ltd. Process and support carrier for flexible substrates
CN101236282B (zh) * 2008-02-04 2011-12-21 日月光半导体制造股份有限公司 镜头模组的封装治具及镜头模组的封装方法
KR20120013732A (ko) * 2010-08-06 2012-02-15 삼성전자주식회사 범프 리플로우 장치 및 이를 이용한 범프 형성 방법
US8104666B1 (en) * 2010-09-01 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compressive bonding with separate die-attach and reflow processes
US8373269B1 (en) * 2011-09-08 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Jigs with controlled spacing for bonding dies onto package substrates
JP5865639B2 (ja) * 2011-09-15 2016-02-17 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法
JP5853525B2 (ja) * 2011-09-16 2016-02-09 富士電機株式会社 半導体チップの位置決め治具及び半導体装置の製造方法
US8809117B2 (en) * 2011-10-11 2014-08-19 Taiwain Semiconductor Manufacturing Company, Ltd. Packaging process tools and packaging methods for semiconductor devices
US10109612B2 (en) * 2013-12-13 2018-10-23 Taiwan Semiconductor Manufacturing Company Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices
KR101776449B1 (ko) * 2014-09-27 2017-09-07 인텔 코포레이션 단방향성 가열을 갖는 강화 유리를 이용한 기판 휘어짐 제어
CN204391051U (zh) * 2014-12-09 2015-06-10 南通富士通微电子股份有限公司 半导体倒装回流焊夹具

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW582083B (en) * 2003-04-17 2004-04-01 Advanced Semiconductor Eng Fixture for die-pull test
TWI257674B (en) * 2004-09-07 2006-07-01 Siliconware Precision Industries Co Ltd Fabrication method and carrier of semiconductor packages
TWI247367B (en) * 2004-12-02 2006-01-11 Siliconware Precision Industries Co Ltd Semiconductor package free of carrier and fabrication method thereof

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