1257674 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體封裳件製法及其承載件，尤 f 一種薄型球柵陣列（TFBGA)半導體封裝件製法及其承載 件。 【先前技術】 習知上用以製成球栅陣列封裝件的基板條片係如美 f專利第5,691，242號案所揭露’如第！圖所示，於基板 条片1〇〇上每一封裝單元預置區1〇1間形成槽孔ι〇7 ⑻叫，以利用該槽孔1〇7釋放基板條片ι〇〇於模墨等後續 2步驟中之熱應力，避免基板條片1〇〇因該熱應力而出 現魅曲。 然而，此類習知設計卻有兩主要缺點；首先， 製程與材料成本均極高，故1成太分& 土板之 其成本錄佔封裝件整體成本 /°以上，因而’若為防止翹曲現象而於基板條片1〇〇 上預留多數槽孔107之空㈤，顯然將造成基板條片刚面 積的大幅增加；且當每一基板條片1〇〇上所預設的封 3 時，所造成的浪f面積亦將愈大，成:為 美國專利第5,776,798號案所揭示之高積集度 片㈣，以充分利用基板上之面積（如第2圖所示），；^ 位面積中的封裝單元預置區1〇1數目，解決成曰： 因此，此類基板條片110已成為今日薄型球拇陣 卜1257674 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a semiconductor package and a carrier thereof, and a method for fabricating a thin ball grid array (TFBGA) semiconductor package and a carrier thereof. [Prior Art] It is known that the substrate strips used to form the ball grid array package are disclosed in Japanese Patent No. 5,691,242. As shown in the figure, a slot ι 7 (8) is formed between each of the package unit pre-sets 1 〇 1 on the substrate strip 1 以 to release the substrate strip ι in the mold ink by using the slot 1 〇 7 Wait for the thermal stress in the subsequent 2 steps to prevent the substrate strip 1 from appearing due to the thermal stress. However, such conventional designs have two major drawbacks. First, the process and material costs are extremely high. Therefore, the cost of the 1% division and the earthboard accounts for the overall cost of the package/° or more. The warping phenomenon leaves a large number of slots 107 on the substrate strip 1 (5), which obviously causes a large increase in the area of the substrate strip; and when each substrate strip 1 is preset on the substrate At 3 o'clock, the resulting area of the wave f will also be larger, as: the high-accumulation piece (4) disclosed in U.S. Patent No. 5,776,798 to make full use of the area on the substrate (as shown in Fig. 2); ^ The number of package unit preset areas in the bit area is 1〇1, which solves the problem: Therefore, such substrate strips 110 have become today's thin ball bucks.
Hne-Pitch Ball Grid Array, TFBGA )封褒件所廣 ^ Π843 6 1257674 基板條片。 一 2而，此一陣列式基板條片110中僅係藉由切割線而、 隔開母一封裝單元預置區1 〇 1，故而，相鄰之封裴單元預 置區101間並未具有可釋放應力之槽孔，此時，若進行例 如回酿硬化製程（p〇st M〇lding Curing，PMC )等後續高溫 二私日守，该基板條片丨i 0將可能因熱應力無法釋放而導致 第3圖所不之翹曲（Warpage)現象；此因該基板11〇之芯層 1 8 的熱膨脹係數（C〇efficient 〇f Thermal Expansi〇n，) 與該拒銲劑層17之熱膨脹係數有所差異，故而在高溫環境馨 下，極易因其不同之熱膨脹量而導致基板100的翹曲變 形，造成晶片11破裂（Crack)，形成製程良率與結構強度 上的一大問題；加以現今薄型球柵陣列（TFBGA)封裝件 所採之基板條片的芯層18厚度已逐漸減小到0 36mm甚至 0.1mm，更使其結構變弱而令拒銲劑層17的收縮熱應力更 =增加，致使基板條片11〇的翹曲愈加嚴重，極易造成後 續製程中卡住傳送機構而產生破壞。 综上所述，如㈣發一種半導體封裝製法及其承載 · 件，以兼顧前述各問題，防止基板輕曲之現象，實已成為 此相關研發領域所迫切待解之課題。 【發明内容】 口此鑒於上述及其他問題，本發明之主要目的在於 提供一種可防止翹曲現象的半導體封裝件製法及其承载 件。 本發明之另一目的在於提供一種可避免晶片受力而 7 17843 1257674 破壞的半導體封農件製法及其承載件。 而可=明之又—目的在於提供—種無需改變基板抓計 件承載件之熱應力的半導體封裝件製法及其;載 件製ί達ίΐί及其他目的’本發明所提出之半導體封! 與-相對之第括』:係具有-第-表面 切割道定義_個封二=係 ::，分別形成導電跡線層;於該第= w跡線層上分職設拒銲劑層 數開口以外露出部份導電跡 層;將多數置 =:k0pe_^^ 元預置巴.、隹 接至該第一表面上之封裝單 =及:=r以形成用以包_ 半導體封裝件衣知，以沿該些切割道切割得多數個 同時，本發明所提出之承載件係包括··具有 面=相對之第二表面的芯層，且該第一表面上係以多條 栅才口乂錯的切割道定義出複數個單 成於該第-表面與第二表面上料電跡線層；以及 設於該，-表面與第二表面之導電跡線層上的拒録劑層， 以瓜成夕數開口而外露出部份導電跡線層；於該切割道上 形成土數拒銲劑層之開槽口以外露出該芯層。 月開槽口之見度係小於該切割道之寬度，一般係可 17843 8 1257674 设計為0.1至0.3毫米（麵)之間，且由於該切割道之寬度 -般」系為0.3毫米’故而該開槽口之寬度較佳係可設計： 〇·2毫米。 因此，藉由此一拒銲劑層上的開槽口設計，將可在益 需改，基板佈局與封裝件設計的情況下，同時解決基板麵 曲、/ϋ膠與成本等問題，解決習知技術之困境。 【實施方式】 、以下係藉由特定的具體實施例說明本發明之實施方 =熟習此技藝之人士可由本說明書所揭示之内容輕易地 的明之其他優點與功效。本發明亦可藉由其他不同 =體貫施例加以施行或應用，本說明書中的各項細節亦 硯點與應用’在不_本發明之精 種修飾與變更。 〜分 至本發:所提出之半導體封裝件製法，其步驟係如第从 伟且右’百先’如第4A ®，製備一芯層20 (C㈣， 有一弟一表® 201與一相對之第二表面202,該第一 ==以多條拇格交錯的切割道加定義出複數個 封π 圖示);接著’如第㈣，依據半導體 封衣件所需的線路佈局’ 201盥m彻h 影方式於該第一表面 $ ―表面202上分別形成導電 跡線層21係藉該芯層2 日 性連接;再如第4C、4D:二：1a)(未圖示)而電 _ . . 9Λ1 , ^ 口（弟4C圖係為上視圖），於該第 表面201與弟二表面202之導恭 銲卹Μ π , 之冷私跡線層21上分別敷設拒 ^ ’此拒銲劑層23亦藉由曝光顯影之方式，而分 9 17843 1257674 Γ7Λ個：口以外露出該導電跡線層21之端點；- 電:二=二? f銲劑層23開σ係用以外露出該導 包跡線層21上的銲指部211 (Fin 而 ^ 上的拒銲劑層23開口則係用以外^弟一表面202 的銲球部叫BaliPad)。路出料電跡線層21上 此外，本發明之特徵即在於，該第一表面2〇ι 表面搬上的拒輝劑層23亦分別形成多數個開槽口、30,一 ==切割道:。5上外露出芯層2〇;亦即，令兩兩相鄰 兮、衣早70預置區間，均具有一拒銲劑層開槽口 ％，而使 Μ不致完全覆蓋該芯層20的所有面積，而得 ==隔之開槽口 30釋放該芯層2〇與拒銲劑層23 間的熱應力。 片35接、ti垃t發明之製法係再如第4E圖所示’將多數晶 片35刀別接置且電性連接至該第一表面2〇ι上之 預，區’而使每-封裝單元預置區上均具有一晶片^，且 «亥曰曰片35係可以録線或覆晶之方式電性連接至該封裝單 =預置區，端視封裝件之設計而_示之實施例係採鲜線 =之方式）；再如第4F圖，進行模壓封膠製程，以於該 弟-表面201上形成用以包覆該晶片％的封裝膠體4〇， 並於桓C後進行硬化製程（p〇st M〇ld〜代，pMc)而固化該 封褒膠體40;進而如第扣圖，於該第二表面2〇2上植設 多數銲球45,該些鲜球45係植設於外露出該第二表面2〇2 之拒鮮劑層23的銲球部212上；最後，如第姐圖，進行 切割製程’以沿該些切割道205切割下每一封裝單元預置 17843 10 J257674 Ϊ ^上?^多數個半導體封裝件1，此時，該拒輝劑 廣 、夕數開槽口 30由於係位於該切割道2〇5上， 而亦將一併受到切险， 中。 而不再出現於母一半導體封装件i 前述開槽030之寬度L係小於該切割道2〇5之究产， =係可Γ為w至〇毫米（職)之間1由於該; 道5之見度-般係為〇·3毫米，故而該開槽口 ％ W佳係可設計為0.2毫米；藉由此一設計，更可確二度 該些切割道加切割得多數半導體封裝件1後，該些開槽 口 30可-Μ到切除’而不致出現於最終半導體封裳件成 ^ °此外’亦由於該些開槽σ %位置係對應於該些切割 道205之上，因此，敷設該拒鲜劑層23以形成該些開槽口 3〇時’將無需改變原有之線路佈局，此些特性均為本發明 之優點。 藉由本备明所设計之開槽口 30，當該芯層2〇 契拒U層23間因熱膨脹量不匹配（CTE购細叫而出 現熱應力％ ’该熱應力將於該些開槽口 ％位置被釋放，而· 不致成承載件整體的赵曲變形，亦不致因該變形而壓迫 晶片35 ;同時，由於本發明係藉由該開槽口川達至釋放 熱應力的效果，故而該承載件之芯層2()上將無需如習知技 術般開設貫通槽孔，從而可避免基板條片面積利用率過低 的問題。 另外，本發明所提出之拒銲劑層開槽口 30，其特徵在 於該些開槽口 30的形成位置係對應於該切割道2〇5之位 11 17843 1257674 ，’至於該開槽口 3G的數量與形狀則非本發明 此，該些開槽π 30可如第4C0所 、制，因 錯；惟復可如第5圖所示拇格彼此交錯交 =亥第Γ表面2G1或僅形成於該第二表面加i;或^成 二:刀刮道205上亦不一定均需形成有該開槽口 J僅 兩W份切割道205上形成該拒鲜 而僅 同樣有釋放熱應力之效果。 3〇即可，亦 第4n: ’本發明所提出可避免翹曲的承載件，即如前述 二4D圖所示，包括—具有第—表面加與 a 面202的芯層20,該第一表面2〇ι 弟—表 =二定義出複數個封裝單元丄=—交:: ，、弟一表面202上係分別形成有導電跡線層21，且該 導％跡線層21亦再敷設有一相雀曰节丨a x 係m門 該拒銲劑層23 數開口以外露出部份導電跡線層21，並於該些切 5场成多數拒銲劑層之開槽口⑽以外露出該# 20’從而可藉該些開槽σ 3轉放後續高溫製程中所產生二 熱應力’解決習知承載件的問題。 以上所述者僅剌以朗本發明之具體實例而已，並 非用以限定本發明之可實施範圍，舉凡熟習該項技術者在 未脫離本發明所揭示之精神與技㈣想下所完成之一切等 效修飾或改變’仍應由後述之申請專利範圍所涵蓋。 【圖式簡單説明】 第1圖係習知具槽孔之基板條片示意圖； 第2圖係習知南積集度之基板條片上視圖； 17843 12 1257674 第3圓係習知封裝件之基板產第㈣Η圖係本發明之半 二广 圖；以及 衣件衣法之流程 圖係本發明之半導體封㈣ 樣之上視圖。 戟件另一實施瘦 主要元件符號說明Hne-Pitch Ball Grid Array, TFBGA) Wide range of sealing parts ^ Π 843 6 1257674 Substrate strips. In addition, the array substrate strip 110 is separated from the mother-prepacked unit preset area 1 〇1 by the cutting line, so that the adjacent sealing unit preset area 101 does not have The slot of the stress can be released. At this time, if a subsequent high temperature two-day defensive process such as a p〇st M〇lding Curing (PMC) is performed, the substrate strip 丨i 0 may not be released due to thermal stress. The result is a warpage phenomenon which is not shown in FIG. 3; the coefficient of thermal expansion of the core layer 18 of the substrate 11 (C〇efficient 〇f Thermal Expansi〇n) and the coefficient of thermal expansion of the solder resist layer 17 There is a difference, so in the high temperature environment, it is easy to cause warpage deformation of the substrate 100 due to its different thermal expansion amount, causing the wafer 11 to crack, forming a major problem in process yield and structural strength; Nowadays, the thickness of the core layer 18 of the substrate strip taken by the thin ball grid array (TFBGA) package has been gradually reduced to 0 36 mm or even 0.1 mm, which further weakens the structure and makes the shrinkage thermal stress of the solder resist layer 17 more = The increase causes the warpage of the substrate strip 11 to become more serious. It could easily lead to damage and subsequent processes to produce jammed transfer mechanism. To sum up, as in (4), a semiconductor package manufacturing method and its bearing members are used to take into account the above problems and prevent the substrate from being slightly curved, which has become an urgent issue in the related research and development field. SUMMARY OF THE INVENTION In view of the above and other problems, it is a primary object of the present invention to provide a method of fabricating a semiconductor package and a carrier thereof that can prevent warpage. Another object of the present invention is to provide a semiconductor encapsulant manufacturing method and a carrier thereof which can prevent the wafer from being damaged by the force of 7 17843 1257674. However, it is possible to provide a method for fabricating a semiconductor package which does not require changing the thermal stress of the carrier member of the substrate, and a semiconductor device of the present invention. In contrast, the hexadecimal:-------------------------------------------------------------------------------------------------------------------------- a portion of the conductive trace layer; a plurality of ==k0pe_^^ elements are pre-set, and the package is connected to the first surface = and: = r to form a package for _ semiconductor package The plurality of cutting passes are cut at the same time. The carrier of the present invention comprises: a core layer having a surface=opposing second surface, and the first surface is cut by a plurality of gates. The track defines a plurality of electrical trace layers formed on the first surface and the second surface; and a repellent layer disposed on the conductive trace layer of the surface and the second surface Opening a portion of the conductive trace layer by opening a plurality of openings; forming a notch of the soil resistant layer on the scribe line Expose the core. The visibility of the monthly notch is less than the width of the scribe line, generally 17838 8 1257674 is designed to be between 0.1 and 0.3 mm (face), and since the width of the scribe line is 0.3 mm, it is The width of the slot is preferably designed to be: 〇 2 mm. Therefore, by using the notch design on the solder resist layer, it is possible to solve the problem of substrate surface curvature,/silicone and cost, etc., while solving the problem of substrate layout and package design. The dilemma of technology. [Embodiment] The following is a description of the embodiments of the present invention by way of specific examples. Those skilled in the art can readily appreciate other advantages and functions as disclosed in the present disclosure. The present invention may also be embodied or applied by other different embodiments, and the details of the present specification are also modified and modified. ~ 分至本发: The proposed semiconductor package manufacturing method, the steps are as follows: from the first and the right '100 first' as in 4A ®, to prepare a core layer 20 (C (four), a brother and a table ® 201 and a relative The second surface 202, the first == defines a plurality of sealed π icons in a plurality of ribs that are staggered by the thumb; and then, as in the fourth, according to the circuit layout required for the semiconductor package, '201盥m Forming the conductive trace layer 21 on the first surface $-surface 202 by means of the shadow pattern is connected by the core layer 2; and 4C, 4D: 2: 1a) (not shown) . . . 9Λ1 , ^口(弟4C图为上上图), on the first surface 201 and the second surface 202 of the second layer 202, the cold private trace layer 21 is respectively placed on the cold resist layer 21 Layer 23 is also exposed by exposure, and is divided into 9 17843 1257674 Γ 7 Λ: the end of the conductive trace layer 21 is exposed outside the mouth; - electricity: two = two? f flux layer 23 open σ system to expose the guide The solder finger portion 211 on the envelope layer 21 (the solder resist layer 23 on the Fin and ^ is used as the ball ball portion of the surface 202 is called BaliPad). In addition, the present invention is characterized in that the anti-corrosion agent layer 23 on the surface of the first surface 2〇1 also forms a plurality of notches, 30, one == scribe line :. 5, the outer core layer 2 露出 is exposed; that is, the two adjacent 兮, the clothing early 70 preset intervals, each has a solder resist layer notch %, so that the Μ does not completely cover all areas of the core layer 20 And the notch 30 is released to release the thermal stress between the core layer 2 and the solder resist layer 23. The method of the invention of the chip 35 and the method of the invention is as shown in Fig. 4E, 'the majority of the wafers 35 are connected and electrically connected to the pre-, zone' on the first surface 2'. Each of the unit preset areas has a wafer ^, and the «Hui film 35 series can be electrically connected to the package sheet = preset area by means of recording or flip chip, and the design of the end view package is implemented. For example, the method of the fresh-keeping line=; and, as in FIG. 4F, the molding and sealing process is performed to form the encapsulant 4〇 on the surface-surface 201 for covering the wafer, and after 桓C a curing process (p〇st M〇ld~ generation, pMc) to cure the sealing gel 40; further, as shown in the figure, a plurality of solder balls 45 are implanted on the second surface 2〇2, and the fresh balls are 45 Implanted on the solder ball portion 212 of the anti-friction agent layer 23 exposing the second surface 2〇2; finally, as shown in the second drawing, a cutting process is performed to cut each package unit along the cutting channels 205. 17843 10 J257674 Ϊ ^上? ^ a plurality of semiconductor packages 1 , at this time, the anti-gluing agent wide, the number of slots 30 are located on the cutting lane 2 〇 5, but also And are subject to all risks, in. However, the width L of the aforementioned slot 030 is less than that of the cutting channel 2〇5, and the system can be w between w and 〇 mm (job) 1 due to this; The visibility is generally 〇·3 mm, so the slotted %W can be designed to be 0.2 mm. With this design, it is better to cut the dicing and cutting most of the semiconductor package 1 After that, the notches 30 can be cut off and not appear in the final semiconductor package. Further, since the slots σ % position correspond to the scribe lines 205, therefore, When the stripping agent layer 23 is applied to form the notched openings 3, the original line layout will not need to be changed, and these characteristics are all advantages of the present invention. With the notch 30 designed in the present specification, when the core layer 2 refuses to have a thermal expansion amount mismatch between the U layers 23 (the thermal stress is generated by the CTE purchase), the thermal stress will be grooved. The port % position is released, and does not cause deformation of the entire carrier member, nor does it cause the wafer 35 to be pressed by the deformation; at the same time, since the present invention achieves the effect of releasing thermal stress by the slotted opening, The core layer 2 of the carrier member does not need to have a through hole as in the prior art, thereby avoiding the problem that the substrate strip area utilization rate is too low. In addition, the solder resist layer notch 30 proposed by the present invention is provided. It is characterized in that the positions of the notches 30 are corresponding to the position of the cutting channel 2〇5, 11 17843 1257674, 'the number and shape of the notch 3G are not according to the invention, and the slots π 30 can be as in 4C0, system, wrong; but the complex can be as shown in Figure 5, the staggered crossover = Haidi Γ surface 2G1 or only formed on the second surface plus i; or ^ into two: knife scraping It is not always necessary to form the notch on the 205, and only the two W divisions 205 form the repellent. Only the same effect of releasing thermal stress is also available. 3〇, also 4n: 'The carrier of the present invention which avoids warpage, as shown in the above two 4D drawings, includes - having the first surface plus the a surface The core layer 20 of 202, the first surface 2 〇 表 - Table = 2 defines a plurality of package units 丄 = - intersection::, the other surface 202 is formed with a conductive trace layer 21, and the guide The % trace layer 21 is further provided with a phase 曰 曰 丨 丨 m m m 该 该 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒 拒The #20' is exposed outside the mouth (10) so that the two thermal stresses generated in the subsequent high-temperature process can be transferred by the slots σ3 to solve the problem of the conventional carrier. The above is only a specific example of the invention. However, it is not intended to limit the scope of the invention, and all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and skill of the invention will still be claimed. Covered by the scope. [Simple description of the diagram] Figure 1 is a conventional slotted hole FIG. 2 is a top view of a substrate strip of a conventionally-accepted Nanji; 17843 12 1257674 A substrate of a third circular conventional package (4) is a half-width diagram of the present invention; and a garment The flow chart of the method is a top view of the semiconductor package (four) of the present invention.
1〇〇 1〇7 110 17 20 202 21 212 3〇 40 L 半導體封裝件 基板條片 槽孔 基板條片 拒銲劑層 芯層 弟一表面 導電跡線層 銲球部 開槽〇 封裝膠體 寬度 10基板 1 〇 1 封#留一 η 日衣早兀預置區 晶片 封裝膠體 忽層 11 16 18 201 205 211 23 35 45 第一表面 切割道 銲指部 拒銲劑層 晶片 銲球 】7843 131〇〇1〇7 110 17 20 202 21 212 3〇40 L Semiconductor package substrate strip slot substrate strip solder resist layer core layer surface conductive trace layer solder ball portion slotted 〇 package colloid width 10 substrate 1 〇1 封#留一η 衣衣早兀 Pre-set area chip package colloid layer 11 16 18 201 205 211 23 35 45 First surface dicing road welding finger solder resist layer wafer solder ball]7843 13