CN106158786A - Semiconductor package body and preparation method thereof - Google Patents
Semiconductor package body and preparation method thereof Download PDFInfo
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- CN106158786A CN106158786A CN201510177522.3A CN201510177522A CN106158786A CN 106158786 A CN106158786 A CN 106158786A CN 201510177522 A CN201510177522 A CN 201510177522A CN 106158786 A CN106158786 A CN 106158786A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of semiconductor package body and preparation method thereof, and semiconductor package body includes insulating barrier, chip, thermal interface material, heat radiation lid and reconfiguration line layer.Insulating barrier has receiving opening.Chip is arranged in receiving opening.Chip has active surface, relative to the back side of active surface and connect the side surface at active surface and the back side.Thermal interface material is filled in receiving opening the side surface with at least coating chip and exposes active surface.Reconfiguration line layer is respectively arranged at the both sides of insulating barrier with heat radiation lid.Heat radiation lid is by thermal interface material and chip thermal coupling.Reconfiguration line layer is covered in active surface and the thermal interface material of chip, and reconfiguration line layer is electrically connected with chip.The semiconductor package body of the present invention has good radiating efficiency.
Description
Technical field
The invention relates to a kind of packaging body and preparation method thereof, and in particular to a kind of quasiconductor
Packaging body and preparation method thereof.
Background technology
For meeting the compact demand of electronic product, as the quasiconductor of the core parts of electronic product
Packaging body also develops towards the direction of miniaturization (Miniaturization).In recent years, industry develops a kind of core
The micro-miniaturized semiconductor packaging body of chip size packaging body (Chip Scale Package is called for short CSP), it is special
Point is, the size being approximately equal in size to its chip of aforementioned chip size packages body or slightly larger than its chip
Size.On the other hand, semiconductor package body, in addition to need to being miniaturized dimensionally, also needs to improve integrated level
(integrity) and with the exterior electrical components such as circuit board be electrically connected with used by input/output terminal
The quantity of (Input/Output is called for short I/O), just meets electronic product in high-performance with high processing rate
Demand.Greater number of input/output terminal can be laid on the limited areal of the active surface of chip for asking
Son (I/O), then wafer level semiconductor packaging body, such as crystal wafer chip dimension encapsulation body (Wafer Level
Chip Scale Packaging, is called for short WLCSP) just arise at the historic moment.
The making of existing crystal wafer chip dimension encapsulation body usually first passes through molding processes (molding
Process) make the brilliant back of the body of packing colloid coating chip and connect the side surface of the crystalline substance back of the body, and exposing relatively
Active surface in the crystalline substance back of the body.Afterwards, on the active surface of packing colloid and chip, formation reconfigures line
Road floor, and make the input/output terminal (I/O) on the active surface of chip electrically connect with reconfiguration line layer
Connect.In general, the thickness of the packing colloid formed by molding processes is thicker, and unfavorable wafer scale
The miniaturization of chip size packages body.Additionally, due to the coefficient of heat conduction of packing colloid is relatively low, heat radiation effect
The poorest, therefore heat produced by chip is to be transferred to the external world by reconfiguring circuit mostly, its area of dissipation
Or sinking path is limited, therefore radiating efficiency is the best.The external world cannot be transferred to rapidly in heat and accumulate in crystalline substance
In the case of the inside of circle level chip scale package body, easily cause crystal wafer chip dimension encapsulation body and produce
Warpage (warpage).
Summary of the invention
The present invention provides a kind of semiconductor package body and preparation method thereof, and it can be produced has good dissipating
The semiconductor package body of the thermal efficiency.
The present invention proposes a kind of semiconductor package body, including insulating barrier, chip, thermal interface material, heat radiation
Lid and reconfiguration line layer.Insulating barrier has receiving opening.Chip is arranged in receiving opening.Core
Sheet has active surface, relative to the back side of active surface and connect the side surface at active surface and the back side.
Thermal interface material is filled in receiving opening the side surface with at least coating chip and exposes actively table
Face.Reconfiguration line layer and heat radiation lid are respectively arranged at the both sides of insulating barrier, and heat radiation lid is connect by heat
Gate material and chip thermal coupling.Reconfiguration line layer is covered in active surface and the thermal interface material of chip,
And reconfiguration line layer is electrically connected with chip.
In one embodiment of this invention, the back side of above-mentioned thermal interface material coating chip and side surface.
In one embodiment of this invention, above-mentioned heat radiation lid contacts with insulating barrier and interface material.
In one embodiment of this invention, above-mentioned thermal interface material exposes the back side of chip, and heat radiation
Lid and insulating barrier, thermal interface material and the rear-face contact of chip.
In one embodiment of this invention, above-mentioned insulating barrier has first surface and relative with first surface
Second surface.Heat radiation lid is configured on first surface, and reconfiguration line layer is configured at second surface
On, and the back side of chip trims the first surface in insulating barrier.
In one embodiment of this invention, above-mentioned reconfiguration line layer includes at least one figure being alternately stacked
Case conductive layer and at least one pattern dielectric layer.
In one embodiment of this invention, above-mentioned semiconductor package body also includes multiple soldered ball.These welderings
Ball is electrically connected with chip by reconfiguration line layer.
The present invention proposes the manufacture method of a kind of semiconductor package body, and it comprises the following steps.On carrier
Form heat radiation lid.Heat radiation lid is formed insulating barrier insulating barrier and there is at least one receiving opening to expose
Go out the heat radiation lid of part.Chip it is configured in receiving opening and inserts hot interface in accommodating in opening
Material, so that thermal interface material coating chip and expose the active surface of chip.In insulating barrier, heat
Reconfiguration line layer, wherein reconfiguration line layer and core is formed on the active surface of interface material and chip
Sheet is electrically connected with.
In one embodiment of this invention, the manufacture method of above-mentioned conductor packaging body is additionally included in and reconfigures
Forming multiple soldered ball on line layer, wherein these soldered balls are electrically connected with chip by reconfiguration line layer.
In one embodiment of this invention, the manufacture method of above-mentioned conductor packaging body also includes making dissipating cover
Body is detached from the carrier.
The present invention proposes the manufacture method of a kind of semiconductor package body, and it comprises the following steps.On carrier
Form heat radiation material layer.Heat radiation material layer is formed insulation material layer.Insulation material layer has multiple appearance
Receive opening to expose the heat radiation material layer of part.Multiple chips are respectively arranged at these accommodate in opening
And accommodate in openings in these and insert thermal interface material so that thermal interface material be coated with these chips and
Expose the active surface of these chips.Master at insulation material layer, thermal interface material and these chips
Forming reconfiguration line structure on dynamic surface, wherein reconfiguration line structure includes multiple reconfiguration line layer,
And each reconfiguration line layer is electrically connected with corresponding chip respectively.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor package body also includes that these are heavy
Form many assembly weldings ball on configuration line layer, the most each assembly welding ball respectively by a wherein reconfiguration line layer with
Corresponding chip is electrically connected with.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor package body also includes order heat radiation
Material layer is detached from the carrier.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor package body also includes along in advance
Determine line of cut cutting heat radiation material layer, insulation material layer and reconfiguration line structure, multiple partly lead to be formed
Body packaging body.
Based on above-mentioned, the semiconductor package body of the present invention can be at least coated with by thermal interface material and be positioned at insulation
The side surface of the chip accommodated in opening of layer, and with heat radiation lid contact thermal interface material, thus have
Good radiating efficiency.On the other hand, the manufacture method of semiconductor package body proposed by the invention can be made
Make the above-mentioned semiconductor package body with good radiating efficiency.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 G illustrates the Making programme of the semiconductor package body of one embodiment of the invention；
Fig. 2 is the schematic diagram of the semiconductor package body of another embodiment of the present invention.
Description of reference numerals:
10: carrier；
100,100A: semiconductor package body；
110: heat radiation material layer；
110a: heat radiation lid；
120: insulation material layer；
120a: insulating barrier；
121: accommodate opening；
121a: first surface；
122a: second surface；
130: chip；
131: active surface；
132: the back side；
133: side surface；
140: thermal interface material；
150: reconfiguration line structure；
151: reconfiguration line layer；
151a, 151b: patterned conductive layer；
151c: pattern dielectric layer；
B: soldered ball；
D: spacing；
L: predetermined cuts line.
Detailed description of the invention
Figure 1A to Fig. 1 G illustrates the Making programme of the semiconductor package body of one embodiment of the invention.Refer to
Figure 1A, first provides carrier 10, and forms heat radiation material layer 110 over the carrier 10.For example, carry
The sheet material that body 10 can be constituted by hard material or flexible material, or fractal film is (as heat discharges glue
Film, ultraviolet light release glued membrane or other suitable glued membranes), but the present invention does not makees for the material of carrier 10
Any restriction.Herein, heat radiation material layer 110 is e.g. temporarily fixed by the way of glued
On carrier 10, it is beneficial to the carrying out of successive process.In the present embodiment, heat radiation material layer 110 is permissible
It is to be made up of the metal or metal alloy that aluminum, magnesium, copper, silver, gold or other heat conductivity are good, or
Graphite or other heat conductivity are good etc. that non-metallic material is constituted.
Then, refer to Figure 1B, heat radiation material layer 110 forms insulation material layer 120, the most absolutely
The material of edge material layer 120 can be polyimides (Polyimide), epoxy resin, silicon (Si), Si oxide
(SiOx) or other suitable insulant.Herein, insulation material layer 120 can have multiple receiving opening
121, to expose the heat radiation material layer 110 of part.For example, the making of insulation material layer 120 can
Being first comprehensively to form one layer of insulant in heat radiation material layer 110, then by exposure imaging or
The processing procedures such as laser perforate are formed in the specific region of aforementioned dielectric material and accommodate opening 121, to obtain pattern
The insulation material layer 120 changed.Or be, by ink jet printing, screen painting, showering curtain type printing,
The modes such as spraying printing or dry film attaching, are directly formed in heat radiation material layer 110 and have receiving opening
The insulation material layer 120 of 121, but the present invention is for forming the making side of the insulation material layer 120 of patterning
Method does not make any restriction.
Then, refer to Fig. 1 C, multiple chips 130 are respectively arranged in these receiving openings 121 also
And insert thermal interface material 140 in these accommodate opening 121, wherein thermal interface material 140 can be to lead
Hot glue, heat-conducting cream, conductive adhesive film or heat conduction adhesive tape.It should be noted that, the present invention is not limiting as putting core
Sheet 130 is in accommodating opening 121 and inserts the thermal interface material 140 priority in accommodating opening 121
Sequentially, such as can make the side surface 133 of thermal interface material 140 at least coating chip 130 and expose
The production process of the active surface 131 of chip 130 is the most applicable.
In the present embodiment, it the most first inserts thermal interface material 140 in accommodating in opening 121, then
Chip 130 is inserted in the receiving opening 121 being filled with thermal interface material 140, and make in chip 130
Space D (i.e. chip 130 is maintained relative to the back side 132 and the heat radiation material layer 110 of active surface 131
The back side 132 does not contacts with heat radiation material layer 110).In another embodiment, it is the most first by chip 130
Insert in receiving opening 121, make the back side 132 of chip 130 contact with heat radiation material layer 110.Then,
Hot interface material is inserted in gap between the side surface 133 and the inwall accommodating opening 121 of chip 130
Material 140 is in accommodating in opening 121.In another embodiment, chip 130 is the most first inserted appearance by it
Receive in opening 121, make the back side 132 of chip 130 contact with heat radiation material layer 110.Then, utilize
Heat conduction adhesive tape or conductive adhesive film are pressed into and accommodate in opening 121 by the mode of vacuum pressing-combining.Time if necessary,
The part of the another active surface 131 that heat conduction adhesive tape or conductive adhesive film cover chip 130 removes to expose
Go out active surface 131.
Then, refer to Fig. 1 D, utilize and reconfigure circuit processing procedure at insulation material layer 120, hot interface material
Reconfiguration line structure 150 is formed, wherein on the active surface 131 of material 140 and each chip 130
Reconfiguration line structure 150 includes multiple reconfiguration line layer 151, and each reconfiguration line layer 151
It is electrically connected with corresponding chip 130 respectively.Specifically, each reconfiguration line layer 151 includes handing over
For patterned conductive layer 151a, 151b and pattern dielectric layer 151c of stacking, wherein each reconfigures
Line layer 151 is the active surface 131 connecting corresponding chip 130 with patterned conductive layer 151a, and
The patterned conductive layer 151a of part can contact with thermal interface material 140.On the other hand, patterned dielectric
Layer 151c can expose patterned conductive layer 151b.It should be noted that, reconfiguration line layer e.g. multilamellar
Line construction, the visual actual demand of the number of plies of its circuit and increased and decreased.
Then, refer to Fig. 1 E, carry out planting ball and reflow (reflow) processing procedure to reconfigure circuit at these
Form many assembly weldings ball B, the most each assembly welding ball B on layer 151 and connect the reconfiguration line layer 151 of correspondence respectively
In patterned conductive layer 151b, and then be electrically connected with corresponding chip 130.It is said that in general, soldered ball
The material of B can include stannum or leypewter or lead-free solder.Then, refer to Fig. 1 F, by carrier 10
Remove from heat radiation material layer 110, i.e. separate heat radiation material layer 110 and carrier 10.
Finally, please also refer to Fig. 1 F and Fig. 1 G, along making a reservation between wantonly two adjacent chips 130
Line of cut L carries out singulation processing procedure, to form multiple semiconductor package body 100.For example, cutter
Or laser can cut through heat radiation material layer 110, insulation material layer 120 and weight along predetermined cuts line L
Pattern dielectric layer 151c of layout line line structure 150, mainly not undermine soldered ball B as principle.Extremely
This, the making of semiconductor package body 100 is substantially completed, wherein heat radiation material layer 110 structure after cutting
Become the insulation material layer 120 after the heat radiation lid 110a of semiconductor package body 100, and cutting to constitute partly to lead
The insulating barrier 120a of body packaging body 100.
Owing to, in the manufacturing process of above-mentioned semiconductor package body 100, it may utilize insulation material of patterning
The bed of material 120 (i.e. having the insulation material layer 120 of multiple receiving opening 121) replaces existing molding processes
Used in framework, therefore can remove the part production process in existing semiconductor packages and required from
Accessory, and then contribute to the package thickness of the semiconductor package body 100 of reduction and reduce its cost of manufacture.
Please continue to refer to Fig. 1 G, in the present embodiment, semiconductor package body 100 include dispel the heat lid 110a,
Insulating barrier 120a, chip 130, thermal interface material 140 and reconfiguration line layer 151.Chip 130
It is arranged in the receiving opening 121 of insulating barrier 120a.Thermal interface material 140 is filled in receiving opening 121
In with the side surface 133 of coating chip 130 and the back side 132, and expose active surface 131.Weight
Configuration line layer 151 is respectively arranged at the opposite sides of insulating barrier 120a with heat radiation lid 110a, due to
Heat radiation lid 110a and insulating barrier 120a and thermal interface material 140 contact and not direct contact chip 130
The back side 132, therefore the heat radiation lid 110a of the present embodiment is e.g. by thermal interface material 140 and core
Sheet 130 thermal coupling.
On the other hand, reconfiguration line layer 151 is covered in active surface 131 and the hot interface of chip 130
Material 140, wherein reconfiguration line layer 151 e.g. connects chip 130 by patterned conductive layer 151a
Active surface 131 to be electrically connected with chip 130, and part patterned conductive layer 151a can be with heat
Interface material 140 contacts.Soldered ball B connects the patterned conductive layer in reconfiguration line layer 151 respectively
151b, to be electrically connected with chip 130.Herein, soldered ball B and chip 13 lay respectively at and reconfigure circuit
The opposite sides of layer 151.
In the present embodiment, the back side 132 of chip 130 and side surface 133 are by thermal interface material 140 institute
Cladding, therefore the area of dissipation of chip 130 can be improved.Furthermore, heat radiation lid 110a can pass through hot interface material
Material 140 with chip 130 thermal coupling, therefore chip 130 when operating produced heat just can pass through hot interface
Material 150 and heat radiation lid 110a are rapidly transferred to the external world.Additionally, due to the patterning of part is led
Electric layer 151a can contact with thermal interface material 140, and produced by therefore in reconfiguration line layer 151, heat is also
The external world can be rapidly transferred to by thermal interface material 140 and heat radiation lid 110a, or by weldering
Ball B is transferred to the external world.Accordingly, semiconductor package body 100 is just difficult to produce because of heat accumulation portion in the inner
Warpage.
Hereinafter will enumerate other embodiments using as explanation.Should be noted that at this, following embodiment edge
With element numbers and the partial content of previous embodiment, wherein use identical label to represent identical or near
As element, and eliminate the explanation of constructed content.Before referring to about the explanation of clipped
Stating embodiment, it is no longer repeated for following embodiment.
Fig. 2 is the schematic diagram of the semiconductor package body of another embodiment of the present invention.Refer to Fig. 2, this reality
Semiconductor package body 100A executing example is substantially similar with the semiconductor package body 100 of above-described embodiment, and two
Major difference is that between person: the thermal interface material 140 of the present embodiment exposes the back side of chip 130
132, and heat radiation lid 110a and insulating barrier 120a, thermal interface material 140 and the back side of chip 130
132 contacts.Specifically, insulating barrier 120a have first surface 121a and with first surface 121a phase
To second surface 122a, heat radiation lid 110a is configured on first surface 121a, and reconfigures circuit
Layer 151 is configured on second surface 122a, and the back side 132 of chip 130 e.g. trims in insulating barrier
The first surface 121a of 120a.
In sum, the semiconductor package body of the present invention can be at least coated with by thermal interface material and be positioned at insulation
The side surface of the chip accommodated in opening of layer, and with heat radiation lid contact thermal interface material, make dissipating cover
Body is by thermal interface material and chip thermal coupling.The most for it, the heat produced during chip running just can be passed through
Thermal interface material and heat radiation lid are rapidly transferred to the external world.Additionally, due to the pattern conductive of part
Layer can contact with thermal interface material, and therefore in reconfiguration line layer, produced heat also can pass through hot interface material
Material and heat radiation lid are rapidly transferred to the external world, or are transferred to the external world by soldered ball.Accordingly, originally
The semiconductor package body of invention can have good radiating efficiency, and is not easy to produce warpage because being heated.
On the other hand, the manufacture method of semiconductor package body proposed by the invention not only can be produced above-mentioned
Having the semiconductor package body of good radiating efficiency, its insulation material layer being also with patterning (i.e. has
Have the insulation material layer of multiple receiving opening) replace the framework used in existing molding processes, use
Remove the part production process in existing semiconductor packages and required accessory from, therefore contribute to the half of reduction
The package thickness of conductor packaging body also reduces its cost of manufacture.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a semiconductor package body, it is characterised in that including:
Insulating barrier, has receiving opening；
Chip, is arranged in described receiving opening, and described chip has active surface, relative to described master
Move the back side on surface and connect the side surface of described active surface and the described back side；
Thermal interface material, is filled in described receiving opening to be at least coated with the described side surface of described chip
And expose described active surface；
Heat radiation lid；And
Reconfiguration line layer, wherein said reconfiguration line layer and described heat radiation lid are respectively arranged at described
The both sides of insulating barrier, described heat radiation lid is by described thermal interface material and described chip thermal coupling, and institute
State reconfiguration line layer and be covered in the described active surface of described chip and described thermal interface material, and described
Reconfiguration line layer is electrically connected with described chip.
Semiconductor package body the most according to claim 1, it is characterised in that described thermal interface material
It is coated with the described back side of described chip and described side surface.
Semiconductor package body the most according to claim 2, it is characterised in that described heat radiation lid with
Described insulating barrier and the contact of described thermal interface material.
Semiconductor package body the most according to claim 1, it is characterised in that described thermal interface material
Expose the described back side of described chip, and described heat radiation lid and described insulating barrier, described hot interface material
Material and the described rear-face contact of described chip.
Semiconductor package body the most according to claim 4, it is characterised in that described insulating barrier has
First surface and the second surface relative with described first surface, described heat radiation lid is configured at described first
On surface, and described reconfiguration line layer is configured on described second surface, and the described back of the body of described chip
Face trims the described first surface in described insulating barrier.
Semiconductor package body the most according to claim 1, it is characterised in that described in reconfigure circuit
Layer includes at least one patterned conductive layer and at least one pattern dielectric layer being alternately stacked.
Semiconductor package body the most according to claim 1, it is characterised in that also include:
Multiple soldered balls, are electrically connected with described chip by described reconfiguration line layer.
Semiconductor package body the most according to claim 7, it is characterised in that more described soldered ball and institute
State chip and lay respectively at the both sides of described reconfiguration line layer.
9. the manufacture method of a semiconductor package body, it is characterised in that including:
Carrier is formed heat radiation lid；
Forming insulating barrier on described heat radiation lid, described insulating barrier has at least one receiving opening to expose
Go out the described heat radiation lid of part；
Chip it is configured in described receiving opening and inserts thermal interface material in described receiving opening,
So that described thermal interface material is coated with described chip and exposes the active surface of described chip；And
The described active surface of described insulating barrier, described thermal interface material and described chip is formed weight
Configuration line layer, wherein said reconfiguration line layer is electrically connected with described chip.
The manufacture method of semiconductor package body the most according to claim 9, it is characterised in that also
Including:
Described reconfiguration line layer is formed multiple soldered ball, more wherein said soldered ball pass through described in reconfigure
Line layer is electrically connected with described chip.
The manufacture method of 11. semiconductor package body according to claim 10, it is characterised in that also
Including:
Described heat radiation lid is made to separate with described carrier.
The manufacture method of 12. 1 kinds of semiconductor package body, it is characterised in that including:
Carrier is formed heat radiation material layer；
Forming insulation material layer in described heat radiation material layer, described insulation material layer has multiple receiving and opens
Mouth is to expose the described heat radiation material layer of part；
Multiple chips it is respectively arranged in more described receiving opening and inserts heat in those accommodate opening
Interface material, so that described thermal interface material is coated with those chips and exposes the active table of those chips
Face；And
The active surface of described insulation material layer, described thermal interface material and those chips is formed weight
Layout line line structure, wherein said reconfiguration line structure includes multiple reconfiguration line layer, and each described
Reconfiguration line layer is electrically connected with corresponding chip respectively.
The manufacture method of 13. semiconductor package body according to claim 12, it is characterised in that also
Including:
Forming many assembly weldings ball in those reconfiguration line layer, the most each assembly welding ball is respectively by a wherein weight
Configuration line layer is electrically connected with corresponding chip.
The manufacture method of 14. semiconductor package body according to claim 13, it is characterised in that also
Including:
Described heat radiation material layer is made to separate with described carrier.
The manufacture method of 15. semiconductor package body according to claim 12, it is characterised in that also
Including:
Along predetermined cuts line cut described heat radiation material layer, described insulation material layer and described in reconfigure line
Line structure, to form multiple semiconductor package body.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510177522.3A CN106158786A (en) | 2015-04-15 | 2015-04-15 | Semiconductor package body and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510177522.3A CN106158786A (en) | 2015-04-15 | 2015-04-15 | Semiconductor package body and preparation method thereof |
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| CN201510177522.3A Pending CN106158786A (en) | 2015-04-15 | 2015-04-15 | Semiconductor package body and preparation method thereof |
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| CN113366616A (en) * | 2018-11-29 | 2021-09-07 | Qorvo美国公司 | Thermally enhanced package and process for making same |
| US11923313B2 (en) | 2019-01-23 | 2024-03-05 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
| US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
| US11961813B2 (en) | 2019-01-23 | 2024-04-16 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12046505B2 (en) | 2018-04-20 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation |
| US12046483B2 (en) | 2019-01-23 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12046535B2 (en) | 2018-07-02 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12057374B2 (en) | 2019-01-23 | 2024-08-06 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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| US12062571B2 (en) | 2021-03-05 | 2024-08-13 | Qorvo Us, Inc. | Selective etching process for SiGe and doped epitaxial silicon |
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| US12062700B2 (en) | 2018-04-04 | 2024-08-13 | Qorvo Us, Inc. | Gallium-nitride-based module with enhanced electrical performance and process for making the same |
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| US12046505B2 (en) | 2018-04-20 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation |
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| CN113366616A (en) * | 2018-11-29 | 2021-09-07 | Qorvo美国公司 | Thermally enhanced package and process for making same |
| US11942389B2 (en) | 2018-11-29 | 2024-03-26 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
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| US12046483B2 (en) | 2019-01-23 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12046570B2 (en) | 2019-01-23 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12057374B2 (en) | 2019-01-23 | 2024-08-06 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12062623B2 (en) | 2019-01-23 | 2024-08-13 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
| US11923313B2 (en) | 2019-01-23 | 2024-03-05 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
| US12112999B2 (en) | 2019-01-23 | 2024-10-08 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12074086B2 (en) | 2019-11-01 | 2024-08-27 | Qorvo Us, Inc. | RF devices with nanotube particles for enhanced performance and methods of forming the same |
| US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
| US12062571B2 (en) | 2021-03-05 | 2024-08-13 | Qorvo Us, Inc. | Selective etching process for SiGe and doped epitaxial silicon |
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Application publication date: 20161123 |