CN1677650A - Semiconductor package device with layer-increasing structure and making method thereof - Google Patents
Semiconductor package device with layer-increasing structure and making method thereof Download PDFInfo
- Publication number
- CN1677650A CN1677650A CNA2004100307158A CN200410030715A CN1677650A CN 1677650 A CN1677650 A CN 1677650A CN A2004100307158 A CNA2004100307158 A CN A2004100307158A CN 200410030715 A CN200410030715 A CN 200410030715A CN 1677650 A CN1677650 A CN 1677650A
- Authority
- CN
- China
- Prior art keywords
- chip
- reinforced structure
- stereoplasm frame
- layer reinforced
- making
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 46
- 239000003292 glue Substances 0.000 claims description 28
- 239000003822 epoxy resin Substances 0.000 claims description 15
- 229920000647 polyepoxide Polymers 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 7
- 239000009719 polyimide resin Substances 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 5
- 229920001187 thermosetting polymer Polymers 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000741 silica gel Substances 0.000 claims description 4
- 229910002027 silica gel Inorganic materials 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 3
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 claims 1
- 230000032798 delamination Effects 0.000 abstract description 8
- 238000004880 explosion Methods 0.000 abstract description 5
- 238000013467 fragmentation Methods 0.000 abstract 1
- 238000006062 fragmentation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 69
- 229920005989 resin Polymers 0.000 description 15
- 239000011347 resin Substances 0.000 description 15
- 239000000084 colloidal system Substances 0.000 description 10
- 241000196324 Embryophyta Species 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 230000004907 flux Effects 0.000 description 9
- 238000003466 welding Methods 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 8
- 239000000306 component Substances 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000004382 potting Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 1
- 241000482268 Zea mays subsp. mays Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 206010016256 fatigue Diseases 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The capsulation piece comprises following parts: hard base, hard frame possessing through hole fixed on the hard base, at least one chip accommodated in the through hole of hard frame, medium filled in gap between chip and hard frame, addition layer structure formed on the chip and hard frame and connected to the chip electrically, multiple pieces of conducting subassemblies soldered on addition layer in use for connecting the chip to external devices electrically. Since the hard base and hard frame are adopted, the disclosed capsulation piece can prevent problems of structural warp, fragmentation, delamination and gas explosion etc. from happening. The invention discloses method for preparing the capsulation piece of semiconductor in wafer level further.
Description
Technical field
The invention relates to a kind of wafer level semiconductor packaging part and method for making thereof, particularly form layer reinforced structure, plant wafer level semiconductor packaging part and the method for making thereof that contact (External Contacts) extends out out this chip action face that expose that connects thereby make for soldered ball about a kind of action face (Active Surface) at chip.
Background technology
For satisfying the compact demand of electronic product, also develop towards the direction of microminiaturized (Miniaturization) as the semiconductor package part of the core component of electronic product.A kind of form that develops the microminiaturized semiconductor package part that in the industry is that (Chip ScalePackage, CSP), the size that it is characterized in that this chip size package equals the size of this chip or bigger approximately 1.2 times than the size of chip to chip size package.
Have again, semiconductor package part is except that microminiaturization dimensionally, also must improve integrated level and connect the quantity of the I/O end (I/O Contact) of usefulness, just satisfy the demand of electronic product on high-performance and high processing rate with electrical electricity of external device such as circuit boards.And the mode of increase I/O terminal number amount, generally be the weld pad of on the action face of chip, laying as much as possible (BondPads), but the weld pad quantity of laying on the action face of chip must be subjected to the area of action face and the restriction of the spacing between weld pad (Pitch); For further on limited area, laying the I/O end of greater number, then the wafer level semiconductor packaging part is arranged, as the appearance of crystal wafer chip dimension packaging part (Wafer Level CSP).
The wafer level semiconductor packaging part is to use a kind of lead rerouting technology (RDL, Redistribution Layer Technology), it is to form dielectric layer (Dielectric Layer) on the action face of chip, the weld pad on the action face of exposed chip beyond the perforate on the dielectric layer again, on this dielectric layer, form many leads then, make an end of this lead respectively be electrically connected to weld pad on the chip, the other end then forms contact (contact), then, on dielectric layer, cover and refuse welding flux layer (Solder Mask Layer), cover this lead and weld pad with lid, at last, refuse to form a plurality of perforates (opening) in the welding flux layer at this, make the contact of this lead can expose outside corresponding perforate, weld with it for soldered ball.This kind utilization lead rerouting technology and the layer reinforced structure (Build-up Layer) that forms are though can effectively increase chip and the extraneous I/O terminal number amount that electrically connects, and it still is subject to the limited area on the action face of chip.
For further increasing the I/O terminal number amount that chip externally electrically connects again, the method for solution is that the laying scope with the I/O end extends out (Fan-out) zone to the action face of chip.This semiconductor package part that makes layer reinforced structure extend to the chip exterior domain is seen the U.S. the 6th, 271, No. 469 patents, as shown in Figure 6, the 6th, 271, the semiconductor package part 6 that No. 469 patent disclosed is that chip 60 is coated in the colloid 62 that mold pressing program (Molding Process) forms, the action face 602 of this chip 60 exposes outside the surface 622 of this colloid 62 after colloid 62 forms, layer reinforced structure 64 is (by dielectric layer 642, lead 644 and refuse welding flux layer 646 and constitute) then be formed on the surface 622 of the action face 602 of this chip 60 and colloid 62, this layer reinforced structure 64 electrically connects by the weld pad 604 of lead 644 with chip 60, when soldered ball 66 plant be connected on this layer reinforced structure 64 and electrically connect with lead 644 after, this chip 60 can electrically connect with extraneous via soldered ball 66.
Though thereby the structure of this semiconductor package part 6 can provide the bigger laying area of I/O end to increase its quantity, but this colloid 62 is not to be formed on the higher substrate of hardness (Substrate), and the position that the middle position ratio that is equipped with chip 60 is not set chip on every side is thin, so warpage easily takes place in the temperature cycles of successive process, and the concentrated influence of stress, label is that 624 parts often have cracked (Crack) phenomenon to produce in the drawings; Simultaneously, because chip 60 roughly coats by colloid 62, promptly can because of both thermal coefficient of expansions (Coefficientof Thermal Expansion, difference CTE) is big, cause the delamination (Delamination) between chip 60 and colloid, thereby influence the quality of manufactured goods.
Be the shortcoming of the semiconductor package part that solves the 6th, 271, No. 469 patents of the aforementioned U.S., the U.S. the 6th, 498, No. 387 patents are a kind of semiconductor package parts with the glass plate carries chips.As shown in Figure 7, this semiconductor package part 7 is with chip 70 sticking putting on glass plate 71, epoxy resin coating layer (Epoxy) 72 on chip 70, so that after these chip 70 coatings, the weld pad 702 on the exposed chip 70 beyond the perforate in this epoxy resin layer 72, then, on this epoxy resin layer 72, form a plurality of leads 73 that electrically connect with this weld pad 702, on this epoxy resin layer 72, lay again and refuse welding flux layer 74 to cover this lead 73, then, the lead 73 of exposed portions serve beyond this refuses welding flux layer 74 perforates supplies soldered ball 75 to plant and is connected on the lead 72 that exposes.
This U.S. the 6th, 498, No. 387 patents are with the bearing part of glass plate 71 as chip 70, utilize the hard characteristic of these glass plate 71 matter can solve the 6th, 271, warpage and cracked problem can take place in the colloid of No. 469 patents, and because of glass plate 71 is close with the CTE of chip 70, the delamination problems that causes so also there is not above-mentioned CTE difference; Yet, this chip 70 is coated fully by epoxy resin layer 72, tend to because of chip 70 and epoxy resin layer 72 in the temperature cycles of the difference on the thermal coefficient of expansion (CTE Mismatch) in successive process, cause chip 70 to be heated stress influence and rhegma take place.Simultaneously, the side 720 of this epoxy resin layer 72 directly is exposed in the atmosphere, promptly can cause extraneous aqueous vapor to be tired out via epoxy resin layer 72 because of the moisture absorption height of epoxy resin itself gathers on the action face of chip 70, so can cause the problem of gas explosion (Popcorn), the reliability of manufactured goods can't be improved.
As from the foregoing, the 6th, 271,469 and 6,498, the semiconductor package part of No. 387 patents all has some problems that wait to overcome.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of no warpage, cracked and delamination problems, can improve the wafer level semiconductor packaging part with layer reinforced structure of reliability.
Another object of the present invention is to provide a kind of method for making that need not use injecting glue with the wafer level semiconductor packaging part with layer reinforced structure of mould.
Thereby a further object of the present invention is to provide a kind of to be difficult for moisture absorption and to avoid producing gas explosion, and then improves the wafer level semiconductor packaging part of product reliability.
It is a kind of perfect in to improve the wafer level semiconductor packaging part of product reliability to the chip protection that another purpose of the present invention is to provide.
For reaching above-mentioned and other purpose, the invention provides a kind of wafer level semiconductor packaging part and comprise: hard base with layer reinforced structure; Be fixed on this hard base and offer the stereoplasm frame of at least one through hole; At least one is installed with in the through hole of this stereoplasm frame and with the chip that its non-acting surface engages with hard base, wherein is formed with the gap between this chip and stereoplasm frame, and its thickness is identical in fact with the thickness of stereoplasm frame; Be filled in the medium in this gap; Be formed at the layer reinforced structure on this chip and the stereoplasm frame, make this layer reinforced structure and chip form electrical connection; And conductive component a plurality of and that this layer reinforced structure electrically connects.
This layer reinforced structure such as the above-mentioned the 6th, 271,469 and 6,498, No. 387 United States Patent (USP) is described, be by at least one dielectric layer,, and be coated on this dielectric layer and the lead and the welding flux layer of refusing that is formed with for the perforate of conductive component and lead electric connection constitutes with a plurality of leads that are formed on this dielectric layer and electrically connect with weld pad on the action face of chip.
The present invention also provides a kind of method for making with wafer level semiconductor packaging part of layer reinforced structure to comprise the following steps: to prepare the tabular hard base of suitable thickness, and the stereoplasm frame of the through hole arranged of a plurality of one-tenth array mode; Stereoplasm frame is fixed on the hard floor; At least one chip is seated on this hard floor via the corresponding through hole of this stereoplasm frame, and maintains default gap between all sides of this chip and stereoplasm frame; Filled media in this gap makes this chip and stereoplasm frame be separated by this medium; Action face side at chip forms the layer reinforced structure that electrically connects with this chip; In this layer reinforced structure, plant a plurality of conductive components that electrically connect with this layer reinforced structure, borrow this conductive component and external device to electrically connect for this chip; And cut one way preface (Singulation) to form a plurality of wafer level semiconductor packaging parts with layer reinforced structure.
In another preferred embodiment of the present invention, this chip can be placed in the predeterminated position on the hard base earlier, and the stereoplasm frame that again this is had a plurality of through holes combines with hard base.In conjunction with after, this chip can be arranged in the corresponding through hole of this stereoplasm frame.
In addition, " stereoplasm frame " mentioned in this article and " hard base " are defined as the framework made from existing chemical materials, at high temperature or can not occur the phenomenon of buckling deformation in the temperature cycles (Temperature Cycle); Medium then is defined as has thermoelasticity effect (Thermoelastic) and the low material of thermal coefficient of expansion, or generally is used for the macromolecule resin material as epoxy resin etc. of coating chip.
In sum, compared with prior art, semiconductor package part and the method for making thereof with layer reinforced structure of the present invention do not have warpage, cracked and delamination problems; need not use the injecting glue mould; avoid producing gas explosion thereby be difficult for moisture absorption, and perfect to the chip protection, improved product reliability.
Description of drawings
Fig. 1 is the cutaway view of the wafer level semiconductor packaging part of the embodiment of the invention 1.
Fig. 2 A to Fig. 2 F is the steps flow chart schematic diagram of the method for making of wafer level semiconductor packaging part shown in Figure 1;
Fig. 3 A to Fig. 3 B is the schematic flow sheet that wafer level semiconductor packaging part shown in Figure 1 forms the embodiment 2 of the step before the layer reinforced structure.
Fig. 4 is the cutaway view of the wafer level semiconductor packaging part of the embodiment of the invention 3.
Fig. 5 is the front view of the embodiment 5 of the employed stereoplasm frame of wafer level semiconductor packaging part of the present invention.
Fig. 6 is the cutaway view of the wafer level semiconductor packaging part of prior art.
Fig. 7 is the cutaway view of wafer level semiconductor packaging part of another embodiment of prior art.
Embodiment
Following conjunction with figs. describes wafer level semiconductor packaging part and the method for making thereof with layer reinforced structure of the present invention in detail.
Embodiment 1
As shown in Figure 1, the wafer level semiconductor packaging part with layer reinforced structure 1 of the present invention mainly by hard base 15, have through hole 100 stereoplasm frame 10, be placed in chip 11 in these stereoplasm frame 10 through holes 100, be filled in 11 of this stereoplasm frame 10 and chips resin material 12, be formed at the layer reinforced structure 13 on this stereoplasm frame 10 and the chip 11 and plant a plurality of soldered balls (being above-mentioned conductive component) 14 that are connected on this layer reinforced structure 13 and constitute.
This hard base 15 and stereoplasm frame 10 are by glass material, metal material (as copper metal etc.), thermosets is (as polyimide resin (Polyimide Resin), BT resin (BismaleimideTriazine Resin) and FR-4 etc.) etc. material made, this hard base 15 and stereoplasm frame 10 be not owing to can produce buckling deformation under the temperature cycles in hot environment or processing procedure, so with its main structure body (Primary Structured body) as wafer level semiconductor packaging part 1, the wafer level semiconductor packaging part that encapsulation is finished does not promptly have the problem of warpage, and its rigid nature can not take place as the 6th, the angle end that 271, No. 469 described colloids of United States Patent (USP) hold the chip groove easily produces the problem of rhegma (Crack).
This hard base 15 has first surface 150 and second surface 151.100 of the through holes of this stereoplasm frame 10 run through the first surface 101 and the opposing second surface 102 of this stereoplasm frame 10, and should be formed at the central part of this stereoplasm frame 10.When this stereoplasm frame 10 is fixed on the hard base 15, it is coating joint glue material 17 at least one surface of the first surface 150 of the second surface 102 of stereoplasm frame 10 and hard base 15, second surface 102 with stereoplasm frame 10 is bonded on the first surface 150 of hard base 15 again, so that suitable curing mode that should joint glue material 17 is cured.
11 of this chips have the electronic building brick of being formed with (Electronic Components), the action face 110 of electronic circuit (Electronic Circuits) and a plurality of weld pad 112 and with respect to the non-action face 111 of this action face 110, when this chip 11 is accommodated in the through hole 100 of stereoplasm frame 10, be first surface 101 coplines that make its action face 110 and stereoplasm frame 10, thereby make its non-action face 111 and the first surface 150 of hard base 15 and second surface 102 coplines of stereoplasm frame 10, just, chip 11 has identical thickness with stereoplasm frame 10; Simultaneously, when this chip 11 places the through hole 100 of this stereoplasm frame 10,10 of this chip 11 and the stereoplasm frames gapped S of being separated by, thus make both unlikely contacts.In addition, the non-action face 111 of this chip 11 can engage fixing by the first surface 150 of joint glue material 18 and hard base 15.
This resin material 12 for low modulus as polyimide resin, silica gel, materials such as epoxy resin, behind the gap that is filled in 10 of this chip 11 and stereoplasm frames, its rubber-like speciality, can become the buffer medium of 10 of chip 11 and stereoplasm frames, with in the temperature cycles of processing procedure, because of the difference on the thermal coefficient of expansion of 11 of stereoplasm frame 10 and chips, the thermal stress that 10 pairs of chips of stereoplasm frame 11 are produced can effectively be discharged by this resin material 12, make the chip 11 can cracked and delamination, so can improve the acceptance rate and the reliability of the manufactured goods of wafer level semiconductor packaging part 1 of the present invention.
This layer reinforced structure 13 is made of the welding flux layer 132 of refusing that is laid in dielectric layer 130 on this chip 11 and the stereoplasm frame 10, a plurality of lead 131 that is formed on this dielectric layer 130 and electrically connects with weld pad 112 on the chip 11 and covers this dielectric layer 130 and lead 131.Because this layer reinforced structure 13 itself and generation type thereof are prior art, so no longer illustrate at this.Simultaneously, this layer reinforced structure 13 can form at least one dielectric layer and many leads (figure is mark not) as required again on this dielectric layer 130 and lead 131.
Fig. 2 A to 2F is the step schematic diagram of above-mentioned wafer level semiconductor packaging part 1 method for making.
With reference to Fig. 2 A, the first step of the wafer level semiconductor packaging part method for making of the embodiment of the invention 1 be prepare a module board 10 of making by glass material ', it comprises that there is the stereoplasm frame 10 (separating with dotted line) of rectangle through hole 100 in a plurality of central authorities, and each stereoplasm frame 10 has first surface 101 and opposing second surface 102.
With reference to Fig. 2 B, with this module board 10 ' be fixed on the hard base made from glass material 15, fixing means is at least one surface of the first surface 150 of the second surface 102 of stereoplasm frame 10 and hard base 15, the coating material is the joint glue material 17 of ultraviolet curing glue (UV glue), second surface 102 with stereoplasm frame 10 is bonded on the first surface 150 of hard base 15 again, UV-irradiation reasonable time by suitable wavelength, this joint glue material 17 is solidified, make this module board 10 ' be fixed on the hard base 15.
With reference to Fig. 2 C, in each through hole 100, place a chip 11, the storing mode of chip 11 is to make the non-action face 111 of chip 11 down in the face of the first surface 150 of hard base 15,110 of its action face expose in the atmosphere up.Simultaneously before placement, on arbitrary surface of the first surface 150 of the hard base 15 of the non-action face 111 of chip 11 or relative position, the coating material is the joint glue material 18 of ultraviolet curing glue (UV glue) at least.Simultaneously, the thickness of this chip 11 be made as with this module board 10 ' thickness identical, when being carried on this hard base 15 so chip 11 is inserted in the through hole 100, first surface 101 coplines of this action face 110 and each stereoplasm frame 10.In addition, the sectional area of this through hole 100 is greater than the area of this chip 11, thereby, when chip 11 is inserted through hole 100, make this chip 11 around with the hole wall of through hole 100 between can not contact, and be formed with default gap S.Have again, chip 11 is carried on the precalculated position of hard base 15 through through hole 100 after, this joint glue material 18 is solidified after by the below immediately, this chip 11 is fixed on the hard base 15 with the UV-irradiation reasonable time of suitable wavelength.
With reference to Fig. 2 D,, relend siphon effect this resin material 12 evenly is filled in the S of gap being filled in regular turn in the gap S of 10 of each chip 11 and stereoplasm frames of appropriate amount with point glue equipment 16 as resin materials 12 such as silica gel, epoxy resin or polyimide resins.
With reference to Fig. 2 E, coating dielectric layer 130 on the action face 110 of the first surface 101 of this stereoplasm frame 10 respectively and chip 11, again in existing mode, include but not limited to that as photolithographic techniques (Photolithographic Technique) and laser drill (Laser Drilling) etc. perforation (not giving label) is offered in the position of weld pad 112 on corresponding to the action face 110 of chip 11; Then, in any existing mode, include but not limited to as photolithographic techniques, on this dielectric layer 130, form multiple bar chart caseization (Patterned) lead 131, an end that makes this lead 131 respectively electrically connects via the perforation and the weld pad on the chip 11 112 of dielectric layer 130, from extend outwardly out all sides of this chip 11 of this weld pad 112, and order respectively the other end of this lead 131 form link (ContactTerminal does not give label); Then, on this lead 131 and dielectric layer 130, lay and refuse welding flux layer 132, offer a plurality of perforates (not giving label) to expose outside the respectively link of this lead 13 1 in any existing mode again, plant respectively on the link that is connected to this lead 131 for a plurality of soldered balls 14, make this soldered ball 14 respectively with by this dielectric layer 130, lead 131 and refuse the layer reinforced structure 13 that welding flux layer 132 constitutes and form electrical connection.So the material of this soldered ball 14 itself and to plant the mode that is connected on the layer reinforced structure 13 all be prior art is no longer explanation.
At last, shown in Fig. 2 F, cut single job (Singulation), to form wafer level semiconductor packaging part 1 as shown in Figure 1 with any existing mode.
From the above, 10 of the chip 11 of wafer level semiconductor packaging part 1 of the present invention and stereoplasm frames are separated by resin material 12, so the thermal stress that this stereoplasm frame 10 is produced in the temperature cycles of processing procedure can effectively be discharged by this resin material 12.Simultaneously, with stereoplasm frame 10 and hard base 15 main structure assembly as this wafer level semiconductor packaging part 1, need not use potting compound (Molding Compound) coating chip mode, encapsulation procedure can be simplified, and easily warpage and cause the problem of the cracked and delamination of chip of the existing colloid that forms by potting compound (Encapsulant) can be avoided; Chip 11 and resin material 12 are coated fully by stereoplasm frame 10 and hard base 15 again, can not contact with outside air, so also can avoid resin material 12 because moisture absorption causes in temperature cycles, the aqueous vapor that sucks in the resin material 12 produces the problem of gas explosion.
If want thinning wafer level semiconductor packaging part 1 of the present invention, then after the step shown in Fig. 2 D is finished, to the second surface 151 of this hard base 15 respectively, in any existing mode, include but not limited to mode as mechanical lapping, carry out grinding operation (Grinding), with the thickness reduction of hard base 15.Grinding operation is a prior art, here no longer explanation.
Embodiment 2
The method for making that the embodiment of the invention 2 will disclose is roughly with above-mentioned embodiment 1, so the conjunction with figs. that only will not exist together is described in detail and the no longer explanation that exists together mutually.In Fig. 3 A to Fig. 3 B, represent with identical label with the identical or similar assembly of Fig. 2 A to Fig. 2 F.
With reference to Fig. 3 A, the module board 10 that the stereoplasm frame 10 of preparing to be arranged by a plurality of one-tenth array modes constitutes ', each stereoplasm frame 10 has rectangle through hole 100, first surface 101 and opposing second surface 102; Simultaneously, prepare hard base 15, this hard base has first surface 150, second surface 151, and the fixing a plurality of chips 21 of the predeterminated position on this hard base 15.Fixing mode is a coating joint glue material 18 at least one surface of the non-action face 111 of the first surface 150 of hard base 15 and chip 11, non-action face 111 with chip 11 is bonded on the first surface 150 of hard base 15 again, so that suitable curing mode that should joint glue material 18 is cured.
With reference to Fig. 3 B,, simultaneously, make chip 11 on the hard base 15 corresponding respectively and be accommodated in the through hole 100 of each stereoplasm frame 10, and make 10 formation of chip 11 and stereoplasm frame gap S this module board 10 ' be fixed on this hard base 15.The fixing means that stereoplasm frame 10 and hard base are 15 can be coated on joint glue material 17 on the composition surface as mentioned above, to be joined after again so that suitable curing mode that should joint glue material 17 is cured.
In preferred embodiment, the condition of cure of the joint glue material 18 of fixed chip 11 and hard base 15, identical in fact with the condition of cure of the fixing joint glue material 17 of stereoplasm frame 10 and hard base 15, therefore this chip 11 can be placed on the hard base 15, and at stereoplasm frame 10 also after placement positioning on the hard base 15, again the joint glue material 18 of chip 11 and stereoplasm frame 10 and the joint glue material 17 of hard base 15 and stereoplasm frame 10 are solidified together, to save processing procedure program and time.
Next semiconductor package part forms among the gap S that step is included in 10 of chip 11 and stereoplasm frames with a glue mode coating resin material, action face 110 at chip 11 forms layer reinforced structure, plant the ball operation, cut single job etc., because with identical described in the embodiment 1, and made finished product is also identical, so no longer explanation.
Embodiment 3
The structure of the wafer level semiconductor packaging part 4 that the embodiment of the invention 3 will disclose is roughly with embodiment 1, and it does not exist together as shown in Figure 4, and its hard base 25 is provided with through hole 252 in the installation position central authorities of corresponding chip 21.
The manufacture method of semiconductor package part 4 is preparation hard bases 25, and this hard base 25 has first surface 250, second surface 251 and at least one through hole 252, each this through hole offer the central authorities that the position is each corresponding chip preset position at it.Secondly, as embodiment 1, stereoplasm frame 20 usefulness joint glue materials 27 are fixed on this hard base 25.Again chip 21 is placed on the hard base 25, the storing mode of chip 21 be make chip 21 non-action face 211 down in the face of the through hole 252 of hard base 25, and chip 21 and 20 of stereoplasm frames are formed with a gap S.After chip 21 was carried on the hard base 25, via through holes 252 was the air sucking-off immediately, made respectively these chip 21 vacuum suction on this hard base 25.
Next semiconductor package part forms step and comprises with glue mode potting resin material 22 in the gap S of 20 of chip 21 and stereoplasm frames, action face 210 at chip 21 forms layer reinforced structure 23, plant the ball operation, cut single job etc., because with identical described in the embodiment 1, and manufactured goods are also identical, so no longer explanation.
Embodiment 4
The structure of the wafer level semiconductor packaging part in embodiment 4 is roughly with embodiment 1, and its difference is in promoting radiating efficiency.The material of hard base 15 is used the higher material of coefficient of heat transfer instead, copper for example, and the grafting material 18 that hard base 15 and chip are 11 can be used the thermal conductivity viscose glue, and the heat that chip 11 is produced can borrow these hard base 15 direct loss to atmosphere.
Embodiment 5
Fig. 5 is the front view of another embodiment of the employed stereoplasm frame of wafer level semiconductor packaging part of the present invention.The roughly same the various embodiments described above of stereoplasm frame 50 that this embodiment 5 is disclosed, its difference be in, for further avoiding stress to concentrate causing stereoplasm frame 50 at the angle of through hole 500 end 500 ' chipping, the angle end 500 of this through hole 500 ' handled by corners, with effective release stress concentration effect, avoid stereoplasm frame 50 that rhegma (Crack) takes place.
Claims (23)
1. wafer level semiconductor packaging part with layer reinforced structure is characterized in that this packaging part comprises:
Hard base;
Stereoplasm frame has at least one through hole, and is fixed on this hard base;
At least one chip is accommodated in the through hole of this stereoplasm frame and is placed on this hard base, and and this stereoplasm frame between be formed with the gap;
Medium is filled between this chip and stereoplasm frame in the formed gap;
Layer reinforced structure is formed on this stereoplasm frame and the chip, and forms electrical connection with this chip; And
A plurality of conductive components are electrically connected to this layer reinforced structure, electrically connect for this chip and external device.
2. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that the thickness of this stereoplasm frame is identical with the thickness of this chip.
3. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, this through hole is a rectangular opening.
4. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 3 is characterized in that the angle end of this through hole is by corners.
5. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, a kind of the making in the cohort that this hard base is made up of glass material, metal material and thermosets.
The 6 wafer level semiconductor packaging parts with layer reinforced structure as claimed in claim 1 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.
7. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, this medium is a kind of in the cohort formed of falope ring epoxy resins and polyimide resin.
8. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that this conductive component is a soldered ball.
The 9 wafer level semiconductor packaging parts with layer reinforced structure as claimed in claim 1 is characterized in that this hard base has at least one through hole on the correspondence position of each chip.
10. the method for making with wafer level semiconductor packaging part of layer reinforced structure is characterized in that this comprises the following steps:
The module board that stereoplasm frame constituted that preparation is arranged by a plurality of one-tenth array modes with through hole;
This module board is fixed on the hard base;
In each through hole, insert at least one chip, make it to be carried on this hard base, and make between the corresponding stereoplasm frame of this chip and module board and be formed with default gap;
Filled media makes this chip and stereoplasm frame be separated by this medium to this gap;
Form layer reinforced structure on this module board and chip, and make this layer reinforced structure be electrically connected to this chip, and make a plurality of conductive component conductions be connected to this layer reinforced structure; And
Cut single job to form the wafer level semiconductor packaging part that this has layer reinforced structure.
11. method for making as claimed in claim 10 is characterized in that, this medium is packed into gap between chip and stereoplasm frame by a glue mode.
12. method for making as claimed in claim 10 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.
13. method for making as claimed in claim 10 is characterized in that, this medium is a kind of in the cohort formed of silica gel, epoxy resin and polyimide resin.
14. method for making as claimed in claim 10 is characterized in that, this conductive component is a soldered ball.
15. method for making as claimed in claim 10 is characterized in that, this hard base respectively is formed with at least one through hole in the position of this chip in correspondence.
16 method for makings as claimed in claim 15 is characterized in that, in each through hole of this stereoplasm frame, insert at least one this chip after, be that the through hole through this hard base utilizes vacuum to fix this chip.
17. the method for making with wafer level semiconductor packaging part of layer reinforced structure is characterized in that this method for making comprises the following steps:
Prepare hard base;
The module board that stereoplasm frame constituted that preparation is arranged by a plurality of one-tenth array modes with through hole;
On this hard base, to placing at least one chip on each this through hole position of module board;
This module board is fixed on this hard base, and makes between the corresponding stereoplasm frame of this chip and module board and be formed with default gap;
Filled media makes this chip and stereoplasm frame be separated by this medium to this gap;
Form layer reinforced structure on this module board and chip, and make this layer reinforced structure be electrically connected to this chip, and make a plurality of conductive component conductions be connected to this layer reinforced structure; And
Cut single job to form the wafer level semiconductor packaging part that this has layer reinforced structure.
18. method for making as claimed in claim 17 is characterized in that, this medium is packed into gap between chip and stereoplasm frame by a glue mode.
19. method for making as claimed in claim 17 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.
20. method for making as claimed in claim 17 is characterized in that, this medium is a kind of in the cohort formed of silica gel, epoxy resin and polyimide resin.
21. method for making as claimed in claim 17 is characterized in that, this conductive component is a soldered ball.
22. method for making as claimed in claim 17 is characterized in that, this hard base respectively is formed with at least one through hole in the position of this chip in correspondence.
23. method for making as claimed in claim 22 is characterized in that, in each through hole of this stereoplasm frame, insert at least one this chip after, be that the through hole through this hard base utilizes vacuum to fix this chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100307158A CN1316604C (en) | 2004-03-31 | 2004-03-31 | Semiconductor package device with layer-increasing structure and making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100307158A CN1316604C (en) | 2004-03-31 | 2004-03-31 | Semiconductor package device with layer-increasing structure and making method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1677650A true CN1677650A (en) | 2005-10-05 |
| CN1316604C CN1316604C (en) | 2007-05-16 |
Family
ID=35050060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100307158A Expired - Fee Related CN1316604C (en) | 2004-03-31 | 2004-03-31 | Semiconductor package device with layer-increasing structure and making method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1316604C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567322B (en) * | 2008-04-21 | 2010-11-17 | 南茂科技股份有限公司 | Encapsulating structure and encapsulating method of chip |
| CN103552977A (en) * | 2013-11-08 | 2014-02-05 | 陈闯 | Wafer level package structure for micro electromechanical system and package method |
| CN106158786A (en) * | 2015-04-15 | 2016-11-23 | 力成科技股份有限公司 | Semiconductor package body and preparation method thereof |
| WO2024001541A1 (en) * | 2022-07-01 | 2024-01-04 | 深圳市华宝新能源股份有限公司 | Solar panel |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10756054B1 (en) | 2019-07-24 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020070443A1 (en) * | 2000-12-08 | 2002-06-13 | Xiao-Chun Mu | Microelectronic package having an integrated heat sink and build-up layers |
| TW557521B (en) * | 2002-01-16 | 2003-10-11 | Via Tech Inc | Integrated circuit package and its manufacturing process |
| CN100389494C (en) * | 2002-05-23 | 2008-05-21 | 威盛电子股份有限公司 | IC package and its preparing process |
-
2004
- 2004-03-31 CN CNB2004100307158A patent/CN1316604C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567322B (en) * | 2008-04-21 | 2010-11-17 | 南茂科技股份有限公司 | Encapsulating structure and encapsulating method of chip |
| CN103552977A (en) * | 2013-11-08 | 2014-02-05 | 陈闯 | Wafer level package structure for micro electromechanical system and package method |
| CN106158786A (en) * | 2015-04-15 | 2016-11-23 | 力成科技股份有限公司 | Semiconductor package body and preparation method thereof |
| WO2024001541A1 (en) * | 2022-07-01 | 2024-01-04 | 深圳市华宝新能源股份有限公司 | Solar panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1316604C (en) | 2007-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1106691C (en) | Packaging for stacked semiconductor chip and its producing method | |
| CN1266764C (en) | Semiconductor device and its producing method | |
| JP4926337B2 (en) | light source | |
| CN1298034C (en) | Semiconductor package having semiconductor constructing body and method of manufacturing the same | |
| CN1235275C (en) | Semiconductor module and method for mfg. semiconductor module | |
| CN1092397C (en) | High performance, low cost multi-chip module package | |
| CN101312203A (en) | Image sensor chip scale package having inter-adhesion with gap and method of the same | |
| US20140206184A1 (en) | Interposer having molded low cte dielectric | |
| CN1337738A (en) | Band with injectable conductive area for semiconductor package treatment and mfg. method thereof | |
| CN86105249A (en) | Semiconductor device and manufacturing thereof | |
| JP2004335641A (en) | Method of manufacturing substrate having built-in semiconductor element | |
| CN1619787A (en) | Semiconductor device | |
| CN1309283C (en) | Manufacturing method of circuit device | |
| CN101202253A (en) | Wafer level package with good coefficient of thermal expansion efficiency performance and method of the same | |
| JP2011082586A (en) | Method of manufacturing multi-chip module | |
| CN1282982A (en) | Manufacturing method of semi-conductor device | |
| CN1543675A (en) | Microelectronic package having a bumpless laminated interconnection layer | |
| US20080211075A1 (en) | Image sensor chip scale package having inter-adhesion with gap and method of the same | |
| CN1716581A (en) | Device mounting board | |
| CN1512580A (en) | Semiconductor device and its producing method | |
| CN1925141A (en) | Chip package structure | |
| CN1835222A (en) | Semiconductor device and a manufacturing method of the same | |
| US20080099903A1 (en) | Stacked chip package, embedded chip package and fabricating method thereof | |
| CN1212786A (en) | Semiconductor device and process for producing the same | |
| CN1855450A (en) | High-heat loss rate semiconductor sealer and its production |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070516 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |