CN103552977A - Wafer level package structure for micro electromechanical system and package method - Google Patents
Wafer level package structure for micro electromechanical system and package method Download PDFInfo
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- CN103552977A CN103552977A CN201310552733.1A CN201310552733A CN103552977A CN 103552977 A CN103552977 A CN 103552977A CN 201310552733 A CN201310552733 A CN 201310552733A CN 103552977 A CN103552977 A CN 103552977A
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Abstract
The invention discloses a wafer level package structure for a micro electromechanical system and a package method. An epoxy resin base material is cut to form epoxy resin disks which have the same sizes as that of a wafer and are used as package materials; the epoxy resin disks are perforated; optical glass, the epoxy resin disks and the wafer are correspondingly pressed to form an integrated package structure; furthermore, during pressing, through holes in the epoxy resin disks correspond to chips on the wafer. According to the wafer level package structure for the micro electromechanical system and the package method, a glass fiber epoxy resin copper-clad plate flame resistant material is used for performing airtight cavity covering and sealing protection on the chips during wafer level package, and the problems of granule and excessive glue pollution and poor bonding which are caused by exposure and development technical procedures for a liquid photoinduced solder resist material on an IC (integrated chip) surface and cracks, stripping, open circuit, short circuit and the like caused by the factor of the photoinduced solder resist in the subsequent procedures can be effectively solved.
Description
Technical field
The present invention relates to a kind of MEMS wafer level packaging structure and method for packing, be mainly used in semiconductor, microelectronics, MEMS field wafer scale (siliceous through hole TSV) encapsulation technology product and wafer IC face to be carried out to air tight housing cover envelope protection.
Background technology
At present; in wafer scale (the siliceous through hole TSV) encapsulation process of semiconductor applications; wafer IC face is carried out to cavity and cover when protection envelope; generally adopt the green oil material with certain viscosity; by this green oil being carried out to viscosity allotment, after stirring, coat on optical glass; then through modes such as exposure, development, bakings, on optical glass, form 40 microns of cavitys that left and right is high, finally by plastic roll, contraposition, bonding techniques, wafer IC and above-mentioned cavity are combined to form wafer IC face covered to envelope protection.But this method has larger limitation: first, green oil has certain requirement in viscosity allotment, after generally static four days of need and viscosity reach requirement, can use, and after four days, need within the period of regulation, to use up in time, otherwise can badly have to abandon use because viscosity or composition change to cause, cause larger waste of material, secondly, green oil needs the time of four days, causes the encapsulation cycle long, is difficult to meet client and hands over phase demand, moreover green oil, in exposure, development, bake process, inevitably causes particle contamination ratio higher, affects the yield of finished product, in addition, in above-mentioned encapsulation process, because the cavity thickness of applying the making of green oil material is because of green oil material nature, the reasons such as the difficult to govern control of cavity manufacturing process, housing surface can be rough and uneven in surface, the thorn-like projection that has more than one to ten micron, these can affect the adhesion of cavity and wafer bonding, the characteristic of green oil itself makes in subsequent technique process simultaneously, after being difficult to answer para-linkage, processes is as ground the mechanical stress of thinning process generation and the harmomegathus that multi-step baking brings, cause crackle, warpage, peel off, infiltration, glue overflows, disconnected poor short circuit problem occurs, finally, along with the development of wafer towards the large scale directions such as 12 inches, under the more and more higher trend of the requirement of wafer scale (siliceous through hole TSV) the multi-functional encapsulation of packaged chip, under prior art condition, operation faces various problems, as unclean, the particle contamination of developing, the disconnected short circuit problem of silicon wafer warpage (warpage) etc., and it is extremely difficult to avoid bad problem, thereby directly affect output and yield, production technology is faced adverse conditions, yield cost advantage no longer, thereby the competitiveness of restriction company product.
Summary of the invention
In order to overcome above-mentioned defect, the invention provides a kind of MEMS wafer level packaging structure and method for packing, adopt glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4), in wafer-level packaging, chip (IC) is carried out to air tight housing and cover envelope protection, can effectively overcome liquid photopolymerizable solder resist (the being commonly called as green oil) material of certain viscosity because of exposure, the particle that developing process flow process causes IC face, excessive glue pollution and bonding are bad, and the crackle producing because of photic solder resist (being commonly called as green oil) material factor in successive process, peel off, the bad problems such as disconnected short circuit.
The present invention for the technical scheme that solves its technical problem and adopt is: a kind of MEMS wafer level packaging structure, comprise wafer, this wafer has two relative sides, several chips of arranging of rule on one of them side, described encapsulating structure also comprises optical glass and epoxy resin disk, on described epoxy resin disk, each chip position place of corresponding described wafer forms respectively a through hole, two opposite flanks of this epoxy resin disk form one with the corresponding pressing in side of described optical glass and a side that is provided with chip of wafer respectively, and the through hole on the corresponding described epoxy resin disk of the difference of the chip described in during pressing on wafer.
As a further improvement on the present invention, described optical glass and epoxy resin disk are all in the same size with the profile of described wafer.
As a further improvement on the present invention, between two opposite flanks of described epoxy resin disk and described optical glass and wafer respectively after coated with adhesive corresponding pressing form one.
As a further improvement on the present invention, described epoxy resin disk is that glass-epoxy copper-clad plate heat proof material is made.
As a further improvement on the present invention, the through hole on described epoxy resin disk adopts laser boring to form.
The present invention also provides a kind of method for packing of MEMS wafer level packaging structure as above, comprises the following steps:
1. prepare optical glass and epoxy resin base plate, according to the shape of wafer to be packaged, epoxy resin base plate is cut and formed and wafer profile epoxy resin disk of the same size, then on the epoxy resin disk cutting at this, punching forms several through holes, and each chip position on the corresponding wafer of the position of through hole difference;
2. by above-mentioned wafer, epoxy resin disk and optical glass in order pressing form one, and the IC face of this wafer is over against epoxy resin disk, and the IC position of this wafer lead to the hole site of corresponding described epoxy resin respectively.
As a further improvement on the present invention, described step 2. in, first by described epoxy resin disk gluing and and optical glass be good for and close formation one, it is cavity that the lead to the hole site place of corresponding described epoxy resin disk forms cavity wall successively, and then by the epoxy resin base plate of this one and optical glass and described wafer is strong closes, and the chip face of the wafer described epoxy resin disk of fitting described in during strong closing, the chip position of this wafer is corresponding to described cavity position simultaneously.
The invention has the beneficial effects as follows:
The epoxide resin material that the present invention adopts has the following advantages than former photic solder resist (being commonly called as green oil) material: this epoxide resin material source is marketing material common on market, and can take the common mode that cuts to be processed into 8 inches or the 12 inches of wafer size patterns that coupling needs, the size that Huo You supplier supply cuts, is more conducive to save material, process time and convenient keeping and uses at any time; The present invention by material, cut that the punching of shaping, material all can process when the supplied materials on request or in common working region from processing, the excessive glue having caused while having reduced particle that the exposure of former green oil technique, developing process flow process cause IC face, gluing and bonding, glue-free or bonding is bad, the crackle causing when successive process attenuate, Reflow Soldering, cutting, the bad items such as short circuit, infiltration of peeling off, break, these bad items are in wafer scale (siliceous through hole TSV) encapsulation or wafer stage chip encapsulation, to affect the main bad item of quality, yield; The present invention can also reduce the difficulty of rear processing procedure processing, and improving product yield, further reduces operating cost, meets the requirement of punctual delivery, the requirement that the multifunction chip that meeting client increases day by day encapsulates; Therefore the present invention can adapt to large scale wafer as the Wafer level packaging requirement of eight cun, 12 inches and large chip size.
Simultaneously, due to the availability of glass-epoxy copper-clad plate flame resistant material (be called for short FR-4 or FR4) and can carry out operation on existing equipment, do not add again new equipment, reduced processing step, shortened Production Time, what met wafer-level packaging airtightly covers envelope requirement; Promote the requirement of punctual delivery, reduced equipment cost. the difficulty of processing procedure processing after reducing, can improving product yield, the function of chip is not had to harmful effect, client and entreprise cost are all decreased; The requirement that the multifunction chip that meeting client increases day by day encapsulates, reduces operating cost, has improved the competitiveness of product.
In a word, it is low that the epoxide resin material that the present invention adopts also has cost, and economic environmental protection is pollution-free, should process, and availability is good, market these technique raw material on sale, and more former technique has good stability. and be direction current and that later develop.
Accompanying drawing explanation
Fig. 1 is wafer cross-sectional view described in the embodiment of the present invention;
Fig. 2 is optical glass cross-sectional view described in the embodiment of the present invention;
Fig. 3 is that epoxy resin is sheared pre-structure schematic diagram described in the embodiment of the present invention;
Fig. 4 be described in the embodiment of the present invention epoxy resin shear after structural representation;
Fig. 5 is cross-sectional view after epoxy resin punching described in the embodiment of the present invention;
Fig. 6 is wafer described in the embodiment of the present invention, epoxy resin base plate and optical glass contraposition stitching state structural representation;
Fig. 7 is the strong rear wafer packaging structure schematic diagram that closes of the present invention.
By reference to the accompanying drawings, make the following instructions:
1---wafer 11---IC
2---epoxy resin disk 21---through hole
3---optical glass 20---epoxy resin base plate
The specific embodiment
By reference to the accompanying drawings, the present invention is elaborated, but protection scope of the present invention is not limited to following embodiment, the simple equivalence of in every case being done with the present patent application the scope of the claims and description changes and modifies, within all still belonging to patent covering scope of the present invention.
A method for packing for MEMS wafer level packaging structure, comprises the following steps:
First, prepare optical glass 3(as Fig. 2) and epoxy resin base plate 20(as Fig. 3), the epoxy resin base plate of selecting in this example is glass-epoxy copper-clad plate heat proof material (being called for short FR-4 or FR4), when selecting, can be according to the thickness of chip wafer product, through wafer size size and the chip length and width of broadwise and customer requirement or design, select suitable epoxy resin base plate, and cut into (6 along the longitude and latitude direction of epoxy resin base plate, 8,12 inches) epoxy resin disk 2(as Fig. 4,5), and identify longitude and latitude direction; And then according to the chip 11 size Aspect Ratios of wafer 1, to epoxy resin disk 2 carry out laser boring form be applicable to size through hole 21(as Fig. 6), these through hole 21 positions are corresponding with chip 11 positions on wafer, then by the surface particles of cleaning or clean air blows down this epoxy resin disk 2, then detect, epoxy resin disk 2 screenings of longitude and latitude direction and punching process exception are fallen;
Then, adopt the wafer bonding method of intermediate layer adhesive bonding, gluing on above-mentioned epoxy resin disk 2, carry out preliminary bonding and detect with above-mentioned optical glass 3, to there is bubble or have the epoxy resin disk of skew and the processing of the key compound heavy industry of optical glass, the cavity of the key compound of normal epoxy resin disk and optical glass is proceeded gluing and is carried out bonding (as Fig. 7) after contraposition with wafer, bonding temperature requires to set according to glass transition temperature (Tg) point of glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) and the pressure of wafer bonding, after bonding, chip wafer is checked, prevent that the reasons such as equipment fault from causing skew or having the bad problems such as bubble, and bad chip is carried out to sign.Complete the encapsulation process to chip wafer, form MEMS wafer level packaging structure as shown in Figure 7.
This MEMS wafer level packaging structure, comprise wafer 1, optical glass 3 and epoxy resin disk 2, this wafer has two relative sides, several chips 11 of arranging of rule on one of them side, on epoxy resin disk, each chip position place of corresponding wafer forms respectively a through hole 21, two opposite flanks of this epoxy resin disk form one with the corresponding pressing in side of optical glass and a side that is provided with chip of wafer respectively, and the through hole on corresponding described epoxy resin disk respectively of the chip on wafer described in during pressing.
Preferably, in above-mentioned encapsulating structure, described optical glass and epoxy resin disk are all in the same size with the profile of described wafer, between two opposite flanks of described epoxy resin disk and described optical glass and wafer, corresponding pressing forms one after coated with adhesive respectively, described epoxy resin disk is that glass-epoxy copper-clad plate heat proof material is made, and the through hole on described epoxy resin disk adopts laser boring to form.
The epoxy resin-matrix plate material that the present invention selects is glass-epoxy copper-clad plate flame resistant material (being called for short FR-4 or FR4), for halogen-free, (refer to and do not contain halogen: the prepreg base material elements such as fluorine, bromine, iodine), having certain fusing point is glass transition temperature (Tg point) (130～210 ℃), there are the features such as moisture resistance, chemical resistance, resistance to stability, at high temperature, under being particularly heated after moisture absorption, the mechanical strength of its material, dimensional stability, cementability, water imbibition, pyrolytic, thermal expansivity are better than green oil material.In addition, glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) also has following advantage: have higher mechanical performance and dielectric properties, good heat resistance and moisture resistivity, and there is a good machining property, electrical insulation capability is stable, flatness is good, smooth surface, without pit, thickness deviation standard, be applicable to being applied to the product of high-performance electronic insulating requirements; Glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) processing procedure characteristic: (1) FR-4 processing procedure pressing plate fusing point (203 ℃); (2) high chemical resistance; (3) low-loss coefficient (Df0.0025); (4) stable and low dielectric constant (Dk2.35); (5) thermoplastic; Therefore in circuit turn on process, do not affect the opering characteristic of electric apparatus of original wafer stage chip encapsulation.
The present invention, by glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) is cut to shaping, punching, material shaping, glass bonding, Wafer alignment, bonding, forms covering of wafer IC face is sealed to protection; Glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) cuts shaping, material punching all can process on request when supplied materials or the processing certainly in common working region, material thickness is only at 30～100 micrometer ranges, therefore chip gross thickness only increases less than 100 microns, follow-up flow process and Reflow Soldering assembling production are not exerted an influence; Glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) can reach client's multi-line and connect on the chip of same size, the designing requirement that pad spacing is less.All designs do not need to increase process apparatus, only, in original package design technical foundation, change a step Treatment technique for processing and can reach the technological process needing. meet the demand in client's different designs.
In wafer scale (siliceous through hole TSV) encapsulation or wafer stage chip encapsulation technology; it is to pass through adhesive technology that wafer IC face is carried out to the method that air tight housing covers envelope protection; adhesive wafer bonding is to adopt a kind of bonding method of Intermediate Layer Bonding (as glass; polymer; resist, polyimides).At the upper gluing of photic solder resist (being commonly called as green oil) material or glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) and carry out contraposition with wafer, under uniform temperature and pressure, bonding forms the method for covering envelope protection to wafer IC face being carried out to air tight housing; Glass-epoxy copper-clad plate flame resistant material (FR-4 or FR4) has accurate temperature and pressure is controlled, and remarkable uniformity after bonding, be applicable to many wafer sizes, and can reduce the cost of wafer scale (siliceous through hole TSV) encapsulation or wafer stage chip encapsulation; The advantages such as because bonding temperature is low, bonding quality is good, and bonding material restriction is few are widely used in fields such as wafer scale (siliceous through hole TSV) encapsulation or wafer stage chip encapsulation.
Because epoxide resin material has an even surface, attenuate after bonding in rear processing procedure, electro-deposition, cutting, during BGA process, also there is good anti-mechanical stress, when chemical erosion shows as wafer attenuate, can well tackle the mechanical stress that mechanical lapping causes, and prevent the silicon wafer warpage that the minimizing because of wafer thickness causes, deviation while reducing exposure and etching is brought can not find contraposition reference point, under-exposed or over-exposed, develop unclean, disconnected short circuit, it is bad that over etching or etching are unclean etc., in sputter (sputter)/electro-deposition (plating) process, there are good tack and adhesion, peeling off of having in Reflow Soldering (BGA) and cutting that good heat-resisting expansion and mechanical stress cause when (saw) is bad, thereby there is more excellent performance in follow-up client's reliability test.
Claims (7)
1. a MEMS wafer level packaging structure, comprise wafer (1), this wafer has two relative sides, several chips (11) of arranging of rule on one of them side, it is characterized in that: described encapsulating structure also comprises optical glass (3) and epoxy resin disk (2), on described epoxy resin disk, each chip position place of corresponding described wafer forms respectively a through hole (21), two opposite flanks of this epoxy resin disk form one with the corresponding pressing in side of described optical glass and a side that is provided with chip of wafer respectively, and the through hole on the corresponding described epoxy resin disk of the difference of the chip described in during pressing on wafer.
2. MEMS wafer level packaging structure according to claim 1, is characterized in that: described optical glass and epoxy resin disk are all in the same size with the profile of described wafer.
3. MEMS wafer level packaging structure according to claim 1 and 2, is characterized in that: between two opposite flanks of described epoxy resin disk and described optical glass and wafer, corresponding pressing forms one after coated with adhesive respectively.
4. MEMS wafer level packaging structure according to claim 1 and 2, is characterized in that: described epoxy resin disk is that glass-epoxy copper-clad plate heat proof material is made.
5. MEMS wafer level packaging structure according to claim 1 and 2, is characterized in that: the through hole on described epoxy resin disk adopts laser boring to form.
6. a method for packing for the MEMS wafer level packaging structure as described in any one in claim 1 to 5, is characterized in that comprising the following steps:
1. prepare optical glass (3) and epoxy resin base plate (20), according to the shape of wafer to be packaged (1), epoxy resin base plate (20) is cut and formed and wafer profile epoxy resin disk of the same size (2), then on the epoxy resin disk cutting at this, punching forms several through holes (21), and each chip position on the corresponding wafer of the position of through hole difference;
2. by above-mentioned wafer, epoxy resin disk and optical glass in order pressing form one, and the IC face of this wafer is over against epoxy resin disk, and the IC position of this wafer lead to the hole site of corresponding described epoxy resin respectively.
7. the method for packing of MEMS wafer level packaging structure according to claim 6, it is characterized in that: described step 2. in, first by described epoxy resin disk gluing and and optical glass be good for and close formation one, it is cavity that the lead to the hole site place of corresponding described epoxy resin disk forms cavity wall successively, and then by the epoxy resin base plate of this one and optical glass and described wafer is strong closes, and the chip face of the wafer described epoxy resin disk of fitting described in during strong closing, the chip position of this wafer is corresponding to described cavity position simultaneously.
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| CN103205087A (en) * | 2012-01-16 | 2013-07-17 | 日东电工株式会社 | Resin Sheet For Hollow Encapsulation And Production Method For The Sheet, And Production Method For Hollow Electronic Part Apparatus And Hollow Electronic Part Apparatus |
| CN203582457U (en) * | 2013-11-08 | 2014-05-07 | 陈闯 | Wafer-level packaging structure for micro electro mechanical system |
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- 2013-11-08 CN CN201310552733.1A patent/CN103552977A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW544887B (en) * | 2002-05-27 | 2003-08-01 | Yi-Liang Liu | COB package structure of image sensor and the manufacturing method thereof |
| US6710461B2 (en) * | 2002-06-06 | 2004-03-23 | Lightuning Tech. Inc. | Wafer level packaging of micro electromechanical device |
| CN1677650A (en) * | 2004-03-31 | 2005-10-05 | 矽品精密工业股份有限公司 | Semiconductor package device with layer-increasing structure and making method thereof |
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Application publication date: 20140205 |