CN207165551U - The encapsulating structure of semiconductor chip - Google Patents

The encapsulating structure of semiconductor chip Download PDF

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Publication number
CN207165551U
CN207165551U CN201721130419.4U CN201721130419U CN207165551U CN 207165551 U CN207165551 U CN 207165551U CN 201721130419 U CN201721130419 U CN 201721130419U CN 207165551 U CN207165551 U CN 207165551U
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CN
China
Prior art keywords
semiconductor chip
electrode
protective layer
layer
wiring layer
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CN201721130419.4U
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Chinese (zh)
Inventor
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201721130419.4U priority Critical patent/CN207165551U/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The utility model provides a kind of encapsulating structure of semiconductor chip, and the encapsulating structure includes：Semiconductor chip, the semiconductor chip surface have electrode；Protective layer, the semiconductor chip surface is formed at, the protective layer, which corresponds to the electrode, has electrode；Encapsulating material, surround the semiconductor chip and the protective layer；Re-wiring layer, it is formed on the encapsulating material and semiconductor chip, the re-wiring layer is connected by the electrode of the protective layer with the electrode of the semiconductor chip；And metal coupling, it is made on the re-wiring layer.The utility model makes protective layer on the wafer of semiconductor chip in advance; and make electrode; position of semiconductor chip on wafer easily positions; the position of electrode can be caused accurately to be aligned with the electrode of semiconductor chip; greatly reduce the possibility of electrode contact skew; the stability of device is improved, the trend of the continuous micro of device can be met.

Description

The encapsulating structure of semiconductor chip
Technical field
The utility model belongs to field of semiconductor package, encapsulating structure and encapsulation more particularly to a kind of semiconductor chip Method.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level more and more higher, and new integrated circuit goes out Existing, encapsulation technology plays more and more important role in IC products, shared in the value of whole electronic system Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when Clock frequency develops, and encapsulation also develops to more highdensity direction.
Because fan-out wafer level encapsulates (fowlp) technology due to having the advantages that miniaturization, low cost and high integration, with And the energy efficiency with better performance and Geng Gao, fan-out wafer level encapsulation (fowlp) technology as high request movement/ The important method for packing of the electronic equipments such as wireless network, it is one of encapsulation technology most with prospects at present.
A kind of encapsulating structure of existing semiconductor chip is as shown in figure 1, this structure includes encapsulating material 102, partly led Body chip 101, re-wiring layer and metal coupling, the upper surface of the semiconductor chip 101 and the encapsulating material 102 are neat Flat, the first layer medium 103 of the re-wiring layer is directly made on the encapsulating material 102 and semiconductor chip 101, Then it is patterned to form electrode corresponding with the electrode position of the semiconductor chip, then re-forms patterned Metal level 104 is contacted by the electrode with the electrode of the semiconductor chip.
This encapsulating structure has the disadvantages that：
First, the first layer medium of the re-wiring layer is made on the encapsulating material and semiconductor chip, by It is not substantially flat in the surface of semiconductor chip, easily cause the defects of first layer medium produces flexural deformation；
Second, the first layer medium of the re-wiring layer is convexly equipped on the encapsulating material and semiconductor chip, is lacked Few protection, phenomena such as being equally easily deformed ftractureing；
3rd, due to needing to make electrode in the first layer medium, because semiconductor chip is to be independently arranged In the encapsulating material, the position of the electrode is generally difficult to completely right with the electrode of each individually semiconductor chip Should, the skew of electrode is caused, causes electrical property unstable.
Based on described above, there is provided a kind of mechanical stability that can be improved encapsulating structure and electrode contact are accurate Property, the encapsulating structure and method for packing that prevent the semiconductor chip of electrode contact skew are necessary.
Utility model content
In view of the above the shortcomings that prior art, the purpose of this utility model is to provide a kind of envelope of semiconductor chip Assembling structure and method for packing, for solving the packaging machinery stability and electrode contact stabilization of semiconductor chip in the prior art The problem of relatively low.
In order to achieve the above objects and other related objects, the utility model provides a kind of encapsulating structure of semiconductor chip, The encapsulating structure includes：Semiconductor chip, the semiconductor chip surface have electrode；Protective layer, it is formed at and described partly leads Body chip surface, the protective layer, which corresponds to the electrode, has electrode；Encapsulating material, surround the semiconductor chip and institute State protective layer；Re-wiring layer, it is formed on the encapsulating material and semiconductor chip, the re-wiring layer passes through the guarantor The electrode of sheath is connected with the electrode of the semiconductor chip；And metal coupling, it is made on the re-wiring layer.
Preferably, the protective layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass One or both of glass combination of the above.
Preferably, the side wall of the protective layer is surrounded completely by the encapsulating material, and the upper surface of the protective layer is exposed Same plane is in the encapsulating material, and with the upper surface of the encapsulating material.
Preferably, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
Preferably, the re-wiring layer includes patterned metal wiring layer and patterned dielectric layer, the gold Category wiring layer is connected by the electrode of the protective layer with the electrode of the semiconductor chip.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium One or more combination.
Preferably, the metal coupling includes copper post, the nickel dam positioned at the copper post upper surface and positioned at the nickel dam On solder bump.
Preferably, the metal barrier includes nickel dam, and the material of the solder bump includes one kind in lead, tin and silver Or include the alloy of any one above-mentioned solder metal.
The utility model also provides a kind of method for packing of semiconductor chip, and the method for packing includes：1) it is brilliant to provide one Circle, the crystal column surface have the electrode of semiconductor chip；2) protective layer is formed in the crystal column surface, and removes the electrode For the protective layer on surface to form electrode, the wafer is cut has the semiconductor core of protective layer to obtain surface Piece；3) support substrate is provided, separating layer is formed in the support substrate surface；4) semiconductor chip is adhered to described In separating layer, wherein, the semiconductor chip has the one of protective layer facing to the separating layer；5) using encapsulating material to institute State semiconductor chip to be packaged, the encapsulating material coats the semiconductor chip and the protective layer；6) based on described point Absciss layer separates the encapsulating material and the support substrate；7) in making rewiring on the encapsulating material and semiconductor chip Layer, the re-wiring layer are connected by the electrode of the protective layer with the electrode of the semiconductor chip；And 8) in Metal coupling is made on the re-wiring layer.
Preferably, the protective layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass One or both of glass combination of the above.
Preferably, the support substrate includes glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramics One kind in substrate；The separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer uses spin coating work first Skill is coated on the support substrate surface, then makes its curing molding using ultra-violet curing or heat curing process.
Preferably, step 5) includes compression forming, transfer modling using the method for the encapsulating material encapsulation logic chip One kind in shaping, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material include polyimides, silica gel and asphalt mixtures modified by epoxy resin One kind in fat.
Preferably, step 7) makes the re-wiring layer as alternately following steps：Using chemical vapor deposition work Skill, evaporation process, sputtering technology, electroplating technology or chemical plating process form gold in the encapsulating material and semiconductor chip surface Belong to layer, and the metal level is performed etching to form patterned metal wiring layer, the metal wiring layer passes through the electrode Perforate is connected with the electrode of the semiconductor chip；Using chemical vapor deposition method or physical gas-phase deposition in the gold Dielectric layer is formed on category wiring layer, and the dielectric layer is performed etching to form patterned dielectric layer.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium One or more combination.
Preferably, step 8) includes：8-1) the metal under making salient point on the re-wiring layer；8-2) in the salient point Lower metal surface forms copper post；8-3) metal barrier is formed in the copper post surface；8-4) in the metal barrier layer surface Solder metal is formed, and solder bump is formed in the metal barrier layer surface using high temperature reflow processes.
Preferably, wherein, the metal barrier includes nickel dam, and the material of the solder bump is included in lead, tin and silver One kind or include the alloy of any one above-mentioned solder metal.
As described above, the encapsulating structure and method for packing of semiconductor chip of the present utility model, have the advantages that：
First, the utility model makes protective layer on the wafer of semiconductor chip in advance, and makes electrode, in crystalline substance Position of semiconductor chip on circle easily positions, can cause electrode position and semiconductor chip electrode it is accurately right Standard, the possibility of electrode contact skew is greatly reduced, the stability of device is improved, becoming for the continuous micro of device can be met Gesture；
Second, sink into encapsulating material in protective layer of the present utility model, the mechanical strength of protective layer can be greatly improved And stability, the protective layer can be as the first layer medium of re-wiring layer, while solves the machinery of re-wiring layer Strength problem and alignment issues；
3rd, the utility model technique and simple in construction can effectively improve the encapsulation performance of semiconductor chip, in semiconductor Encapsulation field is with a wide range of applications.
Brief description of the drawings
Fig. 1 is shown as a kind of encapsulating structure schematic diagram of semiconductor chip of the prior art.
Fig. 2~Figure 13 is shown as the structural representation that each step of method for packing of semiconductor chip of the present utility model is presented Figure.
Component label instructions
201 support substrates
202 separating layers
203 encapsulating materials
204 metal wiring layers
205 patterned dielectric layers
Metal under 206 salient points
207 metal couplings
301 wafers
302 electrodes
303 protective layers
304 electrodes 304
30 semiconductor chips
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the present utility model easily.The utility model can also be by addition Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Refer to Fig. 2~Figure 13.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model, when the component relevant with the utility model is only shown in illustrating then rather than being implemented according to reality Component count, shape and size are drawn, and it is actual when implementing kenel, quantity and the ratio of each component can be a kind of changing arbitrarily Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 2~Figure 13, the present embodiment provides a kind of method for packing of semiconductor chip, the method for packing bag Include：
As shown in Fig. 2 step 1) is carried out first, there is provided a wafer 301, the surface of wafer 301 have semiconductor chip Electrode 302.
As an example, being made in the wafer 301 there are multiple semiconductor chips 30, there is electricity on the semiconductor chip 30 Pole 302.
As shown in Fig. 3~Fig. 6, step 2) is then carried out, forms protective layer 303 in the surface of wafer 301, and remove institute The protective layer 303 on the surface of electrode 302 is stated to form electrode 304, the wafer 301 is cut to be had to obtain surface The semiconductor chip 30 of protective layer 303.
As an example, the protective layer 303 includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, contain One or both of fluorine glass combination of the above.In the present embodiment, the protective layer 303 is from being PI, using coating processes The surface of wafer 301 is formed at, as shown in Figure 3.Polyimides (PI) have high temperature resistant, high mechanical properties, high-insulativity, easily The advantages that processing, the performance of the protective layer 303 is greatly improved, be considered as the first of re-wiring layer of the present utility model Layer medium, so as to improve the performance of the re-wiring layer.
As an example, use laser drilling process in the protective layer 303 to form electrode 304, such as Fig. 4 institutes Show.
As an example, the wafer 301 is cut using laser cutting or mechanical cutting processes, to obtain surface tool The semiconductor chip 30 of matcoveredn 303, as shown in figures 5 and 6.
As shown in fig. 7, step 3) is carried out first, there is provided a support substrate 201, formed in the surface of support substrate 201 Separating layer 202.
As an example, the support substrate 201 include glass substrate, metal substrate, Semiconductor substrate, polymer substrate and One kind in ceramic substrate.In the present embodiment, the support substrate 201 is from being glass substrate, the glass substrate cost It is relatively low, separating layer 202 easily is formed on its surface, and the difficulty of follow-up stripping technology can be reduced.
As an example, the separating layer 202 includes one kind in adhesive tape and polymeric layer, the polymeric layer uses first Spin coating proceeding is coated on the surface of support substrate 201, then makes its curing molding using ultra-violet curing or heat curing process.
In the present embodiment, for the separating layer 202 from being adhesive tape, the adhesive tape cost is relatively low, and in follow-up separation Only need to apply a power in technique and raised, adhesion and separating technology are all relatively simple, can greatly save whole technique Cost.
As shown in figure 8, then carrying out step 4), the semiconductor chip 30 that surface has protective layer 303 is adhered to In the separating layer 202, wherein, the semiconductor chip 30 has the one of protective layer 303 facing to the separating layer 202.
As an example, the protective layer 303 is closely connected with the separating layer 202 so that the separating layer 202 with it is described Electrode 304 forms confined space, to prevent follow-up encapsulating material 203 enters in the electrode 304 from causing electrode The blocking of perforate 304.
As shown in figure 9, then carrying out step 5), addressed semiconductor chip 30 is packaged using encapsulating material 203, The encapsulating material 203 coats the semiconductor chip 30 and the protective layer 303.Sink into package material in the protective layer 303 In material 203, the mechanical strength and stability of protective layer 303 can be greatly improved.
As an example, the method for the semiconductor chip 30 is encapsulated using encapsulating material 203 includes compression forming, transmission mould The one kind being moulded into type, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material 203 include polyimides, silica gel and ring One kind in oxygen tree fat.
As an example, thickness of the thickness of the encapsulating material 203 at least above addressed semiconductor chip 30.
As shown in Figure 10, then carry out step 6), based on the separating layer 202 separate the encapsulating material 203 with it is described Support substrate 201.
As an example, the encapsulating material 203 is raised from the separating layer 202 by applying a power, you can realize and divide From.
As shown in Figure 11~Figure 12, step 7) is then carried out, is made on the encapsulating material 203 and semiconductor chip 30 Re-wiring layer, the re-wiring layer pass through the electrode 304 of the protective layer 303 and the electricity of the semiconductor chip 30 Pole 302 connects.
Specifically, making the re-wiring layer includes：
Step a), using chemical vapor deposition method or physical gas-phase deposition in the encapsulating material 203, semiconductor Metal level is formed on chip 30 and the protective layer 303, and the metal level is performed etching to form patterned metal line Layer 204, the metal wiring layer 204 passes through the electrode 304 of the protective layer 303 and the electrode of the semiconductor chip 30 302 connections.
As an example, the material of the metal wiring layer 204 include copper, aluminium, nickel, gold, silver, one or both of titanium with Upper combination.In the present embodiment, the material selection of the metal wiring layer 204 is copper.
Step b), using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in The surface of patterned metal wiring layer 204 forms dielectric layer, and the dielectric layer is performed etching to form patterned Jie Matter layer 205.
As an example, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass One or both of glass, fluorine-containing glass combination of the above.In the present embodiment, it is silica that the dielectric layer, which is selected,.
It should be noted that the re-wiring layer can include the multiple dielectric layers stacked gradually and multiple hardware cloths Line layer 204, according to line demand, each layer metal wiring layer is realized by each dielectric layer being patterned or being made through hole Interconnection between 204, to realize the line demand of difference in functionality.
As shown in figure 13, step 8) is finally carried out, in making metal coupling 207 on the re-wiring layer.
As an example, the metal coupling 207 can be the combination of metal column, solder ball or copper post and solder metal Deng.
In the present embodiment, step 8) includes：
Step 8-1), the metal 206 under making salient point on the re-wiring layer；
Step 8-2), the surface of metal 206 forms copper post under the salient point；
Step 8-3), form metal barrier in the copper post surface；And
Step 8-4), solder metal is formed in the metal barrier layer surface, and using high temperature reflow processes in the gold Belong to barrier layer surface and form solder bump.
Wherein, the metal barrier includes nickel dam, the material of the solder bump include one kind in lead, tin and silver or Include the alloy of any one above-mentioned solder metal.
As shown in figure 13, the present embodiment also provides a kind of encapsulating structure of semiconductor chip, and the encapsulating structure includes：Half Conductor chip 30, the surface of semiconductor chip 30 have electrode 302；Protective layer 303, it is formed at the table of semiconductor chip 30 Face, the corresponding electrode 302 of the protective layer 303 have electrode 304；Encapsulating material 203, surround the semiconductor chip 30 and the protective layer 303；Re-wiring layer, it is formed on the encapsulating material 203 and semiconductor chip 30, the cloth again Line layer is connected by the electrode 304 of the protective layer 303 with the electrode 302 of the semiconductor chip 30；And metal is convex Block 207, it is made on the re-wiring layer.
As an example, the protective layer 303 includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, contain One or both of fluorine glass combination of the above.
As an example, the side wall of the protective layer 303 is surrounded completely by the encapsulating material 203, the protective layer 303 Upper surface is exposed to the encapsulating material 203, and is in same plane with the upper surface of the encapsulating material 203.
As an example, the encapsulating material 203 includes one kind in polyimides, silica gel and epoxy resin.
As an example, the re-wiring layer includes patterned metal wiring layer 204 and patterned dielectric layer 205, the metal wiring layer 204 passes through the electrode 304 of the protective layer 303 and the electrode of the semiconductor chip 30 302 are connected.
As an example, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass One or both of glass, fluorine-containing glass combination of the above, the material of the metal wiring layer 204 include copper, aluminium, nickel, gold, silver, One or both of titanium combination of the above.
As an example, the metal coupling 207 includes copper post, the nickel dam positioned at the copper post upper surface and positioned at institute State the solder bump on nickel dam.
As an example, the metal barrier includes nickel dam, the material of the solder bump includes one in lead, tin and silver Kind or the alloy for including any one above-mentioned solder metal.
As described above, the encapsulating structure and method for packing of semiconductor chip of the present utility model, have the advantages that：
First, the utility model makes protective layer 303 on the wafer 301 of semiconductor chip in advance, and makes electrode and open Hole 304, the position of semiconductor chip on wafer 301 easily position, and can cause position and the semiconductor core of electrode 304 The electrode 302 of piece is accurately aligned, and is greatly reduced the possibility of the contact skew of electrode 302, is improved the stability of device, can be with Meet the trend of the continuous micro of device；
Second, sink into encapsulating material 203 in protective layer 303 of the present utility model, protective layer 303 can be greatly improved Mechanical strength and stability, the protective layer 303 can be as the first layer medium of re-wiring layer, while solves cloth again The problems of mechanical strength and alignment issues of line layer；
3rd, the utility model technique and simple in construction can effectively improve the encapsulation performance of semiconductor chip, in semiconductor Encapsulation field is with a wide range of applications.
So the utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited Type.Any person skilled in the art can all be carried out without prejudice under spirit and scope of the present utility model to above-described embodiment Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model God and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.

Claims (8)

1. a kind of encapsulating structure of semiconductor chip, it is characterised in that the encapsulating structure includes：
Semiconductor chip, the semiconductor chip surface have electrode；
Protective layer, the semiconductor chip surface is formed at, the protective layer, which corresponds to the electrode, has electrode；
Encapsulating material, surround the semiconductor chip and the protective layer；
Re-wiring layer, it is formed on the encapsulating material and semiconductor chip, the re-wiring layer passes through the protective layer Electrode be connected with the electrode of the semiconductor chip；And
Metal coupling, it is made on the re-wiring layer.
2. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The protective layer includes asphalt mixtures modified by epoxy resin One or both of fat, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass combination of the above.
3. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The side wall of the protective layer is by institute State encapsulating material to surround completely, the upper surface of the protective layer is exposed to the encapsulating material, and upper with the encapsulating material Surface is in same plane.
4. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulating material includes polyamides One kind in imines, silica gel and epoxy resin.
5. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The re-wiring layer includes figure The metal wiring layer of shape and patterned dielectric layer, electrode and institute of the metal wiring layer by the protective layer The electrode for stating semiconductor chip is connected.
6. the encapsulating structure of semiconductor chip according to claim 5, it is characterised in that：The material of the dielectric layer includes One or both of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass combination of the above, it is described The material of metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
7. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The metal coupling includes copper Post, the nickel dam positioned at the copper post upper surface and the solder bump on the nickel dam.
8. the encapsulating structure of semiconductor chip according to claim 7, it is characterised in that：The metal barrier includes nickel Layer, the material of the solder bump include one kind in lead, tin and silver or include the alloy of any one above-mentioned solder metal.
CN201721130419.4U 2017-09-05 2017-09-05 The encapsulating structure of semiconductor chip Active CN207165551U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369664A (en) * 2017-09-05 2017-11-21 中芯长电半导体（江阴）有限公司 The encapsulating structure and method for packing of semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369664A (en) * 2017-09-05 2017-11-21 中芯长电半导体（江阴）有限公司 The encapsulating structure and method for packing of semiconductor chip

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