TW582083B - Fixture for die-pull test - Google Patents
Fixture for die-pull test Download PDFInfo
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- TW582083B TW582083B TW92109182A TW92109182A TW582083B TW 582083 B TW582083 B TW 582083B TW 92109182 A TW92109182 A TW 92109182A TW 92109182 A TW92109182 A TW 92109182A TW 582083 B TW582083 B TW 582083B
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582083582083
五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種覆晶封裝構造之晶片凸塊杈力、 試之治具(fixture for die-pull test),更特別係有貝】 於一種覆晶封裝構造之面固定(f a c e - f i x e d)之晶片& 胃 ^ % -fer 力測試之治具。 【先前技術】 一般而言,覆晶封裝構造(Flip Chip Package)包含 一基板、一晶片利用覆晶技術安裝於該基板、以及銲锡或 金凸塊(solder or gold bump)用以將該晶片電性連接至 該基板。一填膠(underf i 1 1)可另填充於該晶片與基板 間,藉以包封該基板、該晶片及該凸塊。為了解覆晶接合 之可靠度,故需要進行晶片凸塊拉力測試(die puli test)。 參考第1圖,其顯示先前技術之一晶片凸塊拉力測試 之治具1 8,一覆晶封裝構造1 5係穩固的固定於其上。該覆 晶封裝構造15具有一基板14及一晶片12藉由凸塊16配置於 該基板1 4上。該晶片凸塊拉力測試之治具1 8具有兩凹槽 20,用以夾住該基板14之兩側。一黏著層24係塗覆於該覆 晶封裝構造1 5之該晶片1 2上,將該晶片1 2黏著至一萬能材 料试驗機(Universal testing machine)(圖中未示)之一 測試頭(TestingHeadorJig)22 上。 j 參考第2圖,於該測試過程中,該測試頭2 2係為該萬 能材料試驗機向上驅動,藉以對該晶片1 2向上施加作用 力。隨著該測試頭22向上移動,該晶片及該基板間之結V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a wafer bump force and a fixture for die-pull test of a flip-chip package structure, and more particularly to a shell] Face-fixed chip & stomach ^% -fer force test fixture in a flip-chip package structure. [Previous technology] Generally, a flip chip package includes a substrate, a wafer mounted on the substrate using flip-chip technology, and solder or gold bumps for the wafer. It is electrically connected to the substrate. An underfill (underf i 1 1) can be filled between the wafer and the substrate to encapsulate the substrate, the wafer and the bump. In order to understand the reliability of flip-chip bonding, a die puli test is required. Referring to FIG. 1, which shows a jig 18 for a wafer bump tensile test according to one of the prior arts, a flip-chip package structure 15 is firmly fixed thereto. The flip-chip package structure 15 has a substrate 14 and a wafer 12 disposed on the substrate 14 through bumps 16. The jig 18 for the wafer bump tensile test has two grooves 20 for clamping both sides of the substrate 14. An adhesive layer 24 is coated on the wafer 12 of the flip-chip package structure 15. The wafer 12 is adhered to a test head of a universal testing machine (not shown). (TestingHeadorJig) on 22. j Referring to FIG. 2, during the test, the test head 22 is driven upward for the universal material testing machine, so as to apply upward force to the wafer 12. As the test head 22 moves upward, the junction between the wafer and the substrate
00642.ptd 第6頁 582083 五、發明說明(2) 構,諸如該凸塊16及凸塊下金屬層(Under Bump Metallurgy ;UBM)(圖中未示)承受拉伸應力(tensile stress)而變形,且進一步斷裂,使得該晶片12與該基板 1 4分離。 然而,前述之該晶片凸塊拉力測試之治具1 8僅僅固定 該基板1 4的邊緣,因此當該基板1 4係為一撓性基板,諸如 FR-4及BT樹脂基板時,於測試過程中,該基板14會產生彎 曲。於此情況下,該凸塊1 6將不僅承受正向的拉伸應力, 同時亦承受剪應力(shearing stress)。再者,該基板14 的彎曲亦造成應力集中於該凸塊16中之外圍凸塊上。因 此,此一測試過程中所獲得的數據,係大幅度的低於該基 板1 4與該晶片1 2實際可承受之正向作用力。 再者’於此一配置下,測試或斷裂後之該基板丨4及該 晶片1 2係固定於該治具1 8上,且通常會藉由光學顯微鏡 (optical microscope ;〇M)或電子顯微鏡(scanning electron microscope ;SEM)觀察該凸塊16之破壞模式 (failure mode)。然而,該治具a之可運作之高度往往無 法與該光學顯微鏡或電子顯微鏡相配合,而無法進行破獲 模式之觀察。 有鑑於此,便有需供一種晶片凸塊拉力測試之治具,00642.ptd Page 6 582083 V. Description of the invention (2) Structures, such as the bump 16 and the Under Bump Metallurgy (UBM) (not shown) are deformed under tensile stress And further break, so that the wafer 12 is separated from the substrate 14. However, the aforementioned fixture 18 for the wafer bump tensile test only fixes the edge of the substrate 14, so when the substrate 14 is a flexible substrate, such as FR-4 and BT resin substrate, during the test process In this case, the substrate 14 is bent. In this case, the bump 16 will not only withstand the tensile stress in the forward direction, but also with the shearing stress. Furthermore, the bending of the substrate 14 also causes stress to be concentrated on the peripheral bumps in the bumps 16. Therefore, the data obtained during this test are significantly lower than the actual forward force that the substrate 14 and the wafer 12 can withstand. Furthermore, in this configuration, the substrate 4 and the wafer 12 after the test or break are fixed on the jig 18, and usually through an optical microscope (OM) or an electron microscope. (Scanning electron microscope; SEM) Observe the failure mode of the bump 16. However, the operational height of the jig a often cannot be matched with the optical microscope or the electron microscope, and observation of the cracking mode cannot be performed. In view of this, there is a need for a jig for a wafer bump tensile test.
用以克服前述的問題。 【發明内容】 本發明之一目的在於提供一種 具,以面固定的方式,對丰邋辦仏 %权供一種晶片凸塊拉力測試之治 對半導體封裝構造施力,藉以正確To overcome the aforementioned problems. [Summary of the Invention] An object of the present invention is to provide a method for fixing a semiconductor chip in a surface-fixed manner for a wafer bump tensile test to apply force to a semiconductor package structure so as to be correct.
第7頁 582083 五、發明說明(3) 的量測該半導體覆晶封裝構造之抗拉強度。 為達上述目的,本發明提供一種治具,應用於一覆晶 封裝構造之晶片凸塊拉力測試。該晶片凸塊拉力測試之治 具包含一第一平台及一第二平台。該第一平台係面固定的 支撐該覆晶封裝構造之該基板。該第二平台係面固定的支 撐該覆晶封裝構造之該半導體晶片,並與一外部之萬能材 料試驗機(Uni vers al test ing machine)之一測試頭相連 接。 根據本發明之該晶片凸塊拉力測試之治具,其係藉由 兩平台,面固定地支撐該半導體封裝構造之基板及半導體 晶片。該覆晶封裝構造之基板以及半導體晶片係以整個表 面固定於該平台上。因此,於測試過程中,該基板將不致 於產生彎曲或變形,而影響測試的結果。 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯’下文特舉本發明較佳實施例,並配合所附圖示,作 詳細說明如下。 【實施方式】 現請參考第3圖’其顯示根據本發明之一晶片凸塊拉 力測試之治具5 0 ’用以對一覆晶封裝構造5 5進行晶片凸塊 拉力測試。該覆晶封裝構造55具有一基板54及一半導體焉 片5 2 ’藉由覆晶技術連接於該基板5 4上。 I芝 該晶片凸塊拉力測試之治具5 〇包括一托架5 8以及一固 定平台60。該晶片凸塊拉力測試之治具5〇另包括一測試平 台64 ’與一萬能材料試驗機之一測試頭(Testing Head orPage 7 582083 V. Description of the invention (3) Measure the tensile strength of the semiconductor flip-chip package structure. To achieve the above object, the present invention provides a jig, which is applied to a wafer bump tensile test of a flip-chip package structure. The jig for pulling the wafer bump includes a first platform and a second platform. The first platform is fixedly supporting the substrate of the flip-chip package structure. The second platform fixedly supports the semiconductor wafer of the flip-chip package structure and is connected to a test head of an external universal testing machine. According to the jig for testing the tensile strength of the wafer bump according to the present invention, the semiconductor package structure substrate and the semiconductor wafer are fixedly supported by two platforms. The substrate and semiconductor wafer of the flip-chip package structure are fixed on the platform with the entire surface. Therefore, during the test, the substrate will not be bent or deformed, which will affect the test results. In order to make the above and other objects, features, and advantages of the present invention more obvious, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, as follows. [Embodiment] Please refer to FIG. 3 ′, which shows a jig 50 0 ′ for a wafer bump tensile test according to the present invention, to perform a wafer bump tensile test on a flip-chip package structure 55. The flip-chip package structure 55 has a substrate 54 and a semiconductor wafer 5 2 ′ connected to the substrate 54 by a flip-chip technology. The fixture 50 of the wafer bump tensile test includes a bracket 58 and a fixed platform 60. The jig for the wafer bump tensile test 50 also includes a test platform 64 ′ and one of the testing heads of a universal material testing machine (Testing Head or
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IHI 00642.ptd 第8頁 582083IHI 00642.ptd Page 8 582083
Jig) 62相連接。兩薄板70、72係可藉由諸如螺栓之類的固 定件(圖中未示)或諸如滑槽等固定裝置,分別固定於該托 架58及該固定平台60上。該薄板70、72係由剛性的材料所 製造,諸如鋼(stee 1)。 一黏著層6 8係塗覆於該薄板7 2上,用以將該覆晶封裝 構造55之該基板54黏著於該薄板72上,如此使得該基板54 能夠加裝於該固定平台6 0上。一黏著層6 6係塗覆於該薄板 70上,用以將該覆晶封裝構造55之該半導體晶片52黏著於 該薄板70上,如此使得該半導體晶片52能夠加裝於該測試 平台6 4上。 參考第4圖,於該測試過程中,該測試頭6 2係為該萬 能材料試驗機向上驅動,藉以對該晶片5 2向上施加作用 力。隨著該測試頭6 2向上移動,該晶片5 2及該基板5 4間之 元件’諸如複數個銲錫或金凸塊(solder bump or gold bump)56 及凸塊下金屬層(Under Bump Metallurgy ;UBM )(圖中未示),承受拉伸應力(tensile stress)而變形, 且進一步斷裂,使得該晶片5 2與該基板5 4分離。於該測試 過程中,該測試頭6 2之位移量及作用力會被記錄,而完& 晶片凸塊拉力測試。 艮 再者,於此一配置下,分離後之該晶片52與該基板54 仍舊藉由該黏著層6 6及該黏著層6 8,分別黏著於該該薄板 70及該薄板72上。該基板54及該晶片52可與該薄板70及該 薄板72,一併放置於光學顯微鏡(optical microscope ; 〇M)或電子顯微鏡(scanning electron microscope ;SEM)Jig) 62. The two thin plates 70 and 72 can be fixed on the bracket 58 and the fixed platform 60 by a fixing member (not shown) such as a bolt or a fixing device such as a chute. The thin plates 70, 72 are made of a rigid material, such as steel (stee 1). An adhesive layer 68 is coated on the thin plate 72 to adhere the substrate 54 of the flip-chip package structure 55 to the thin plate 72, so that the substrate 54 can be mounted on the fixed platform 60. . An adhesive layer 6 6 is coated on the thin plate 70 to adhere the semiconductor wafer 52 of the flip-chip package structure 55 to the thin plate 70, so that the semiconductor wafer 52 can be mounted on the test platform 6 4. on. Referring to FIG. 4, during the test, the test head 62 is driven upwards by the universal material testing machine, so as to apply upward force to the wafer 52. As the test head 62 moves upward, the components' between the wafer 52 and the substrate 54 are such as a plurality of solder bumps or gold bumps (solder bump or gold bump) 56 and an under bump metallurgy (Under Bump Metallurgy; UBM (not shown), deforms under tensile stress, and further breaks, so that the wafer 52 is separated from the substrate 54. During the test, the displacement and force of the test head 62 will be recorded, and the & wafer bump tensile test is completed. In addition, in this configuration, the wafer 52 and the substrate 54 are still adhered to the thin plate 70 and the thin plate 72 through the adhesive layer 6 6 and the adhesive layer 68 respectively. The substrate 54 and the wafer 52 may be placed together with the thin plate 70 and the thin plate 72 in an optical microscope (OM) or an scanning electron microscope (SEM).
00642.ptd 第9頁 582083 五、發明說明(5) 中’觀察該覆晶封裝構造55之破壞模式(faiiure mode)。 現請參考第5及6圖,其顯示根據本發明之另一實施例 之一晶片凸塊拉力測試之治具8 〇,用以對一覆晶封裝構造 8 5進行晶片凸塊拉力測試。該晶片凸塊拉力測試之治具8 〇 係與該晶片凸塊拉力測試之治具5 〇相類似,其中類似的元 件標示類似的圖號。 該晶片凸塊拉力測試之治具8〇包括一固定吸盤9〇,具 有複數個通道98與一外部真空源(圖中未示)相連接,用以 將該覆θθ封裝構造85之該基板84吸著於該固定吸盤gQ其 上。 八 該晶片凸塊拉力測試之治具8〇另包括一測試吸盤94, 與一萬能材料試驗機之一測試頭(Testing Head 〇r Jig) 92相連接。該測試吸盤94具有複數個通道96與一外部 真空源(圖中未示)相連接,用以將覆晶封裝構造“之該 導體晶片8 2吸著於該測試吸盤g 4上。 人 綜前所述,於本發明之該晶片凸塊拉力測試之治具 中,覆晶封裝構造係”面固定,,的。亦即,該覆晶封‘;暴 之基板以及半導體晶片係以整個”表面固定"於該平台 盤上。因此,於測試過程中,該基板將不致於 g曲00642.ptd Page 9 582083 V. In the description of the invention (5), ′ observe the failure mode of the flip-chip package structure 55. Please refer to FIGS. 5 and 6, which shows a jig 80 for a wafer bump tensile test according to another embodiment of the present invention, which is used to perform a wafer bump tensile test on a flip-chip package structure 85. The fixture 80 of the wafer bump tensile test is similar to the fixture 50 of the wafer bump tensile test, and similar components are marked with similar drawing numbers. The jig 80 for the wafer bump tensile test includes a fixed suction cup 90, which has a plurality of channels 98 connected to an external vacuum source (not shown), for the substrate 84 covering the θθ package structure 85 Suction on the fixed suction cup gQ. 8. The jig for testing the tensile strength of the wafer bump 80 includes a test chuck 94, which is connected to a Testing Head 〇r Jig 92, which is a universal material testing machine. The test chuck 94 has a plurality of channels 96 connected to an external vacuum source (not shown), and is used to suck the conductor wafer 8 2 of the flip-chip package structure onto the test chuck g 4. As mentioned above, in the jig for testing the tensile strength of the wafer bump of the present invention, the flip-chip package structure is “face-fixed”. That is, the flip chip substrate and the semiconductor wafer are fixed on the platform disk with the entire surface. Therefore, during the test, the substrate will not be damaged.
變形:響測試的結果。精於本技藝者將可瞭解U 台及忒覆a曰封裝構造間之面固定的方式前 1 黏著層及吸盤所限。 个以刚所所述之「 雖然前述的描述及圖示已揭示本發明之 li 必須瞭解到各種增添、•改和取代可能使用於;:::佳Deformation: The result of the loud test. Those skilled in this art will understand how to fix the surface between the U stage and the cover a. The packaging structure is limited by the adhesive layer and the suction cup. As mentioned just now, "Although the foregoing description and illustrations have revealed the invention of the invention, it must be understood that various additions, modifications and substitutions may be used in ::: 佳
00642.ptd 第10頁 582083 五、發明說明= 離如所附申請專利範圍所界定的本發明 實施例浐ί及範圍。熟悉該技藝者將可體會本發明可能使 f ί;形式、結構、#置'比例、材料、元件和組件的 修改。因此,本文於此所揭示的實施例於所有觀點,應被 視為用以說明本發明’而非用以限制本發明。本^从 圍應由後附申請專利範圍所界 X月的犯 並不限於先前的描述。 並涵盍八a法均等物,00642.ptd Page 10 582083 V. Description of the invention = departure from the scope and scope of the embodiments of the invention as defined by the scope of the attached patent application. Those skilled in the art will appreciate that the present invention may make modifications in form, structure, scale, materials, components, and components. Therefore, the embodiments disclosed herein should, in all respects, be considered to illustrate the invention 'and not to limit the invention. The crime of this month shall be bounded by the scope of the attached patent application for X months and the offender is not limited to the previous description. And contains the eighth method equivalent,
582083 圖式簡單說明 【圖式簡單說明】 第1圖:係先前技術之晶片凸塊拉力測試之治具之側面示 意圖。 第2圖:係先前技術之晶片凸塊拉力測試之治具,於測試 過程中之側面示意圖。 第3圖:係為根據本發明之一實施例之一晶片凸塊拉力測 試之治具之側面示意圖。 第4圖:係為第3圖中之該晶片凸塊拉力測試之治具,於測 試過程中之側面不意圖。 第5圖:係為根據本發明之另一實施例之一晶片凸塊拉力 測試之治具之側面示意圖。 第6圖:係為第5圖中之該晶片凸塊拉力測試之治具,於測 試過程中之側面示意圖。 圖號說明:582083 Schematic description [Schematic description] Figure 1: The side view of the jig for the wafer bump tensile test of the prior art. Figure 2: This is a side view of the jig for the wafer bump tensile test of the prior art during the test. FIG. 3 is a schematic side view of a jig for a wafer bump tensile test according to an embodiment of the present invention. Figure 4: This is the jig for the wafer bump tensile test in Figure 3. The side surface during the test is not intended. Fig. 5 is a schematic side view of a jig for testing tensile strength of a wafer bump according to another embodiment of the present invention. Fig. 6 is a schematic side view of the jig for the wafer bump tensile test in Fig. 5 during the test. Figure number description:
18 晶片凸塊拉力測試之治具 15 覆晶封裝構造 14 基板 12 晶片 16 凸塊 2 0 凹槽18 Jig for wafer bump tensile test 15 Flip-chip package structure 14 Substrate 12 Wafer 16 bump 2 0 groove
00642.ptd 第12頁 58208300642.ptd Page 12 582083
圖式簡單說明 24 黏 著 層 22 測 試 頭 50 晶 片 凸 塊 拉 力測試之治具 52 半 導 體 晶 片 54 基 板 55 覆 晶 封 裝 構 造 56 凸 塊 58 托 架 60 固 定 平 台 62 測 試 頭 64 測 試 平 台 66 黏 著 層 68 黏 著 層 70 薄 板 72 薄 板 80 晶 片 凸 塊 拉 力測試之治具 82 半 導 體 晶 片 84 基 板 85 覆 晶 封 裝 構 造 86 凸 塊 88 托 架 90 固 定 吸 盤 92 測 試 頭 94 測 試 吸 盤 96 通 道 98 通 道 00642.ptd 第13頁Brief description of the drawing 24 Adhesive layer 22 Test head 50 Jig for wafer bump tensile test 52 Semiconductor wafer 54 Substrate 55 Flip-chip package structure 56 Bump 58 Bracket 60 Fixed platform 62 Test head 64 Test platform 66 Adhesive layer 68 Adhesive layer 70 thin plate 72 thin plate 80 wafer jig pull test fixture 82 semiconductor wafer 84 substrate 85 flip chip package structure 86 bump 88 bracket 90 fixed suction cup 92 test head 94 test suction cup 96 channel 98 channel 00642.ptd page 13
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Cited By (2)
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---|---|---|---|---|
TWI447376B (en) * | 2011-05-10 | 2014-08-01 | Au Optronics Corp | Method for measuring sealant strength of lcd panel and measuring apparatus thereof |
TWI642133B (en) * | 2016-10-20 | 2018-11-21 | 矽品精密工業股份有限公司 | Mounting method for electronic component and carrying jig applying the mounting method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108666298B (en) * | 2017-03-27 | 2019-12-10 | 中芯国际集成电路制造(北京)有限公司 | Chip stress testing assembly and preparation method thereof |
-
2003
- 2003-04-17 TW TW92109182A patent/TW582083B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI447376B (en) * | 2011-05-10 | 2014-08-01 | Au Optronics Corp | Method for measuring sealant strength of lcd panel and measuring apparatus thereof |
TWI642133B (en) * | 2016-10-20 | 2018-11-21 | 矽品精密工業股份有限公司 | Mounting method for electronic component and carrying jig applying the mounting method |
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TW200423273A (en) | 2004-11-01 |
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