CN108666298B - Chip stress testing assembly and preparation method thereof - Google Patents
Chip stress testing assembly and preparation method thereof Download PDFInfo
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- CN108666298B CN108666298B CN201710186774.1A CN201710186774A CN108666298B CN 108666298 B CN108666298 B CN 108666298B CN 201710186774 A CN201710186774 A CN 201710186774A CN 108666298 B CN108666298 B CN 108666298B
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- chip
- opening
- chip stress
- stress test
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The invention provides a chip stress testing assembly and a preparation method thereof, wherein the preparation method comprises the following steps: 1) providing a chip stress test structure, wherein the chip stress test structure comprises a chip functional structure and an annular welding pad positioned above the chip functional structure; the top parts of the chip functional structure and the annular welding pad are covered with passivation protective layers; 2) forming a first opening in the passivation protection layer; 3) removing the bonding pad to form a second opening below the first opening; 4) fixing a first substrate at the bottom of the chip stress test structure obtained in the step 3); 5) placing a solder layer on the top surface of the chip stress test structure obtained in the step 4); 6) and providing a second substrate, and fixing the second substrate on the top of the chip stress test structure through a solder layer. The invention avoids the influence of the bonding layer on the stress test result of the chip and improves the reliability of the test result; and the preparation process is simple and the preparation success rate is high.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a chip stress testing assembly and a preparation method thereof.
background
The chip stress test (die pull) is a test item for effectively measuring the bonding performance between a metal layer and an insulating film layer of the existing semiconductor chip product, and the preparation method of the current chip stress test component generally comprises the following steps: the chip is directly fixed on the upper substrate and the lower substrate through the bonding layer to obtain a chip stress testing assembly, and then the obtained chip stress testing assembly is placed on a testing machine for testing. In the preparation method, the chip stress test structure is fixed on the upper substrate and the lower substrate through the bonding layers by manual operation of operators, different operators, the change of the formula of the bonding layers and the flatness of the bonding layers can influence the test result, so that the success rate of the preparation of the chip stress test assembly in the existing chip stress test is low, and the reliability of the test result is poor.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a chip stress testing assembly and a method for manufacturing the same, which are used to solve the problems in the prior art that the chip stress testing result is easily affected by the operator, the adhesive layer configuration and the flatness of the adhesive layer, and thus the success rate of manufacturing the chip stress testing assembly is low and the reliability of the testing result is poor.
in order to achieve the above and other related objects, the present invention provides a method for manufacturing the above chip stress test assembly, which at least includes the following steps:
1) Providing a chip stress test structure, wherein the chip stress test structure comprises a chip functional structure and an annular welding pad positioned above the chip functional structure, and the annular welding pad is connected with a top metal layer of the chip functional structure; the chip functional structure and the top of the annular welding pad are covered with passivation protective layers;
2) forming a first opening in the passivation protection layer, wherein the annular welding pad is exposed out of the first opening;
3) Removing the annular welding pad to form a second opening below the first opening, wherein the second opening exposes the top metal layer of the chip functional structure;
4) Providing a first substrate, and fixing the first substrate at the bottom of the chip stress test structure obtained in the step 3);
5) Placing a solder layer on the top surface of the chip stress test structure obtained in the step 4);
6) and providing a second substrate, and fixing the second substrate on the top of the chip stress test structure through the solder layer.
As a preferable scheme of the preparation method of the chip stress test assembly, in the step 2), a first opening is formed in the passivation protection layer by adopting photoetching and etching processes.
As a preferable aspect of the method for manufacturing a chip stress test assembly according to the present invention, the width of the first opening is smaller than the maximum width of the ring-shaped pad.
As a preferable scheme of the method for manufacturing the chip stress test assembly according to the present invention, in step 3), the chip stress test structure obtained in step 2) is placed in an acid solution to remove the annular pad, and a second opening is formed below the first opening.
as a preferable embodiment of the method for manufacturing a chip stress test assembly according to the present invention, in step 4), the first substrate is fixed to the bottom of the chip stress test structure obtained in step 3) through an adhesive layer.
As a preferable aspect of the method for manufacturing a chip stress test assembly according to the present invention, in step 6), the step of fixing the second substrate to the top of the chip stress test structure through the solder layer includes the steps of:
61) Placing the second substrate on the surface of the solder layer;
62) And putting the structure obtained in the step 61) in a high-temperature furnace for reflow process treatment, so that the second substrate is fixed on the top of the chip stress test structure through the solder layer.
As a preferable scheme of the method for manufacturing the chip stress test assembly of the present invention, in the step 62), the temperature of the reflow process is 150 ℃ to 300 ℃.
The invention also provides a chip stress testing assembly, which at least comprises:
The chip stress testing structure comprises a chip functional structure and a passivation protective layer positioned above the chip functional structure, wherein an opening structure is formed in the passivation protective layer, and the opening structure exposes a top metal layer of the chip functional structure;
The solder layer is positioned on the surface of the chip stress test structure and in the opening structure;
The first substrate is fixed at the bottom of the chip stress test structure;
And the second substrate is fixed at the top of the chip stress test structure through the solder layer.
As a preferable aspect of the chip stress test assembly of the present invention, the opening structure is an annular opening structure.
As a preferable aspect of the chip stress test assembly of the present invention, the number of the opening structures is two or more.
As a preferable aspect of the chip stress test assembly of the present invention, the opening structure includes a second opening located above the top metal layer of the chip functional structure and a first opening located above the second opening, and a width of the first opening is smaller than a maximum width of the second opening.
as described above, the chip stress test assembly and the preparation method thereof of the present invention have the following beneficial effects: according to the chip stress testing assembly, the opening structure of the top metal layer exposing the chip functional structure is arranged in the chip stress testing structure, the chip stress testing structure is fixed on the surface of the second substrate through the solder layer, and the solder layer is positioned on the surface of the chip stress testing structure and in the opening structure, so that the adhesion force between the chip stress testing structure and the second substrate is enhanced, compared with a chip stress testing assembly in the prior art, the influence of an adhesive layer on a chip stress testing result is avoided, and the reliability of the testing result is improved; meanwhile, the chip stress testing assembly is simple in preparation process and high in preparation success rate.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a chip stress test assembly according to a first embodiment of the invention.
Fig. 2 to 8 are schematic cross-sectional structures of steps of a method for manufacturing a chip stress test assembly according to a first embodiment of the invention. .
Description of the element reference numerals
1 chip stress test structure
111 metal layer
112 interlayer dielectric layer
113 rewiring layer
121 ring pad
124 metal plug
13 passivation protective layer
131 first passivation protective layer
132 second passivation layer
14 first opening
15 second opening
2 solder layer
3 first substrate
4 second substrate
5 adhesive layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present invention provides a method for manufacturing a chip stress test assembly, which at least includes the following steps:
1) providing a chip stress test structure, wherein the chip stress test structure comprises a chip functional structure and an annular welding pad positioned above the chip functional structure, and the annular welding pad is connected with a top metal layer of the chip functional structure; the chip functional structure and the top of the annular welding pad are covered with passivation protective layers;
2) Forming a first opening in the passivation protection layer, wherein the annular welding pad is exposed out of the first opening;
3) Removing the annular welding pad to form a second opening below the first opening, wherein the second opening exposes the top metal layer of the chip functional structure;
4) Providing a first substrate, and fixing the first substrate at the bottom of the chip stress test structure obtained in the step 3);
5) Placing a solder layer on the top surface of the chip stress test structure obtained in the step 4);
6) And providing a second substrate, and fixing the second substrate on the top of the chip stress test structure through the solder layer.
referring to step S1 in fig. 1 and fig. 2, a chip stress test structure 1 is provided, where the chip stress test structure 1 includes a chip functional structure and a ring pad 121 located above the chip functional structure, and the ring pad 121 is connected to a top metal layer of the chip functional structure; the chip functional structure and the top of the ring pad 121 are covered with a passivation layer 13.
it should be noted that, in order to facilitate highlighting the invention point of the present invention, only a partial structure of the chip stress testing structure 1 is taken as an example in fig. 2, and the whole structure of the chip stress testing structure 1 is not fully shown.
As an example, as shown in fig. 2, the chip functional structure includes a plurality of metal layers 111 stacked in sequence, each metal layer 111 is separated by an interlayer dielectric layer 112, and adjacent metal layers 111 are connected by a metal plug 124. A passivation protection layer 13 is arranged on the top of the chip functional structure, the passivation protection layer 13 includes a first passivation protection layer 131 and a second passivation protection layer 132, the first passivation protection layer 131 is located on the upper surface of the metal layer 111 on the top layer, and the second passivation protection layer 132 is located on the upper surface of the first passivation protection layer 131; the surface of the first passivation layer 131 is further provided with a rewiring layer 113, and the second passivation layer 132 is located at the periphery of the rewiring layer 113.
as an example, as shown in fig. 2, the annular pad 121 penetrates through the first passivation layer 131 and partially extends to the surface of the second passivation layer 132, and the width of the annular pad 121 on the surface of the second passivation layer 132 is greater than the width of the annular pad 121 in the first passivation layer 131.
referring to step S2 in fig. 1 and fig. 3, a first opening 14 is formed in the passivation layer 13, and the first opening 14 exposes the ring pad 121.
as an example, a first opening 14 is formed in the passivation protection layer at a position corresponding to the ring pad 121 using a photolithography and etching process.
As an example, the width of the first opening 14 is smaller than the maximum width of the ring pad 121.
It should be noted that, in order to facilitate highlighting the invention point of the present invention, only a partial structure of the chip stress testing structure 1 is taken as an example in fig. 3, and the entire structure of the chip stress testing structure 1 is not fully shown.
Please refer to step S3 in fig. 1 and fig. 4 and 5, wherein fig. 4 is a schematic cross-sectional structure diagram of a partial structure of the chip stress test structure 1, and fig. 5 is a top view of fig. 4, the ring pad 121 is removed to form a second opening 15 below the first opening 14, and the second opening 15 exposes the top metal layer of the chip functional structure.
As an example, the chip stress test structure 1 obtained in step 2) is placed in an acid solution to remove the ring-shaped pad 121, and a second opening 15 is formed below the first opening 14.
as an example, the annular pad 121 may be, but is not limited to, an aluminum pad, and the acid solution may be, but is not limited to, one or more of a hydrochloric acid solution, a sulfuric acid solution, or a nitric acid solution.
as an example, the second opening 15 is obtained by removing the ring pad 121, and the shape of the second opening 15 is the same as that of the ring pad 121, so as to ensure that the second opening 15 exposes the top metal layer of the chip functional structure, and ensure that the maximum width of the second opening 15 is greater than the width of the first opening 14. The maximum width of the second opening 15 is greater than the width of the first opening 14, so that when a solder layer is formed subsequently, the solder layer can be embedded into the passivation protection layer 13, so as to enhance the adhesion between the chip stress test structure 1 and a first substrate arranged subsequently.
Referring to step S4 in fig. 1 and fig. 6, a first substrate 3 is provided, and the first substrate 3 is fixed to the bottom of the chip stress test structure 1 obtained in step 3).
As an example, the first substrate 3 is fixed to the bottom of the chip stress testing structure 1 obtained in step 3) through an adhesive layer 5. The adhesive layer 5 may be a material layer used for adhesion in the prior art, such as an adhesive layer, and is not limited herein.
Referring to step S5 in fig. 1 and fig. 7, a solder layer 2 is disposed on the top surface of the chip stress test structure 1 obtained in step 4).
By way of example, the solder layer 2 may be, but is not limited to, a tin layer.
Referring to step S6 in fig. 1 and fig. 8, a second substrate 4 is provided, and the second substrate 4 is fixed on the top of the chip stress test structure 1 through the solder layer 2.
As an example, the step of fixing the second substrate 4 on the top of the chip stress testing structure 1 through the solder layer 2 comprises the following steps:
61) Placing the second substrate 4 on the surface of the solder layer 2;
62) And putting the structure obtained in the step 61) in a high-temperature furnace for reflow process treatment, so that the second substrate 4 is fixed on the top of the chip stress test structure 1 through the solder layer 2. During the reflow process, the solder layer 2 will melt, and except for most of the solder layer 2 still located on the top surface of the chip stress test structure 1 obtained in step 4), another part of the solder layer 2 will reflow into the first opening 14 and the second opening 15, and even fill the first opening 14 and the second opening 15.
As an example, the temperature of the reflow process in step 62) may be, but is not limited to, 150 ℃ to 300 ℃.
In the preparation method of the embodiment, the chip stress test structure 1 is fixed on the surface of the second substrate 4 through the solder layer 2, and the solder layer 2 is positioned on the surface of the chip stress test structure 1 and in the opening, so that the adhesion between the chip stress test structure 1 and the second substrate 4 is enhanced, compared with a chip stress test assembly in the prior art, the influence of an adhesive layer on a chip stress test result is avoided, and the reliability of the test result is improved; meanwhile, the chip stress testing assembly is simple in preparation process and high in preparation success rate.
example two
With continuing reference to fig. 4, 5, 6 and 8, the present invention further provides a chip stress testing assembly, which at least includes: the chip stress testing structure 1 comprises a chip functional structure and a passivation protective layer 13 positioned above the chip functional structure, wherein an opening structure is formed in the passivation protective layer 13, and the opening structure exposes a top metal layer of the chip functional structure; the opening structure here includes the first opening 14 and the second opening 15 in fig. 4; the solder layer 2 is positioned on the surface of the chip stress test structure 1 and in the opening structure; the first substrate 3 is fixed at the bottom of the chip stress test structure 1; and the second substrate 4 is fixed on the top of the chip stress test structure 1 through the solder layer 2.
As an example, the opening structure is an annular opening structure.
By way of example, the number of opening structures is two or more.
As an example, the opening structure includes a second opening 15 located above a top metal layer of the chip functional structure and a first opening 14 located above the second opening 15, and a width of the first opening 14 is smaller than a maximum width of the second opening 15.
In summary, the present invention provides a chip stress testing assembly and a method for manufacturing the same, wherein the method for manufacturing the chip stress testing assembly at least comprises the following steps: 1) providing a chip stress test structure, wherein the chip stress test structure comprises a chip functional structure and an annular welding pad positioned above the chip functional structure, and the annular welding pad is connected with a top metal layer of the chip functional structure; the chip functional structure and the top of the annular welding pad are covered with passivation protective layers; 2) forming a first opening in the passivation protection layer, wherein the annular welding pad is exposed out of the first opening; 3) removing the annular welding pad to form a second opening below the first opening, wherein the second opening exposes the top metal layer of the chip functional structure; 4) providing a first substrate, and fixing the first substrate at the bottom of the chip stress test structure obtained in the step 3); 5) placing a solder layer on the top surface of the chip stress test structure obtained in the step 4); 6) and providing a second substrate, and fixing the second substrate on the top of the chip stress test structure through the solder layer. According to the chip stress testing assembly, the opening structure of the top metal layer exposing the chip functional structure is arranged in the chip stress testing structure, the chip stress testing structure is fixed on the surface of the second substrate through the solder layer, and the solder layer is positioned on the surface of the chip stress testing structure and in the opening structure, so that the adhesion force between the chip stress testing structure and the second substrate is enhanced, compared with a chip stress testing assembly in the prior art, the influence of an adhesive layer on a chip stress testing result is avoided, and the reliability of the testing result is improved; meanwhile, the chip stress testing assembly is simple in preparation process and high in preparation success rate.
the foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. The preparation method of the chip stress testing assembly is characterized by at least comprising the following steps of:
1) Providing a chip stress test structure, wherein the chip stress test structure comprises a chip functional structure and an annular welding pad positioned above the chip functional structure, and the annular welding pad is connected with a top metal layer of the chip functional structure; the chip functional structure and the top of the annular welding pad are covered with passivation protective layers;
2) Forming a first opening in the passivation protection layer, wherein the annular welding pad is exposed out of the first opening;
3) Removing the annular welding pad to form a second opening below the first opening, wherein the second opening exposes the top metal layer of the chip functional structure;
4) Providing a first substrate, and fixing the first substrate at the bottom of the chip stress test structure obtained in the step 3);
5) placing a solder layer on the top surface of the chip stress test structure obtained in the step 4);
6) And providing a second substrate, and fixing the second substrate on the top of the chip stress test structure through the solder layer.
2. The method of manufacturing a chip stress-testing assembly of claim 1, wherein: and 2), forming a first opening in the passivation protective layer by adopting photoetching and etching processes.
3. The method of manufacturing a chip stress-testing assembly of claim 1, wherein: the width of the first opening is smaller than the maximum width of the annular welding pad.
4. the method of manufacturing a chip stress-testing assembly of claim 1, wherein: in the step 3), the chip stress test structure obtained in the step 2) is placed in an acid solution to remove the annular welding pad, and a second opening is formed below the first opening.
5. The method of manufacturing a chip stress-testing assembly of claim 1, wherein: in the step 4), the first substrate is fixed at the bottom of the chip stress test structure obtained in the step 3) through an adhesive layer.
6. the method of manufacturing a chip stress-testing assembly of claim 1, wherein: in step 6), fixing the second substrate to the top of the chip stress test structure through the solder layer includes the following steps:
61) Placing the second substrate on the surface of the solder layer;
62) And putting the structure obtained in the step 61) in a high-temperature furnace for reflow process treatment, so that the second substrate is fixed on the top of the chip stress test structure through the solder layer.
7. The method for preparing a chip stress test assembly according to claim 6, wherein the temperature of the reflow process in step 62) is 150 ℃ ~ 300 ℃.
8. a chip stress testing assembly, comprising at least:
The chip stress testing structure comprises a chip functional structure and a passivation protective layer positioned above the chip functional structure, wherein an opening structure is formed in the passivation protective layer, and the opening structure exposes a top metal layer of the chip functional structure; the opening structure comprises a second opening positioned above the top metal layer of the chip functional structure and a first opening positioned above the second opening, and the width of the first opening is smaller than the maximum width of the second opening;
The solder layer is positioned on the surface of the chip stress test structure and in the opening structure;
the first substrate is fixed at the bottom of the chip stress test structure;
And the second substrate is fixed at the top of the chip stress test structure through the solder layer.
9. the chip stress-testing assembly of claim 8, wherein: the opening structure is an annular opening structure.
10. The chip stress-testing assembly of claim 9, wherein: the number of the opening structures is more than two.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710186774.1A CN108666298B (en) | 2017-03-27 | 2017-03-27 | Chip stress testing assembly and preparation method thereof |
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| CN201710186774.1A CN108666298B (en) | 2017-03-27 | 2017-03-27 | Chip stress testing assembly and preparation method thereof |
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| CN108666298A CN108666298A (en) | 2018-10-16 |
| CN108666298B true CN108666298B (en) | 2019-12-10 |
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| CN112526315B (en) * | 2020-11-05 | 2021-11-12 | 长江存储科技有限责任公司 | Test method of packaged chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200423273A (en) * | 2003-04-17 | 2004-11-01 | Advanced Semiconductor Eng | Fixture for die-pull test |
| CN101106114A (en) * | 2006-07-11 | 2008-01-16 | 日月光半导体制造股份有限公司 | Chip structure and its forming method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150057389A (en) * | 2013-11-19 | 2015-05-28 | 삼성전기주식회사 | Printed Circuit Board and Method for Manufacturing The same |
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2017
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200423273A (en) * | 2003-04-17 | 2004-11-01 | Advanced Semiconductor Eng | Fixture for die-pull test |
| CN101106114A (en) * | 2006-07-11 | 2008-01-16 | 日月光半导体制造股份有限公司 | Chip structure and its forming method |
Non-Patent Citations (1)
| Title |
|---|
| "Sample Preparation DOE for the Die Pull Test";Xiali Chen etc.;《2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits》;20150702;第181-184页 * |
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