CN101106114A - Chip structure and its forming method - Google Patents
Chip structure and its forming method Download PDFInfo
- Publication number
- CN101106114A CN101106114A CNA2006100902951A CN200610090295A CN101106114A CN 101106114 A CN101106114 A CN 101106114A CN A2006100902951 A CNA2006100902951 A CN A2006100902951A CN 200610090295 A CN200610090295 A CN 200610090295A CN 101106114 A CN101106114 A CN 101106114A
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- protective layer
- layer
- chip structure
- opening
- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13017—Shape in side view being non uniform along the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a chip structure and the fabricating method thereof. The chip structure comprises a basement, a pad, a first protecting layer, a second protecting layer and a conducting pump. The pad is formed on the basement. The first protecting layer is formed on the basement and the pad is exposed. The second protecting layer is formed on the first protecting layer, the second protecting layer has a protecting layer cut which is positioned above the pad. The conducting pump is formed on the pad, the part of the conducting pumps is filled into the protecting layer cut, wherein the width of the bottom of the protecting layer cut is larger than the width of the top of the protecting layer cut, which allows the second protecting layer to grab the conducting pump.
Description
Technical field
The present invention relates to a kind of chip structure and forming method thereof, particularly a kind of chip structure that can anti-stress and forming method thereof.
Background technology
Please respectively referring to figs. 1A to Fig. 1 G, Figure 1A to Fig. 1 G represents that tradition forms the schematic diagram of chip structure.Form chip structure and need pass through following flow process.At first shown in Figure 1A, in substrate 101, form first protective layer 103, and expose a weld pad 105.Then, on first protective layer 103, form one second protective layer 107, and utilize the mode of exposure imaging on 109, to form a protective layer opening.Then, shown in Fig. 1 C, (Under Bump Metallurgylayer UBM), and carries out the Butut technology of projection lower metal layer 111 to deposition projection lower metal layer 111 on first protective layer 103.Shown in Fig. 1 D, on projection lower metal layer 111, more form one first photoresist layer 113.Then, shown in Fig. 1 E, etching projection lower metal layer 111, and remove first photoresist layer 113.Please refer to Fig. 1 F again, on second protective layer 107, form one second photoresist layer 118, and in protective layer opening 109 filled conductive material 119 (for example tin cream).At last, shown in Fig. 1 G, reflow (Reflow) electric conducting material 119 is with formation conductive projection 123 and remove second photoresist layer 118, thereby forms chip structure 100.
After finishing chip structure 100, must carry out the test (Reliability test) of reliability to chip structure 100.Test event for example, the variation of temperature, pressure and engineering properties, and must the cycle and testing repeatedly.Yet at present regular meeting appears in the chip structure 100 among the result of test, conductive projection 123 and projection lower metal layer 111, or usually have the phenomenon of disengaging between projection lower metal layer 111 and the weld pad 105.Investigating reason, is because due to the coefficient of expansion difference of conductive projection 123, projection lower metal layer 111 and weld pad 105 in fact.When three's coefficient of expansion not simultaneously, be easy to generate stress and separate conductive projection 123, projection lower metal layer 111 and weld pad 105.That is to say that in many traditional die structures 100,105 of conductive projection 123, projection lower metal layer 111 and weld pads, adhesion each other are not enough to keep out temperature in the reliability test, pressure and engineering properties and change the separation stresses that is produced.The reliability and the competitiveness of product have also therefore been reduced.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of chip structure that promotes anti-stress ability, to increase the reliability and the competitiveness of product.In addition, another problem that will solve of the present invention is that a kind of method of making this chip structure also will be provided.
For above-mentioned a kind of chip structure problem that promotes anti-stress ability that provides is provided, the technological means that the invention provides comprises a kind of chip structure, and this chip structure has a substrate, a weld pad, one first protective layer, one second protective layer and a conductive projection.Weld pad is formed in the substrate.First protective layer is formed in the substrate and exposes weld pad.Second protective layer is formed on first protective layer, and second protective layer has a protective layer opening, and the protective layer opening is positioned at the weld pad top.Conductive projection is formed on the weld pad, and partially conductive projection system is filled in the protective layer opening.Wherein, the width of protective layer open bottom makes second protective layer vise conductive projection greater than the width of protective layer open top.
For solving said chip structure making process problem, the technological means that the invention provides comprises a kind of chip structure manufacture method, and this chip structure manufacture method comprises: at first, provide a substrate.Then, in substrate, form one first protective layer and a weld pad, and weld pad exposes to first protective layer.Then, form one second protective layer on first protective layer, and second protective layer has a protective layer opening to expose weld pad, the width of protective layer open bottom is greater than the width of protective layer open top.At last, form a conductive projection, the partially conductive projection is configured in the protective layer opening, and conductive projection and weld pad electrically connect.
Chip structure provided by the present invention and manufacture method thereof are to utilize the bottom width of protective layer opening greater than top width, thereby can assist second protective layer to clamp conductive projection, prevent from that conductive projection from coming off to leave weld pad and projection lower metal layer.Therefore can increase the reliability of chip structure and the anti-stress value of lifting chip structure.
Description of drawings
Figure 1A to Fig. 1 G forms the schematic diagram of chip structure for the expression tradition;
Fig. 2 A to Fig. 2 H represents to form the chip structure schematic flow sheet respectively;
Fig. 3 forms the undercutting schematic diagram for expression second protective layer;
The 4th figure illustrates the flow chart that forms chip structure.
Wherein, description of reference numerals is as follows:
100 chip structures, 200 chip structures
101 substrates, 201 substrates
103 first protective layers, 203 first protective layers
105 weld pads, 205 weld pads
107 second protective layers, 207 second protective layers
109 protective layer openings, 209 second protective layers
111 projection lower metal layers, 211 projection lower metal layers
113 first photoresist layers, 213 first photoresist layers
118 second photoresist layers, 218 second photoresist layers
119 electric conducting materials, 244 electric conducting materials
123 conductive projections, 223 conductive projections
237 focuses, 239 light shields
240 photoresist layer openings
Embodiment
Please refer to Fig. 2 A to Fig. 2 H and Fig. 4, Fig. 2 A to Fig. 2 F represents to form the schematic flow sheet of chip structure respectively, and Fig. 4 represents to form the flow chart of chip structure.Shown in Fig. 2 A, at first be step 301, go up in substrate 201 (Wafer) and form first protective layer 203 (passivation layer), and expose weld pad 205 (Pad).The material of weld pad 205 is aluminium or copper normally, forms with external circuit thus to electrically connect.First protective layer 203 is used at the bottom of the protecting group 201 and planarized surface.Next step 303 shown in Fig. 2 B, further forms one second protective layer 207, and form a protective layer opening 209 on second protective layer 207 on first protective layer 203.The width b1 of protective layer opening 209 bottoms is greater than the width b2 at protective layer opening 209 tops, thereby forms a undercutting (Undercut).The material of second protective layer 207 for example is light-sensitive polyimide (photosensitive polyimide), can be used for reaching the effect that absorbs stress (Stress Buffer) and buffering stress.Step 305 deposits projection lower metal layer 211 (Under Bump Metallurgy layer, UBM layer) on second protective layer 207 and weld pad 205 shown in Fig. 2 C then.Because protective layer opening 209 has undercutting, therefore when deposition projection lower metal layer 211, the projection lower metal layer 211 on second protective layer 207 can not be connected to the projection lower metal layer 211 on the weld pad 205.Projection lower metal layer 211 is formed (adhesion coating, barrier layer and wetting layer do not show in the drawings) by an adhesion layer (adhesion layer), barrier layer (barrier layer) with a wetting layer usually.Adhesion layer can provide good tackness for weld pad 205 and first protective layer 203, and its material can be aluminium, titanium, chromium, tungsten titanium etc.Barrier layer is used for preventing that the conductive projection 223 (being illustrated in 2H figure) and the metal of weld pad 205 from spreading mutually, and its material can be nickel vanadium, nickel etc.Wetting layer provides good adhesiveness between projection lower metal layer 211 and conductive projection 223, its material can be copper, molybdenum, platinum.
Next be step 307, please refer to Fig. 2 D, on projection lower metal layer 211, form one first photoresist layer 213 and patterning first photoresist layer 213.Be step 309 then, please refer to Fig. 2 E projection lower metal layer 211 is partly carried out etching, and remove first photoresist layer 213.Then step 311 forms one second photoresist layer 218, and patterning second photoresist layer 218, makes second photoresist layer 218 have a photoresist layer opening 240.Step 313 then, filled conductive material 244 in photoresist layer opening 240, electric conducting material 244 for example are tin cream.And the mode of filling is preferably with mode of printing and is filled in the photoresist layer opening 240.At last, reflow electric conducting material 244 and removes second photoresist layer 218 forming a conductive projection 223 in the step 315, and becomes chip structure 200.
Shown in Fig. 2 H, in chip structure 200 since protective layer opening 209 bottom width b1 greater than top width b2, make the cross section of protective layer opening 209 roughly be ladder type.Therefore in chip structure 200, the bottom of conductive projection 223 is anchored in the protective layer opening 209.When chip structure 200 carried out reliability test, the protective layer opening 209 of trapezoidal shape can increase the ability (stress is produced by different temperature, pressures and engineering properties variation) of conductive projection 223 anti-stress.Below will illustrate how to form the protective layer opening 209 of trapezoidal shape.Generation type can see through following several, comprising: first kind is to adjust the mode of exposure machine focal length.Second kind is the mode that adopts overdevelop.
Please refer to Fig. 3, Fig. 3 is the schematic diagram that second protective layer forms undercutting.When forming each protective layer opening 209; by adjusting exposure machine; make light through light shield 239; light is injected second protective layer 207 during exposure; light focus 237 is positioned at the top of second protective layer 207; and form an acute angle theta in the bottom, and remove second protective layer 207 of part through developing again, make each protective layer opening 209 form the little trapezoidal shape in big tops, bottom.In addition; therefore the second way impinges upon second protective layer, 207 tops by light, and 207 light-absorbing energy of second protective layer are higher, the increase by developing time; the amount that second protective layer, 207 bottoms are removed is greater than the top, thereby can form undercutting (Undercut) shape.
The disclosed chip structure of the above embodiment of the present invention, the bottom width of protective layer opening can assist second protective layer to clamp conductive projection greater than top width, prevent from that conductive projection from coming off to leave weld pad and projection lower metal layer.Therefore, with reliability that increases chip structure and the anti-stress value that promotes chip structure.
The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.
Claims (10)
1. a chip structure is characterized in that, this chip comprises:
One substrate;
One weld pad is formed in this substrate;
One first protective layer is formed in this substrate and exposes this weld pad;
One second protective layer is formed on this first protective layer, and this second protective layer has a protective layer opening, and this protective layer opening is positioned at this weld pad top; And
One conductive projection is formed on this weld pad, and this conductive projection of part is filled in this protective layer opening;
Wherein the width of this protective layer open bottom makes this second protective layer vise this conductive projection greater than the width of this protective layer open top.
2. chip structure as claimed in claim 1 is characterized in that, this chip structure comprises that further (Under Bump Metallurgy layer UBM), is formed between this conductive projection and this weld pad projection lower metal layer.
3. chip structure as claimed in claim 2 is characterized in that, this projection lower metal layer more is formed between this conductive projection and this second protective layer.
4. a method that forms the described chip structure of claim 1 is characterized in that, this method may further comprise the steps:
One substrate is provided;
In this substrate, form one first protective layer and a weld pad, and this weld pad is for exposing to this first protective layer;
Form one second protective layer on this first protective layer, and this second protective layer has a protective layer opening to expose this weld pad, the width of this protective layer open bottom is greater than the width of this protective layer open top; And
Form a conductive projection, this conductive projection of part is configured in this protective layer opening, and this conductive projection and this weld pad electrically connect.
5. the method for formation chip structure as claimed in claim 4 is characterized in that, on this first protective layer, form after the step of this second protective layer and form the step of this conductive projection at this protective layer opening before more may further comprise the steps:
Deposition one projection lower metal layer on this second protective layer and this weld pad;
On this projection lower metal layer, form one first photoresist layer, and this first photoresist layer of patterning; And
This projection lower metal layer of part is carried out etching, and remove this first photoresist layer.
6. the method for formation chip structure as claimed in claim 5 is characterized in that, the step that forms this conductive projection comprises:
Form one second photoresist layer;
This second photoresist layer of patterning makes this second photoresist layer have a photoresist layer opening, and this photoresist layer opening is positioned at this protective layer opening top;
In this photoresist layer opening and this protective layer opening, fill an electric conducting material; And
This electric conducting material of reflow, and remove this second photoresist layer to form this conductive projection.
7. the method for formation chip structure as claimed in claim 4 is characterized in that, comprises in the step that forms this second protective layer:
This second protective layer of coating on this first protective layer, the material of this second protective layer is light-sensitive polyimide (photosensitive polyimide);
Use a light shield so that this second protective layer is exposed; And
This second protective layer is carried out overdevelop, to form this protective layer opening.
8. the method for formation chip structure as claimed in claim 4 is characterized in that, this second protective layer is being carried out more comprising in the step of exposing:
Adjust the exposure focal length of an exposure machine, the top that the feasible time line focus that exposes is positioned at this second protective layer forms acute angle.
9. the method for formation chip structure as claimed in claim 8 is characterized in that, further comprises in the step of this second protective layer of developing:
Control is developed time of this second protective layer, makes the top of the area of this second protective layer bottom institute liquid that is developed erosion greater than this second protective layer.
10. the method for formation chip structure as claimed in claim 9 is characterized in that, comprises in the step that forms this second protective layer:
This second protective layer of coating on this first protective layer, the material of this second protective layer is light-sensitive polyimide (photosensitive poiyimide);
Use a light shield so that this second protective layer is exposed, the time line focus that exposes is positioned at the top of this second protective layer; And
This second protective layer is developed to form this protective layer opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100902951A CN101106114A (en) | 2006-07-11 | 2006-07-11 | Chip structure and its forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100902951A CN101106114A (en) | 2006-07-11 | 2006-07-11 | Chip structure and its forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101106114A true CN101106114A (en) | 2008-01-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100902951A Pending CN101106114A (en) | 2006-07-11 | 2006-07-11 | Chip structure and its forming method |
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| CN (1) | CN101106114A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201351A (en) * | 2010-03-25 | 2011-09-28 | 新科金朋有限公司 | Semiconductor device and method for forming dual UBM structure for lead free bump connection |
| CN102244019A (en) * | 2010-05-12 | 2011-11-16 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN104465426A (en) * | 2014-12-25 | 2015-03-25 | 颀中科技（苏州）有限公司 | Protruding block manufacturing method and protruding block assembly |
| CN104952735A (en) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Chip packaging structure having metal post and formation method of chip packaging structure |
| CN108666298A (en) * | 2017-03-27 | 2018-10-16 | 中芯国际集成电路制造(北京)有限公司 | Die stress test suite and preparation method thereof |
| CN109166791A (en) * | 2018-07-23 | 2019-01-08 | 上海集成电路研发中心有限公司 | A kind of hybrid bonded structure of autoregistration and preparation method thereof |
-
2006
- 2006-07-11 CN CNA2006100902951A patent/CN101106114A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201351A (en) * | 2010-03-25 | 2011-09-28 | 新科金朋有限公司 | Semiconductor device and method for forming dual UBM structure for lead free bump connection |
| US9711438B2 (en) | 2010-03-25 | 2017-07-18 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming a dual UBM structure for lead free bump connections |
| CN102201351B (en) * | 2010-03-25 | 2016-09-14 | 新科金朋有限公司 | Semiconductor device and the method forming the double UBM structures connected for unleaded projection |
| US8993431B2 (en) | 2010-05-12 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating bump structure |
| US9257401B2 (en) | 2010-05-12 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating bump structure and bump structure |
| CN102244019A (en) * | 2010-05-12 | 2011-11-16 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN104952735A (en) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Chip packaging structure having metal post and formation method of chip packaging structure |
| CN104952735B (en) * | 2014-03-25 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Chip-packaging structure and forming method thereof with metal column |
| CN104465426A (en) * | 2014-12-25 | 2015-03-25 | 颀中科技（苏州）有限公司 | Protruding block manufacturing method and protruding block assembly |
| CN104465426B (en) * | 2014-12-25 | 2018-04-27 | 颀中科技（苏州）有限公司 | The production method of convex block |
| CN108666298A (en) * | 2017-03-27 | 2018-10-16 | 中芯国际集成电路制造(北京)有限公司 | Die stress test suite and preparation method thereof |
| CN108666298B (en) * | 2017-03-27 | 2019-12-10 | 中芯国际集成电路制造(北京)有限公司 | Chip stress testing assembly and preparation method thereof |
| CN109166791A (en) * | 2018-07-23 | 2019-01-08 | 上海集成电路研发中心有限公司 | A kind of hybrid bonded structure of autoregistration and preparation method thereof |
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