CN100555593C - Form the method for soldering projection - Google Patents
Form the method for soldering projection Download PDFInfo
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- CN100555593C CN100555593C CNB2006101085549A CN200610108554A CN100555593C CN 100555593 C CN100555593 C CN 100555593C CN B2006101085549 A CNB2006101085549 A CN B2006101085549A CN 200610108554 A CN200610108554 A CN 200610108554A CN 100555593 C CN100555593 C CN 100555593C
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- metal layer
- lower metal
- projection
- layer
- projection lower
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a kind of method that forms soldering projection.At first, provide a substrate, and this substrate surface is formed with a projection lower metal layer.Then form a patterning photoresist layer on this projection lower metal layer surface, and this patterning photoresist layer includes at least two openings, in order to this projection lower metal layer of expose portion, these at least two open bottom form the different undercutting hole of big or small degree.This projection lower metal layer surface of part in these at least two openings forms a prime coat respectively afterwards, and this prime coat fills up this undercutting hole, and inserts scolder in these at least two openings.Carry out the photoresist strip step then, to remove this patterning photoresist layer, and carry out etching manufacture method step, and utilize this scolder to be used as shielding with this prime coat of etching part and this projection lower metal layer of part, then carry out the reflow manufacture method to form this soldering projection.
Description
[technical field]
The invention relates to a kind of method of wafer welding, particularly a kind of method that forms soldering projection.
[background technology]
Chip bonding (flip-chip) technology is the electronic packaging technology of widely utilizing at present.What be different from the conventional package technology is, in the chip bonding technology, crystal grain (die) no longer is that weld pad is electrically connected on the base plate for packaging via the mode of beating gold thread (wirebonding), but its inverted soldering projection that sees through is electrically connected and adorning (mount) to base plate for packaging.Because the chip bonding technology does not need the connection of gold thread, so can significantly dwindle the size of packaging body and increase the speed that circuit transmits between crystal grain and base plate for packaging.
Please refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is the existing method schematic diagram that forms soldering projection 10.As shown in Figure 1, at first provide a substrate 12, for example: finished the wafer that intraware and circuit are provided with.Include a patterned protective layer 14 (passivation layer) on the surface of substrate 12, and protective layer 14 exposes several weld pads 16.Wherein weld pad 16 can be made of copper or aluminium, is used for electrically connecting the internal wiring (not shown) that is formed in the substrate 12 and the outside line (not shown) on the base plate for packaging.
As shown in Figure 2, then utilize manufacture methods such as sputter, deposition and etching to form the projection lower metal layer 18 (under bump metallurgy layer) that several layers piles up, and be covered in each weld pad 16 and protective layer 14.Wherein projection lower metal layer 18 can be made of aluminium/nickel vanadium/copper or titanium/nickel vanadium/copper in regular turn.As shown in Figure 3, form a photoresist layer 20 on whole substrate 12 surfaces then, be covered in protective layer 14 and projection lower metal layer 18 tops.Wherein the material of photoresist layer 20 can be dry film photoresist or liquid photoresist.
Then as shown in Figure 4, expose with the development manufacture method with photoresist layer 20 patterning, to form several openings 22, expose the projection lower metal layer 18 of each weld pad 16 top accordingly at photoresist layer 20.As shown in Figure 5, utilize the mode of electroplating that scolder 24 is filled out then and be distributed in each opening 22, wherein scolder 24 can be materials such as tin or copper.Then divest photoresist layer 20.As shown in Figure 6, carry out reflow (reflow) manufacture method at last,, finish the existing method that forms soldering projection 10 above each corresponding weld pad 16, to form several soldering projections 10.
Yet in the prior art, when in photoresist layer 20, forming several openings 22, be subjected to the exposure light of projection lower metal layer 18 reflections and the influence of factors such as employed developer solution of development manufacture method and chemical solvent, photoresist layer 20 bottom of the part that is connected with projection lower metal layer 18 in will each opening 22 of inevasible erosion, cause undercut phenomenon, form the different undercutting hole of big or small degree 26, and then cause follow-uply inserting scolder 24 in the opening 22 except covering is exposed to projection lower metal layer 18 in the opening 22, also fill up the undercutting hole 26 of photoresist layer 20 bottom that are etched simultaneously.Therefore when follow-up when carrying out the reflow manufacture method, insert the cause of the scolder 24 that the scolder 24 of opening 22 will be inserted because of undercutting hole 26, and the floor space that causes soldering projection 10 is predetermined bigger than original, and not of uniform size, and then influences the yield and stability of whole manufacture method.Therefore, how can effectively control the size of soldering projection when the reflow manufacture method and be one of current important problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of method that forms soldering projection, solves above-mentioned the problems of the prior art.
According to aforementioned purpose of the present invention, the invention provides a kind of method that forms soldering projection, this method includes the following step.At first, provide a substrate, and this substrate surface is formed with at least one weld pad, a patterning protective layer and a projection lower metal layer (UBM layer) that covers this substrate surface and this weld pad of expose portion in regular turn.Then form a patterning photoresist layer on this projection lower metal layer surface, and this patterning photoresist layer includes at least two openings, be used for this projection lower metal layer of expose portion, the different undercutting hole of big or small degree is formed on the bottom of these at least two openings.This projection lower metal layer surface of part in these at least two openings forms a prime coat (footplating) respectively filling up this undercutting hole afterwards, and inserts scolder respectively in these at least two openings.Carry out the photoresist strip step then, to remove this patterning photoresist layer, and carry out etching manufacture method step, utilize this scolder to be used as shielding, then carry out reflow (reflow) manufacture method to form this soldering projection with this prime coat of etching part and this projection lower metal layer of part.
Because the present invention utilizes patterning photoresist layer to form at least two openings and expose this projection lower metal layer of part on projection lower metal layer surface earlier, in these two openings, form projection lower metal layer that prime coat and cover part expose subsequently at least and fill up undercutting hole, in these two openings, insert scolder more at least and remove not part prime coat and part projection lower metal layer by scolder covered, therefore can effectively strengthen and insert interior scolder of opening and the structure between the projection lower metal layer, with in follow-up size of carrying out the reflow manufacture method time control projection that forms soldering projection, and then promote the yield and stability of manufacture method.
[description of drawings]
Fig. 1 to Fig. 6 is the existing method schematic diagram that forms soldering projection.
Fig. 7 to Figure 12 is the method schematic diagram that forms soldering projection in the embodiment of the present invention.
[embodiment]
Please refer to Fig. 7 to Figure 12, Fig. 7 to Figure 12 forms the method schematic diagram of soldering projection for most preferred embodiment of the present invention.As shown in Figure 7, a substrate 30 at first is provided, wafer for example, and substrate 30 surfaces are formed with several conductor structures, for example weld pad 32, its material is generally copper or aluminium, is used for electrically connecting the internal wiring (not shown) that is formed in the substrate 30 and the outside line (not shown) on the base plate for packaging.Then form the part surface that a patterning protective layer 34 is covered in substrate 30 surfaces and exposes each weld pad 32 respectively, be used for protecting the internal wiring (not shown) in the wafer.Then carry out manufacture methods such as sputter manufacture method (sputtering), deposition and etching; with the projection lower metal layer 36 (underbump metallurgy layer be called for short UBM layer) of covering of forming that several layers the piles up weld pad 32 that part exposes with patterning protective layer 34 surfaces.Wherein, projection lower metal layer 36 is formed (specifically not illustrating) by an adhesion layer (adhesion layer), a barrier layer (barrier layer) and a wetting layer usually.Adhesion layer can provide weld pad 32 and patterning protective layer 34 good tackness, and its material can be aluminium, titanium, chromium, tungsten titanium etc.Barrier layer spreads mutually in order to the metal that prevents soldered ball and weld pad, and its material can be nickel vanadium, nickel etc.And wetting layer provides attaching property good between projection lower metal layer 36 and the soldered ball, and its material can be copper, molybdenum, platinum etc.
As shown in Figure 8, form patterning shielding, for example a photoresist layer 38 on projection lower metal layer 36 surfaces subsequently.Generally speaking, photoresist layer 38 can be selected liquid photoresist or dry film photoresist for use.Then carry out the exposure imaging manufacture method,, form at least two openings 40 of follow-up soldering projection simultaneously to expose the projection lower metal layer 36 of each weld pad 32 top accordingly.In other words, these at least two openings 40 are the land of follow-up scolder of inserting and projection lower metal layer 36, and its thickness is and follow-up height correlation with the soldering projection that forms.In addition, in the present embodiment, at least two openings 40 be positioned at weld pad 32 directly over.Yet, in other embodiments, at least two openings 40 also can be formed on the projection lower metal layer 36 of contiguous weld pad 32, to cooperate the position that needs the change contact in RDL (Redistribution Layer the is called for short RDL) manufacture method because of the needs in the joint configuration design.
Then part projection lower metal layer 36 surfaces at least two openings 40 form a prime coat 42 (foot plating), for example a copper metal layer respectively.As shown in Figure 9, prime coat 42 is to be formed at least two openings 40 bottoms of photoresist layer 38 and to cover the projection lower metal layer 36 that is exposed at least two openings 40.Then after inserting prime coat 42, electroplate manufacture method at least two openings 40, inserting scolder 44 respectively, and cover prime coat 42 fully.
Because when in photoresist layer 38, forming at least two openings 40, be subjected to the exposure light of projection lower metal layer 36 reflections and the influence of factors such as employed developer solution of development manufacture method and chemical solvent, photoresist layer 38 bottom of the part that is connected with projection lower metal layer 36 in will each opening 40 of inevasible erosion, cause undercut phenomenon, form the different undercutting hole of big or small degree 45.Therefore the present invention inserts prime coat 42 at least two openings 40 bottoms earlier, be used for filling up the undercutting hole 45 of photoresist layer 38 bottom that are etched, electroplate manufacture method then and at least two openings 40, insert scolder 44, and cover prime coat 42 fully.The Control Parameter of etching selectivities such as the last material of utilizing prime coat 42 and scolder 44 again, thickness, lattice structure; remove the part prime coat 42 and part projection lower metal layer 36 that are not covered by scolder 44; until patterning protective layer 34 surfaces, and then effectively control the size of soldering projection that follow-up reflow forms.
As shown in figure 10, then carry out the photoresist strip step, to remove photoresist layer 38.As shown in figure 11, carry out etching manufacture method step subsequently, utilize scolder 44 to be used as shielding with etching part prime coat 42 and part projection lower metal layer 36, until patterning protective layer 34 surfaces.At last as shown in figure 12, again scolder 44 is carried out reflow (reflow) manufacture method, make scolder 44, on pairing weld pad 32 and projection lower metal layer 36, to form a soldering projection 46 because of the surface tension englobement.
Compared with prior art, the present invention form the welding projection method be to utilize earlier a patterning photic Resist layer metal level surface under projection forms opening and exposes metal level under this projection of part, subsequently Metal level and undercutting hole under the projection that prime coat of formation and cover part expose in this opening, again In this opening, insert scolder and remove not by metal under part prime coat that scolder covered and the part projection Layer, therefore can be in follow-up size of carrying out effectively controlling when the reflow manufacture method is welded projection to form projection And the yield of lifting manufacture method and stability.
Claims (9)
1. method that forms soldering projection, this method includes following steps: provide a substrate, and this substrate surface is formed with the step of a projection lower metal layer; Form a patterning photoresist layer on this projection lower metal layer surface, and this patterning photoresist layer includes at least two openings, in order to this projection lower metal layer of expose portion, the step of the different undercutting hole of big or small degree is formed on the bottom of these at least two openings; In these two openings, insert the step of scolder at least; Carry out photoresist and peel off, to remove the step of this patterning photoresist layer; Carry out etching manufacture method step, utilize this scolder to be used as the step of shielding with this projection lower metal layer of etching part; And carry out the reflow manufacture method to form the step of this soldering projection: it is characterized in that: it also is included in inserts that the part projection lower metal layer surface in these at least two openings forms a prime coat respectively to fill up the step of this undercutting hole before the scolder at least in these two openings, also comprise utilizing this scolder to be used as this prime coat of shielding etching part in carrying out etching manufacture method step.
2. the method for claim 1, it is characterized in that: aforementioned substrates is a wafer.
3. the method for claim 1; it is characterized in that: between the step that substrate surface forms a projection lower metal layer also is included in this substrate and this projection lower metal layer, be provided with at least one weld pad in addition and be electrically connected the circuit of being located in this substrate; aforementioned opening is positioned at this weld pad top, and patterning protective layer is covered in the step of this substrate surface and this weld pad of expose portion.
4. the method for claim 1, it is characterized in that: this prime coat is a copper metal layer.
5. the method for claim 1, it is characterized in that: this projection lower metal layer includes an adhesion layer, a barrier layer and a wettable layer.
6. the method for claim 1, it is characterized in that: this projection lower metal layer is to utilize the sputter manufacture method to form.
7. the method for claim 1, it is characterized in that: this inserts the scolder step is to utilize a plating mode to reach.
8. bump manufacturing method, this bump manufacturing method includes: provide a wafer as substrate, and this substrate surface is formed with the projection lower metal layer, this projection lower metal layer includes an adhesion layer, a barrier layer and a wettable layer, include at least one weld pad in addition between this substrate and this projection lower metal layer and be electrically connected the circuit of being located in this substrate, and a patterning protective layer is covered in this substrate surface and this weld pad of expose portion; Form a patterning shielding on this projection lower metal layer surface, this patterning shield pack contains at least two openings above aforementioned weld pad, is used for this projection lower metal layer of expose portion, and the different undercutting hole of big or small degree is formed on the bottom of these at least two openings; Part projection lower metal layer surface in these at least two openings forms a prime coat respectively, and this prime coat fills up this undercutting hole; And in these two openings, form a projection at least respectively.
9. bump manufacturing method as claimed in claim 8, it is characterized in that: this patterning shielding is a patterning photoresist layer, form this projection in this opening after, other includes a photoresist strip step, in order to remove this patterning photoresist layer; After removing this patterning photoresist layer, other includes an etching manufacture method step, utilizes this projection to be used as shielding with this prime coat of etching part and this projection lower metal layer of part; After etching manufacture method step, other comprises a reflow manufacture method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101085549A CN100555593C (en) | 2006-07-21 | 2006-07-21 | Form the method for soldering projection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101085549A CN100555593C (en) | 2006-07-21 | 2006-07-21 | Form the method for soldering projection |
Publications (2)
| Publication Number | Publication Date |
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| CN101110377A CN101110377A (en) | 2008-01-23 |
| CN100555593C true CN100555593C (en) | 2009-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101085549A Active CN100555593C (en) | 2006-07-21 | 2006-07-21 | Form the method for soldering projection |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645413B (en) * | 2008-08-04 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal connecting wire |
| CN102222653A (en) * | 2010-04-15 | 2011-10-19 | 财团法人工业技术研究院 | Dimpling block structure |
| US20120098124A1 (en) * | 2010-10-21 | 2012-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having under-bump metallization (ubm) structure and method of forming the same |
| CN104124205B (en) * | 2014-07-18 | 2018-03-16 | 华进半导体封装先导技术研发中心有限公司 | A kind of preparation method of RDL wiring layers |
| CN110544629A (en) * | 2019-09-24 | 2019-12-06 | 北京北方华创微电子装备有限公司 | Oxide layer removing method and semiconductor processing equipment |
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- 2006-07-21 CN CNB2006101085549A patent/CN100555593C/en active Active
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| CN101110377A (en) | 2008-01-23 |
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