TW201347056A - Method for fabricating a bonding pad structure - Google Patents

Abstract

A method for fabricating a bonding pad structure, including: providing a semiconductor structure with a conductive layer and a patterned dielectric layer having a first opening therein; performing a first deposition process to form a layer of first protective material over the dielectric layer and the conductive layer; performing a first patterning process to pattern the layer of first protective material, forming a first passivation layer with a second opening therein; performing a second deposition process to form a second layer of protective material over the first passivation layer, the dielectric layer, and the conductive layer and performing a second patterning process to forming a second passivation layer having a third opening, wherein the second passivation and the first passivation layer form a composite passivation layer.

Description

Method for manufacturing pad structure

The present invention relates to the fabrication of semiconductor devices, and more particularly to a method of fabricating a pad structure for use in a semiconductor device.

In general, the fabrication of a semiconductor device is performed by sequentially depositing and patterning a plurality of layers of insulating, conducting, and semiconductor material on a wafer.

Generally, one of the plurality of material film layers formed at the uppermost portion includes a pad layer for electrically connecting a lower active region and a component in the wafer, and the pad layer is also appropriately protected by a protective layer. The pad layer is protected from damage during subsequent testing and packaging processes.

However, as the size of semiconductor devices shrinks, improvements in the pad structure are required to ensure that the protective layer within the semiconductor device provides adequate protection of the pad layer as the size of the semiconductor device is reduced.

According to an embodiment, the present invention provides a method of fabricating a pad structure, comprising: providing a semiconductor structure having a conductive layer formed thereon and a dielectric layer patterned with one of the first openings, the first opening Part of exposing a portion of the conductive layer; performing a first deposition process to form a first protective material on the dielectric layer and the conductive layer; performing a first patterning process to pattern the first protection of the layer a material to form a first protective layer having a second opening, wherein the second opening exposes the first opening, a portion of the dielectric layer adjacent to the first opening, and the conductive layer; performing a second deposition process Forming a second protective material on the first protective layer, the dielectric layer and the conductive layer; and performing a second patterning process to pattern the second protective material to form a third opening a second protective layer, wherein the third opening exposes the second opening, a portion of the first protective layer adjacent to the second opening, the first opening, and a portion of the dielectric layer adjacent to the first opening The second protection Constitute a composite protective layer and the first protective layer.

The above described objects, features and advantages of the present invention will become more apparent and understood.

Referring to Figures 1-3, there is shown a method of fabricating a pad structure suitable for use in a semiconductor device in accordance with an embodiment of the present invention. Here, the manufacturing method as shown in Figs. 1-3 is used as a comparative example to illustrate the reliability of the pad structure encountered by the inventors of the present invention, and is not intended to limit the scope of the present invention.

Referring to FIG. 1, a semiconductor device 100 is generally provided, which includes a semiconductor structure 102, a conductive layer 104, and a dielectric layer 106. As shown in FIG. 1, the conductive layer 104 and the dielectric layer 106 are sequentially formed on the semiconductor structure 102, and an opening 108 is formed in the dielectric layer 106. The opening 108 partially exposes the underlying conductive layer 104.

In one embodiment, the semiconductor structure 102 can include a semiconductor substrate, a plurality of dielectric layers, a plurality of active components, a plurality of passive components, and a plurality of conductive interconnect components, and the components are appropriately designed. And set up to form an integrated circuit. However, for the purpose of simplifying the drawing, the semiconductor structure 102 is not shown as a flat structure. In one embodiment, the conductive layer 104 is used as a pad layer, which may include a metal material such as copper, aluminum, or tungsten, and the dielectric layer 106 formed on the conductive layer 104 may include, for example, yttrium oxide. A dielectric material of tantalum nitride, or a combination thereof.

Referring to FIG. 2, a deposition process (not shown) is then performed to form a layer of protective material 110 on the semiconductor structure 102. Next, a patterning process 112 is performed to pattern the layer of protective material 110 to form a patterned protective layer 110a on the dielectric layer 106, as shown in FIG.

Referring to FIG. 3, the opening 114 formed in the patterned protective layer 110a is slightly larger than one opening of the opening 108. In addition to exposing the opening 108, the exposed dielectric layer 106 is partially exposed. The conductive layer 104 is exposed by the opening 108.

In an embodiment, the protective layer 110a and the protective material 110 may be made of a photosensitive polyimide material. Therefore, it can be formed by a deposition process such as one of a spin coating method, and the above-described patterning program 112 can employ a patterning process such as a lithography method. However, limited by the lithography process of the patterning process 112 performed on the protective layer 110a/protective material 110, the thickness T1 of the protective layer 110/protective material 110 on the dielectric layer 106 will be limited. It has a thickness of about no more than 100,000 angstroms after baking.

However, as the size of the semiconductor device 100 is reduced, the protective layer 110 having the thickness T1 described above may not be able to withstand the electrical connection such as wire bonding and probe test in subsequent testing and packaging processes. Damage caused by related processes such as the sex test process. As such, after the subsequent testing and packaging process is performed, the protective layer 110 may be partially or completely damaged, and the related protection of the conductive layer 104 of the semiconductor device 100 against undesired effects such as moisture and ion blocking may not be provided. This will further affect the electrical and reliability performance of the semiconductor device 100.

Referring to FIG. 4-5, respectively, one of the semiconductor devices 100 as shown in FIG. 3 is shown, and the semiconductor device 100 shown in FIG. 3 shows the line segment 3 along the 4th to 5th. 3 profile situation.

As shown in FIG. 4, the openings 108 and 114 in the semiconductor device 100 have a generally circular shape and are generally concentric. As shown in FIG. 5, the openings 108 and 114 in the semiconductor device 100 have a generally rectangular shape and are substantially concentric. However, the shapes of the openings 108 and 114 in the semiconductor device 100 are not limited to those shown in Figures 4-5, and may be other polygonal shapes, and the openings 108 and 114 may have the same or different shapes. .

In summary, as the size of the semiconductor device is reduced, it is necessary to improve the structure of the pad to provide a manufacturing method of a pad structure with better protection effect. In view of the above, please refer to FIGS. 6-9, which illustrate a method for fabricating a pad structure suitable for a semiconductor device according to another embodiment of the present invention, which is preferably manufactured in response to the trend of size reduction of the semiconductor device. Protective pad structure.

Referring to FIG. 6, a semiconductor device 200 is generally provided, which includes a semiconductor structure 202, a conductive layer 204, and a dielectric layer 206. As shown in FIG. 2, the conductive layer 204 and the dielectric layer 206 are sequentially formed on the semiconductor structure 202, and an opening 208 is formed in the dielectric layer 206, and the opening 208 partially exposes the underlying conductive layer 204.

In one embodiment, the semiconductor structure 202 can include a semiconductor substrate, a plurality of dielectric layers, a plurality of active components, a plurality of passive components, and a plurality of conductive interconnect components, and the components are appropriately designed. And set up to form an integrated circuit. However, for the purpose of simplifying the drawing, the semiconductor structure 202 is not shown as a flat structure. In one embodiment, the conductive layer 204 is used as a pad layer, which may include a metal material such as copper, aluminum, or tungsten, and the dielectric layer 206 formed on the conductive layer 204 may include, for example, yttrium oxide. A dielectric material of tantalum nitride, or a combination thereof.

Referring to FIG. 7, a deposition process (not shown) is then performed to form a layer of protective material 210 on the semiconductor structure 202. Next, a patterning process 212 is performed to pattern the layer of protective material 210 to form a patterned one of the protective layers 210a on the dielectric layer 206, as shown in FIG.

Referring to FIG. 8, the opening 214 formed in the patterned protective layer 210a is slightly larger than the opening of the opening 208. In addition to the opening 208, the exposed dielectric layer 206 is partially exposed. The conductive layer 204 is exposed by the opening 208.

Next, another deposition process (not shown) is performed to form a layer of protective material 216 on the semiconductor structure 202. Next, a patterning process 218 is performed to pattern the layer of protective material 216 to form a patterned other protective layer 216a on the protective layer 210a, as shown in FIG.

In one embodiment, the protective layers 210a and 216a and the protective materials 210 and 216 may each be made of a photosensitive polyimide material. Therefore, it can be formed by one deposition process such as a spin coating method, and the above-described patterning programs 212 and 218 can adopt a patterning process such as a lithography method.

The thickness T2 of the protective layer 210/protective material 210 on the dielectric layer 206 and the protective layer 210a are limited by the limitations of the lithography process for the patterning processes 212 and 218 performed on the protective materials 210 and 216, respectively. The T3 of the upper protective layer 216a/protective material 216 will be limited to have a post-baking thickness of no more than about 200,000 angstroms, respectively. However, compared to the case shown in FIG. 3, after integration, the protective layers 210a and 216a on the dielectric layer 206 may constitute a composite protective layer 250, the overall thickness of which is much larger than that in FIG. The protective layer 110a is shown, so that the composite protective layer 250 can resist electrical testing such as wire bonding and probe test in subsequent testing and packaging processes as the size of the semiconductor device 200 is reduced. Damage caused by related processes. As such, after the subsequent testing and packaging process is performed, the composite protective layer 250 may be partially damaged, but it can still provide reliable protection against the undesired effects of the conductive layer 204 of the semiconductor device 200 on moisture, ion blocking, and the like. In this case, the electrical and reliability performance of the semiconductor device 200 will be further ensured.

Referring to FIGS. 10-11, respectively, one of the semiconductor devices 200 as shown in FIG. 9 is shown, and the semiconductor device 200 shown in FIG. 9 is shown as a segment along the line 9-11. 9 profile situation.

As shown in FIG. 10, the openings 208, 214, and 220 in the semiconductor device 200 have a generally circular shape and are substantially concentric, and have a diameter D1, D2, and D3, respectively, wherein D3 is larger than D2. More than 10%. As shown in FIG. 11, the openings 208, 214 and 220 in the semiconductor device 200 have a substantially rectangular shape and are substantially concentric, and have a maximum length L1, L2 and L3, respectively, wherein L3 is larger than L2. More than 10%. However, the shapes of the openings 208, 214, and 220 in the semiconductor device 200 are not limited to those shown in FIGS. 10-11, and may be other polygonal shapes, and the openings 208, 214, and 220 may have the same or Different shapes. Furthermore, the composite protective layer 250 formed on the dielectric layer 206 is not limited to two layers as shown in FIGS. 9-11, and may be a composite protective layer composed of a protective layer including more than two layers. And the opening in the protective layer of each upper layer is slightly larger than about 10% of the opening in the protective layer below it.

Moreover, the composite protective layer 250 based on the present embodiment has an opening that is more expanded from the bottom to the top, and thus does not affect the above process in the subsequent bonding process such as wire bonding and electrical testing such as detection test. The process window is therefore suitable for the application case where the size of the semiconductor device 200 is reduced.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100, 200. . . Semiconductor device

102, 202. . . Semiconductor structure

104, 204. . . Conductive layer

106, 206. . . Dielectric layer

108, 208. . . Opening

110, 210. . . Protective material

110a, 210a. . . The protective layer

112, 212. . . Patterning program

114,214. . . Opening

216. . . Protective material

216a. . . The protective layer

218. . . Patterning program

220. . . Opening

250. . . Composite protective layer

T1, T2, T3. . . thickness

D1, D2, D3. . . diameter

L1, L2, L3. . . The maximum length

1 to 3 are views showing a method of manufacturing a pad structure applied to a semiconductor device in accordance with an embodiment of the present invention;

4 is a view showing a top view of a pad structure applied to a semiconductor device in accordance with an embodiment of the present invention;

Figure 5 is a view showing a top view of a pad structure applied to a semiconductor device in accordance with another embodiment of the present invention;

6-8 are views showing a manufacturing method of a pad structure applied to a semiconductor device according to another embodiment of the present invention;

Figure 9 is a view showing a top view of a pad structure applied to a semiconductor device in accordance with an embodiment of the present invention;

Figures 10-11 respectively show a top view of a pad structure applied to a semiconductor device in accordance with another embodiment of the present invention.

200. . . Semiconductor device

202. . . Semiconductor structure

204. . . Conductive layer

206. . . Dielectric layer

208. . . Opening

210a. . . The protective layer

214. . . Opening

216a. . . The protective layer

220. . . Opening

250. . . Composite protective layer

T2, T3. . . thickness

Claims (10)

A method of fabricating a pad structure includes: providing a semiconductor structure having a conductive layer formed thereon and a dielectric layer patterned with one of the first openings, the first opening portion exposing a portion of the conductive layer Performing a first deposition process to form a first protective material on the dielectric layer and the conductive layer; performing a first patterning process to pattern the first protective material to form a second opening a first protective layer, wherein the second opening exposes the first opening, a portion of the dielectric layer adjacent to the first opening, and the conductive layer; performing a second deposition process on the first protective layer, the Forming a second protective material on the dielectric layer and the conductive layer; and performing a second patterning process to pattern the second protective material to form a second protective layer having a third opening, wherein the The third opening exposes the second opening, a portion of the first protective layer adjacent to the second opening, the first opening and a portion of the dielectric layer adjacent to the first opening, and the second protective layer and the first The protective layer constitutes a complex The protective layer. The method of manufacturing a pad structure according to claim 1, wherein the first layer of protective material comprises a photosensitive polyamine. The method of manufacturing a pad structure according to claim 2, wherein the first deposition process is a spin coating process. The method of manufacturing a pad structure according to claim 2, wherein the first patterning process is a lithography process. The method of manufacturing a pad structure according to claim 1, wherein the second layer of protective material comprises a photosensitive polyamidoamine. The method of manufacturing a pad structure according to claim 5, wherein the second deposition process is a spin coating process. The method of manufacturing a pad structure according to claim 5, wherein the second patterning process is a lithography process. The method of manufacturing a pad structure according to claim 1, wherein the third opening is substantially concentric with the second opening and has a substantially circular top view shape, and one of the third openings has a diameter One of the second openings has a diameter greater than 10%. The method of manufacturing a pad structure according to claim 1, wherein the third opening is substantially concentric with the second opening and has a substantially rectangular top view shape, and a maximum length of one of the third openings is greater than The maximum length of one of the second openings is greater than 10%. The method of fabricating a pad structure according to claim 1, wherein the dielectric layer comprises tantalum nitride, hafnium oxide or a combination thereof, and the conductive layer comprises copper, aluminum, or tungsten.