TW463343B - Method for manufacturing passivation layer of bonding pad - Google Patents

Method for manufacturing passivation layer of bonding pad Download PDF

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Publication number
TW463343B
TW463343B TW089126794A TW89126794A TW463343B TW 463343 B TW463343 B TW 463343B TW 089126794 A TW089126794 A TW 089126794A TW 89126794 A TW89126794 A TW 89126794A TW 463343 B TW463343 B TW 463343B
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TW
Taiwan
Prior art keywords
layer
silicon oxide
pad
oxide layer
patent application
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TW089126794A
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Chinese (zh)
Inventor
Dian-Hau Chen
Lin-Jiun Wu
Guang-Ming Lin
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Taiwan Semiconductor Mfg
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Priority to TW089126794A priority Critical patent/TW463343B/en
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Publication of TW463343B publication Critical patent/TW463343B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A method for manufacturing the passivation layer of bonding pad comprises sequentially forming a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer on a substrate formed thereon bonding pads, and covering the bonding pads; then flattening the second silicon oxide layer until reaching the silicon nitride layer; next, forming an opening in the silicon nitride layer and the first silicon oxide layer for exposing the surface of the bonding pad.

Description

463343 A7 ________B7 五、發明説明（） 發明頜域 本發明是有關於一種半導體電路的製造方法，且特別 是有關於一種銲墊護層的製造方法。 發明背景 在半導體製程技術邁入涂次微米(Deep .Micron)領域之 際，因尺寸縮小而逐漸突顯出許多原本無須考量的問題。 其中’靜塾（Bonding Pad)與導線（Bonding Wire)之間的連 接口□質即對製成兀件之可靠度（Reliability)有相當大的影 響。 ’ 當元件尺寸越來越小’銲墊與導線連接的面積也逐漸 縮小，因此導致在打線銲接時銲墊需承受較大的應力 (stress)，且舞塾與導線之間的附著力(adherence)也降低。 經濟部智慧財產局員工消費合作社印製 ij 1 n- - I u « tn n m 1 -I I T (f先閲讀背面之注意事項再填寫本頁) 例如一般覆盖在靜塾周圍之護層(Passivation Layer)的 高度會較高’因此在打線時常會使得銲墊下之晶方（die)產 生裂痕。若使用聚亞醯胺（polyimide)或 BCB (henzosLyclohutene)聚合物來使銲墊周圍之護層較爲平坦 時，雖然可以解決上述問題，但是又會使封裝產品之可靠 度下降。 發明目的與槪沭 因此本發明的主要目的就是在提供一種銲墊護層的製 造方法，可使銲墊周圍之護層平坦化，並可提高後續錫$ 2 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 463343 A7 ______B7_ 五、發明説明（） 製程之可靠度= 此方法包括在已形成有銲墊之基底上，依序形成第一 氧化矽層、氮化矽層與第二氧化矽層於該基底上並覆蓋該 靜墊。然後平坦化第一氧化砂層，直至氮化砍層爲止。接 著於氮化矽層與第一氧化矽層中形成一個開口，以暴露出 銲墊之表面。 · 依照本發明一較佳實施例，其中上述之第一氧化矽層 之形成方法例如可爲高密度電漿化學氣相沈積法，氮化矽 層之形成方法例如可爲低壓化學氣相沈積法，第二氧化矽 層之形成方法例如可爲電漿增強式化學氣相沈積法。而第 一氧化矽層'氮化矽層與第二氧化矽層之厚度可分別爲 1K - 10K埃、1K - 10K埃與1K - 20K埃。另外第二氧化 矽層之平坦化方法例如可用化學機械硏磨法來進行之。 本發明利用第二氧化矽層做爲銲墊護層平坦化之用， 如此不僅可以解決在打線時晶方產生裂痕的問題，而且又 可以大幅提升封裝產品之可靠度。 圖式之簡單說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1A - 1D圖依照本發明一較佳實施例的一種銲墊護 __3_______ 本紙張尺度適用中國國家梂準（CNS ) A4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局8工消費合作社印製 463343 A7 B7 五、發明说明（ 層的製造方法流程剖面圖。 网忒之標記說明 100 :基底 110 :銲墊 120 、 120a ： 第一氧化砂層 130 ' 130a : 氮化矽層 140 、 140a ： 第二氧化矽層 150 :開口 160 :錫球下複金屬層 170 :錫球 (請先闖讀背面之注意事項再填寫本頁) 裝_ 經濟部智慧財產局員工消費合作社印製 發昍夕詳細說明 請參照第1A - 1D圖，其繪示依照本發明一較佳實施 例的一種銲墊護層的製造方法流程剖面圖。 請參照第1A圖，在基底100上形成銲墊110，其材 質例如可爲鋁銅合金。接著依序在基底100上形成第一氧 化矽層12〇、氮化矽層130與第二氧化矽層14〇，其厚度 例如可分別爲IK - 10K埃、IK - 10K埃與1K-20K埃。 而第一氧化矽層120、氮化矽層130與第二氧化矽層M〇 之形成方法例如可分別爲高密度電漿化學氣相沈積法 (High-Density Plasma Chemical Vapor Deposition ； HDP CVD)、低壓化學氣相沈積法(Low Pressure CVD)與電费汾 本紙張尺度通用中國國家揉隼（CNS}A4規格（210X297公釐） 4633 4 3 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 強式化學氣相沈積法(Plasma Enhance CVD)。 請參照第1B圖，接著以氮化矽層130爲平坦化終點， 對第二氧化矽層140進行平坦化步驟，使其成爲第二氧化 矽層140a，如此至少在銲墊110周圍之護層表面是平坦 的。其中上述之平坦化方法例如可使用化學機械硏磨法 (Chemical Mechanical Polishing ; CMP)，在此若使用 CMP 爲平坦化方法甚至可以達成晶圓（wafer)全面平坦化之效 果。 請參照第1C圖，接著進行微影蝕刻製程，在氮化矽 層130與第一氧化矽層120中形成開口 150，暴露出銲墊 Π0之表面。同時，氮化砂層130與第一氧化砂層120分 別轉變成氮化砂層130a與第一氧化砂層120a。 請參照第ID圖，接著在基底100上沈積錫球下複金 屬層（Under Bump Metallurgy ; UBM) 160，再瑕成錫球 (Solder Bump) Π0於開口 ISO之上。最後蝕刻未被錫球ι7〇 覆蓋之錫球下複金屬層160，完成錫球製程。 因爲習知是用聚亞醯胺或BCB聚合物來形成平坦的 護層覆蓋在銲墊之周圍，但是因爲聚亞醯胺或BCB聚合 物是有機材料，對後續之錫球下複金屬層之沈積與纟虫刻之 抗腐蝕力不夠，才使得封裝產品之可靠度下降。但是在本 發明中’以無機材質之氧化矽取代有機材質之聚亞醯胺或 BCB聚合物，因此使得護層表面之抗化學腐蝕力高了，對 後續之錫球下複金屬層之沈積與蝕刻之抗腐餓力也就跟著 私紙張尺度適用中國闺家棣準（CNS ) A4C格（210X297公釐） _n- HI I -I I —I. j· - I ^ -I - - - - ^^1« mi 1^1 (請先閲讀背面之注意事項再填寫本頁) 463343 A7 經濟部智慧財產局員工消費合作社印製 _______B7_ 五、發明説明（） 提升了。而且利用化學機械硏磨法來平坦化最上層之氧化 矽層’可達全面平坦化效果，使打線時晶方產生裂痕之可 能性降至最低。 發明人對護層表面沒有進行平坦化之封裝產品做晶方 剪應力測試(die shear test)，發現裂痕主要是自銲墊周圍之 氮化矽層延伸至銲墊下方之晶方。可能原因是因爲剪應力 會集中在銲墊周圍的護層表面突起之處，兼以氮化矽層較 脆(brittle)之故。若對護層表面有進行平坦化之封裝產品做 晶方剪應力測試，則在沈積錫球下複金屬層時就沒有階梯 高度差（step high)之問題，而且可以獲得較好之銲墊高度 (bump height)與高寬比（aspect ratio)，使錫球下複金屬層 之沈積較易。如此之結構可使錫球承受較高之應力，最後 斷裂面發生於錫球之截面，證明平坦化之護層，可使應力 分散，避免銲墊下方之晶方產生裂痕。 由上述本發明較佳實施例可知，應用本發明不僅可以 分散於打線時施於銲墊下方晶方之應力，並且可增加銲塾 護層之抗化學腐鈾力，使封裝產品之可靠度大幅提昇。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (諳先閱讀背面之注意事項再填寫本頁) -訂 6_ 本纸张尺度適用中國國家標準（CNS ) A4規格（2丨〇><297公釐）463343 A7 ________B7 V. Description of the invention () Inventive jaw field The present invention relates to a method for manufacturing a semiconductor circuit, and more particularly to a method for manufacturing a pad protection layer. BACKGROUND OF THE INVENTION As semiconductor process technology enters the field of deep .Micron, due to the reduction in size, many problems that have not been considered have gradually become apparent. Among them, the quality of the connection interface between the bonding pad and the bonding wire has a considerable influence on the reliability of the manufactured components. 'When the component size is getting smaller and smaller' the area where the pad is connected to the wire is gradually shrinking, so the pad needs to bear greater stress during wire bonding, and the adhesion between the dance ball and the wire (adherence ) Is also reduced. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ij 1 n--I u «tn nm 1 -IIT (f read the precautions on the back before filling in this page) For example, a protective layer covering a quiet area (Passivation Layer) The height will be higher ', so the die under the bonding pad will often have cracks when wire bonding. If polyimide or BCB (henzos Lyclohutene) polymer is used to make the protective layer around the pad relatively flat, although the above problems can be solved, the reliability of the packaged product will be reduced. The purpose of the invention and the main purpose of the present invention is therefore to provide a method for manufacturing a solder pad protective layer, which can flatten the protective layer around the solder pad and increase the subsequent tin. This paper size is applicable to Chinese national standards (CNS > A4 specification (210X297 mm) 463343 A7 ______B7_ 5. Reliability of the process () Process reliability = This method includes sequentially forming a first silicon oxide layer, a silicon nitride layer and A second silicon oxide layer is on the substrate and covers the static pad. Then the first oxide sand layer is planarized until the nitride cut layer. Then an opening is formed in the silicon nitride layer and the first silicon oxide layer to expose the silicon oxide layer. According to a preferred embodiment of the present invention, the method for forming the first silicon oxide layer described above may be, for example, a high-density plasma chemical vapor deposition method, and the method for forming the silicon nitride layer may be a low pressure method. In the chemical vapor deposition method, the formation method of the second silicon oxide layer may be, for example, a plasma enhanced chemical vapor deposition method, and the thicknesses of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer may be respectively 1K-10K angstrom, 1K-10K angstrom and 1K-20K angstrom. In addition, the planarization method of the second silicon oxide layer can be performed by, for example, chemical mechanical honing. The present invention uses the second silicon oxide layer as a pad protection layer. For the purpose of planarization, this not only solves the problem of cracks in the crystal during wire bonding, but also greatly improves the reliability of the packaged product. The brief description of the drawings is to allow the above and other objects, features, and advantages of the present invention to It is more obvious and easy to understand. A preferred embodiment is described below in conjunction with the accompanying drawings, and described in detail as follows: Figures 1A-1D A pad protection according to a preferred embodiment of the present invention __3_______ This paper size is applicable China National Standards (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs to print 463343 A7 B7 V. Description of the invention (layer manufacturing Method flow cross-section diagram. Marking description of the mesh 100: substrate 110: pads 120, 120a: first sand oxide layer 130 '130a: silicon nitride layer 140, 140a: second silicon oxide layer 150 : Opening 160: Double metal layer under solder ball 170: Solder ball (please read the precautions on the back before filling out this page) Packing _ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy For details, please refer to Section 1A- FIG. 1D is a cross-sectional view of a method for manufacturing a pad protection layer according to a preferred embodiment of the present invention. Referring to FIG. 1A, a pad 110 is formed on a substrate 100. The material may be, for example, an aluminum-copper alloy. Then, a first silicon oxide layer 120, a silicon nitride layer 130, and a second silicon oxide layer 14 are sequentially formed on the substrate 100. The thicknesses can be, for example, IK-10K angstrom, IK-10K angstrom, and 1K-20K. Aye. The formation methods of the first silicon oxide layer 120, the silicon nitride layer 130, and the second silicon oxide layer Mo can be, for example, high-density plasma chemical vapor deposition (High-Density Plasma Chemical Vapor Deposition; HDP CVD), Low Pressure Chemical Vapor Deposition (Low Pressure CVD) and Electricity Fees The paper size is common to the Chinese National Standard (CNS) A4 (210X297 mm) 4633 4 3 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs DESCRIPTION OF THE INVENTION () Plasma Enhance CVD. Please refer to FIG. 1B, and then use the silicon nitride layer 130 as a planarization end point to perform a planarization step on the second silicon oxide layer 140 to become The second silicon oxide layer 140a is flat at least on the surface of the protective layer around the bonding pad 110. The aforementioned planarization method can be, for example, chemical mechanical polishing (CMP). If CMP is used here, The planarization method can even achieve the effect of wafer planarization. Please refer to FIG. 1C, and then perform a lithography etching process to form the silicon nitride layer 130 and the first silicon oxide layer 120. The opening 150 exposes the surface of the solder pad Π0. At the same time, the nitrided sand layer 130 and the first oxidized sand layer 120 are transformed into the nitrided sand layer 130a and the first oxidized sand layer 120a, respectively. Please refer to FIG. ID, and then deposit tin on the substrate 100 Under Bump Metallurgy (UBM) 160, and then defected into Solder Bump Π0 above the opening ISO. Finally, the under metal ball 160 is not etched and is not covered by the solder ball 〇7 to complete the tin. The ball process. Because it is conventional to use polyurethane or BCB polymer to form a flat cover to cover the pads, but because polyimide or BCB polymer is an organic material, it is used for subsequent solder balls. The deposition of the metal layer and the corrosion resistance of the tapeworm are not enough to reduce the reliability of the packaged product. However, in the present invention, 'silicon oxide of inorganic material is used instead of polyimide or BCB polymer of organic material, so that The anti-corrosive force of the surface of the protective layer is high, and the anti-corrosive force for the subsequent deposition and etching of the complex metal layer under the solder ball will follow the Chinese paper standard (CNS) A4C (210X297 mm) according to the private paper scale. _n- HI I -II —I. J ·-I ^ -I----^^ 1 «mi 1 ^ 1 (Please read the precautions on the back before filling out this page) 463343 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs_ ______B7_ 5. The description of the invention () has been improved. In addition, the chemical mechanical honing method is used to planarize the uppermost silicon oxide layer 'to achieve a comprehensive planarization effect, which minimizes the possibility of cracks on the crystal surface during wire bonding. The inventor performed a die shear test on a package product with no flattened surface of the protective layer, and found that the cracks were mainly from the silicon nitride layer around the pad to the die below the pad. The possible reason is that the shear stress will be concentrated on the surface of the protective layer around the pad, and the silicon nitride layer is brittle. If the surface of the protective layer is flattened and the crystal shear stress test is performed, there is no problem of step high when the metal layer is deposited under the deposited solder balls, and a better pad height can be obtained. (bump height) and aspect ratio make the deposition of the metal layer under the solder ball easier. Such a structure allows the solder ball to withstand higher stress, and the final fracture surface occurs on the cross section of the solder ball. It is proved that the flattened protective layer can disperse the stress and avoid cracks on the crystal below the solder pad. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention can not only disperse the stress applied to the crystal cubes under the bonding pads during wire bonding, but also increase the chemical resistance of the corrosion resistance of the solder coating to the package, which greatly improves the reliability of the packaged product. Promotion. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (谙 Please read the notes on the back before filling in this page) -Order 6_ This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 〇 > < 297 mm)

Claims (1)

463343 器 D8 六、申請專利範圍 由請專利範圍 1. 一種銲墊護層的製造方法’可應用於—基底上，該 基底上至少已形成有一銲墊，該方法至少包括： 形成一第一氧化矽層於該基底上並覆蓋該銲墊； 形成一氮化矽層於該第一氧化矽層上； 形成一第二氧化矽層於該氮化矽層上；' 平坦化該第二氧化矽層，至該氮化矽層爲止：以及 形成一開口於該氮化砂層與該第一氧化砂層中，以暴 露出該銲塾之表面。 2. 如申請專利範圍第1項所述之銲墊護層的製造方 法，其中該第一氧化矽層之形成方法包括高密度電漿化學 氣相沈積法。 3_如申請專利範圍第1項所述之銲墊護層的製造方 法，其中該氮化矽層之形成方法包括低壓化學氣相沈積 法。 4_如申請專利範圍第1項所述之銲墊護層的製造方 法’其中該第二氧化矽層之彤成方法包括電漿增強式化學 氣相沈積法。 5.如申請專利範圍第1項所述之銲墊護層的製造方 ___ 7 (請先閱讀背面之注意事項再填寫本頁) 策. 1r 經濟部智总时.4局貞工消費合作钍印製 本紙張尺度適用中國國家梂準（CNS ) A4規格（2丨OXM7公釐） 經濟部智慧財產局肖工消f合作社印製 63343 K C8 D8 六、申請專利範圍 法，其中該第二氧化矽層之厚度約爲1K至20K埃。 6. 如申請專利範圍第1項所述之銲墊護層的製造方 法，其中平坦化該第二氣化矽層之方法包括化學機械硏磨 法。 7. 如申請專利範圍第1項所述之銲墊護層的製造方 法，更包括： 形成共形之一錫球下複金屬層於該開口之表面，並覆 蓋該開口周緣之該氮化矽層；以及 形成一錫球於該錫球下複金屬層之上。 8. —種銲墊護層的製造方法，可應用於已形成有一銲 墊之一基底上，該方法至少包括： 以高密度電漿化學氣相沈積法形成一第一氧化矽層於 該基底上並覆蓋該銲墊； 形成一氮化矽層於該第一氧化矽層上； 以電漿增強式化學氣相沈積法形成一第二氧化矽層於 該氮化矽層上； 以化學機械硏磨法平坦化該第二氧化矽層，至該氮化 砂層爲止；以及 依序蝕刻該氮化矽層與該第一氧化矽層以形成一開口 暴露出該銲墊之表面。 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家梯準（CNS > A4说格（210X297公釐） i· 4 3 8 8 8 8 A BCD 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 9. 如申請專利範圍第8項所述之銲墊護層的製造方 法，其中該第二氧化矽層之厚度至少爲該氮化矽層與該第 一氧化砂層厚度之總和。 10. 如申請專利範圍第8項所述之銲墊護層的製造方 法，其中該第一氧化矽層與該氮化矽層之厚度分別約爲1K 至10K埃。 U.如申請專利範圍第8項所述之銲墊護層的製造方 法，其中該第二氧化矽層之厚度約爲1K至20K埃。 12.如申請專利範圍第8項所述之銲墊護層的製造方 法，更包括： 形成共形之一錫球下複金屬層於該開口之表面，並覆 蓋該開口周圍之該氮化矽層；以及 形成一錫球於該錫球下複金屬層之上。 13· —種銲墊結構，該結構至少包括： 一銲墊位於一基底上； 共形之一第一氧化矽層位在該銲墊周圍之該基底上與 該銲墊表面之周緣； 共形之一氮化矽層位於該第一氧化矽層上：以及 ____^--- 本紙張尺度適用中國國家標牟（CNS M4说格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) 訂 A8 B8 C8 D8 六、申請專利範圍 平坦之一第二氧化矽層位於該氮化矽層上，該第二氧 化矽層之表面與該氮化矽層之表面最高處等高。 !4.如申請專利範圍第13項所述之銲墊結構，更包括： 一錫球下複金屬層位於暴露出之該銲墊上與該銲墊周 緣之部分該氮化砂層上；以及 ' 一錫球位於該錫球下複金屬層上。 15. 如申請專利範圍第13項所述之銲墊結構，其中該 第二氧化矽層之厚度至少爲該氮化矽層與該第一氧化矽層 厚度之總和。 16. 如申請專利範圍第Π項所述之銲墊結構，其中該 第一氧化矽層與該氮化矽層之厚度分別約爲1K至10K 埃。 1?·如申請專利範圍第13項所述之銲墊結構，其中該 第二氧化矽層之厚度約爲1K至20K埃。 463343 (請先閱讀背面之注意事項再填寫本I ) ir. 經濟部智慧財產局員工消費合作钍印製 14)- 本紙張尺度適用中國國家梯率（CNS ) Μ说格（21〇Χ297公釐）463343 器 D8 6. The scope of patent application is from the scope of patent application 1. A method for manufacturing a pad protection layer 'can be applied to-a substrate, at least a pad has been formed on the substrate, the method includes at least: forming a first oxidation A silicon layer on the substrate and covering the bonding pad; forming a silicon nitride layer on the first silicon oxide layer; forming a second silicon oxide layer on the silicon nitride layer; 'planarizing the second silicon oxide Layer to the silicon nitride layer: and forming an opening in the nitrided sand layer and the first oxide sand layer to expose the surface of the solder pad. 2. The method for manufacturing a pad protection layer as described in item 1 of the patent application scope, wherein the method for forming the first silicon oxide layer includes a high-density plasma chemical vapor deposition method. 3_ The method for manufacturing a pad protection layer as described in item 1 of the patent application scope, wherein the method for forming the silicon nitride layer includes a low-pressure chemical vapor deposition method. 4_ The method for manufacturing a pad protection layer as described in item 1 of the scope of the patent application, wherein the forming method of the second silicon oxide layer includes a plasma enhanced chemical vapor deposition method. 5. The manufacturer of the pad protection layer as described in item 1 of the scope of patent application ___ 7 (Please read the precautions on the back before filling out this page) Policy. 1r Ministry of Economy and Wisdom. 4 Bureau of Labor and Consumerism Cooperation尺度 The paper size for printing is applicable to China National Standards (CNS) A4 (2 丨 OXM7 mm), printed by Xiao Gongxiao, Intellectual Property Bureau, Ministry of Economic Affairs, 63633 K C8 D8. Patent Application Law, of which the second The thickness of the silicon oxide layer is about 1K to 20K Angstroms. 6. The method for manufacturing a pad protection layer as described in item 1 of the patent application scope, wherein the method of planarizing the second vaporized silicon layer includes a chemical mechanical honing method. 7. The method for manufacturing a pad protection layer as described in item 1 of the scope of the patent application, further comprising: forming a conformal metal layer under a solder ball on the surface of the opening, and covering the silicon nitride at the periphery of the opening. Layer; and forming a solder ball on the metal layer under the solder ball. 8. A method for manufacturing a pad protection layer, which can be applied to a substrate on which a pad has been formed. The method at least includes: forming a first silicon oxide layer on the substrate by a high-density plasma chemical vapor deposition method; Forming and covering the bonding pad; forming a silicon nitride layer on the first silicon oxide layer; forming a second silicon oxide layer on the silicon nitride layer by a plasma enhanced chemical vapor deposition method; using chemical mechanical The honing method planarizes the second silicon oxide layer until the nitrided sand layer; and sequentially etches the silicon nitride layer and the first silicon oxide layer to form an opening to expose the surface of the bonding pad. (Please read the notes on the back before filling this page) The size of the paper is applicable to the Chinese National Standard (CNS > A4) (210X297 mm) i · 4 3 8 8 8 8 A BCD VI. Economic scope of patent application Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative 9. The manufacturing method of the pad protection layer as described in item 8 of the scope of patent application, wherein the thickness of the second silicon oxide layer is at least the silicon nitride layer and the first oxide The sum of the thickness of the sand layer. 10. The method for manufacturing a pad protection layer as described in item 8 of the scope of the patent application, wherein the thickness of the first silicon oxide layer and the silicon nitride layer are about 1K to 10K angstroms, respectively. U. The manufacturing method of the pad protection layer according to item 8 of the patent application scope, wherein the thickness of the second silicon oxide layer is about 1K to 20K Angstrom. 12. The pad protection layer according to item 8 of the patent application scope The manufacturing method further includes: forming a conformal metal layer under a solder ball on the surface of the opening, and covering the silicon nitride layer around the opening; and forming a solder ball on the metal layer under the solder ball. 13 · —A solder pad structure, the structure includes at least: A solder pad is located on a substrate; a conformal first silicon oxide layer is located on the substrate around the pad and the periphery of the pad surface; a conformal silicon nitride layer is located on the first silicon oxide layer Above: And ____ ^ --- This paper size applies to Chinese national standards (CNS M4 scale (210X297 mm) (please read the precautions on the back before filling out this page) Order A8 B8 C8 D8 VI. Apply for a patent A second silicon oxide layer having a flat range is located on the silicon nitride layer, and the surface of the second silicon oxide layer is the same as the highest point of the surface of the silicon nitride layer.! 4. As described in item 13 of the scope of patent application The solder pad structure further includes: a metal layer under the solder ball is located on the exposed nitride layer on the solder pad and a portion of the periphery of the solder pad; and a solder ball is located on the metal layer under the solder ball. 15. The pad structure described in item 13 of the scope of patent application, wherein the thickness of the second silicon oxide layer is at least the sum of the thickness of the silicon nitride layer and the first silicon oxide layer. The pad structure described in item Π, wherein the first silicon oxide layer and the silicon nitride layer The thickness is about 1K to 10K Angstroms respectively. 1 ·· As described in the patent application for item 13 of the pad structure, wherein the thickness of the second silicon oxide layer is about 1K to 20K Angstroms. 463343 (Please read the note on the back first Please fill in this item again. I) ir. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Co-operation of the Ministry of Economic Affairs 14)-This paper size is applicable to China's National Slope (CNS) M Grid (21〇 × 297 mm)
TW089126794A 2000-12-14 2000-12-14 Method for manufacturing passivation layer of bonding pad TW463343B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI503904B (en) * 2012-05-10 2015-10-11 Vanguard Int Semiconduct Corp Method for fabricating a bonding pad structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI503904B (en) * 2012-05-10 2015-10-11 Vanguard Int Semiconduct Corp Method for fabricating a bonding pad structure

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