TWI730884B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and its forming method are provided. The semiconductor structure includes a substrate, a dielectric layer on the substrate and a conductive layer on the dielectric layer. In some embodiments, the semiconductor structure also includes a stacked structure on the conductive layer, and the stacked structure exposes at least one region of the top surface of the conductive layer. In some embodiments, the stacked structure includes an anti-reflective coating layer (ARC layer) on the conductive layer, a first passivation layer on the ARC layer, and a second passivation layer on the first passivation layer. The second passivation layer also covers an inner edge of the first passivation layer and an inner edge of the second passivation layer.

Description

Semiconductor structure and its forming method

The present invention relates to a semiconductor structure and a method of forming the same, and more particularly to a semiconductor structure with a double protective layer for contact pads and a method of forming the same.

In the process of manufacturing and packaging the semiconductor structure, the metal layer above the semiconductor element (for example, the uppermost metal layer) includes a plurality of exposed areas as bonding pads. The packaged semiconductor device can be electrically connected to an external circuit through the contact pad. Furthermore, an anti-reflective coating layer is generally formed on the metal layer. When the photoresist above the metal layer is patterned by an optical lithography process, the anti-reflective coating can reduce the surface of the metal layer. Reflected light. However, there is moisture in the environment where the semiconductor structure is stored and used. The moisture may enter the package through the exposed contact pads, and then corrode the metal layer and/or the anti-reflective coating on the metal layer, and affect the manufacturing process. Obtain the electrical performance and reliability of the semiconductor structure.

Furthermore, with the continuous and rapid development of integrated circuits (ICs), in order to meet consumer demand for miniaturized electronic devices, the size of semiconductor components in the devices has decreased, and the integration degree has also increased. The size of the semiconductor element decreases, the thickness of each material layer and the distance between each component also shrink. If the semiconductor element’s ability to block moisture is not good, before the semiconductor element is used (such as the storage state before sale) and After a period of use, the corrosion caused by moisture entering the semiconductor element will more severely affect the electrical performance and reliability of the semiconductor element.

Although the existing semiconductor structures and their forming methods can cope with their original intended use, they still have problems that need to be overcome in terms of their structures and manufacturing methods. How to improve the semiconductor structure to avoid the occurrence of the above-mentioned situation, and the improved semiconductor structure is also suitable for the manufacture of electronic devices including components with different electronic characteristics, is indeed an important issue for the related industry.

Some embodiments of the present invention disclose a semiconductor structure including a substrate, a dielectric layer above the substrate, and a conductive layer above the dielectric layer. The semiconductor structure of some embodiments also includes a stacked structure on the conductive layer, and the stacked structure exposes at least one area of the top surface of the conductive layer. In the semiconductor structure of some embodiments, the aforementioned stacked structure includes an anti-reflective coating layer (ARC layer) located above the aforementioned conductive layer, and a first protective layer ( first passivation layer), and a second passivation layer (second passivation layer) located above the first protection layer, wherein the second passivation layer further extends to the inner edge of the first protection layer and the resistance The inner edge of the reflective coating layer covers the inner edge of the first protective layer and the inner edge of the anti-reflective coating.

Some embodiments of the present invention disclose a method for forming a semiconductor structure, including providing a substrate, and forming a dielectric layer on the substrate. In some embodiments, the method for forming the semiconductor structure also includes forming a conductive layer above the dielectric layer, and forming a stacked structure on the conductive layer, and the stacked structure exposes at least the top surface of the conductive layer A bonding pad region. According to some embodiments of the present disclosure, the foregoing stacked structure includes an anti-reflective coating (ARC layer) located above the conductive layer, a first passivation layer (first passivation layer) located above the anti-reflective coating, and A second passivation layer above the first protective layer, wherein the second passivation layer further extends to the inner edge of the first protective layer and the inner edge of the anti-reflective coating, And cover the inner edge of the first protective layer and the inner edge of the anti-reflective coating.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, rather than to show the relationship between the different embodiments discussed.

Furthermore, spatially relevant terms can be used in the following descriptions, such as "below", "below", "below", "above", "above" and other similar The terms are used to simplify the statement of the relationship between one element or component and other elements or other components as shown in the figure. This space-related wording includes not only the directions depicted in the diagrams, but also the different orientations of the device in use or operation. The device can be positioned in other directions (rotated by 90 degrees or in other directions), and the spatial description used here can be interpreted accordingly.

Some changes of the embodiment are described below. In the different drawings and illustrated embodiments, similar component symbols are used to designate similar components. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

The embodiments of the present disclosure provide a semiconductor structure and a method of forming the same. In some embodiments, by forming a double-layer protective layer to completely cover the anti-reflective coating on the metal layer, it can effectively prevent water vapor from entering the semiconductor structure from the contact pad area of the metal layer and causing corrosion of the anti-reflective coating. , Thereby improving the electrical performance and reliability of the manufactured semiconductor structure.

The semiconductor structure of the present disclosure does not particularly limit the applicable device types. One or more integrated circuit devices (IC devices) formed on the substrate may include different types of semiconductor devices, including planar devices and non-planar devices. Therefore, a planar structure or a three-dimensional structure (three-dimensional structure) device, such as a metal oxide half field effect transistor, (MOSFET), can be disposed in the substrate of some embodiments of the disclosure, and the contact of the upper metal layer The bonding pad region can be electrically connected with the aforementioned elements.

FIG. 1 is a top view of a contact pad area in a semiconductor structure according to some embodiments of the disclosure. In some embodiments, the fabrication of the semiconductor device is completed on the substrate, and after the insulating layer and the conductive layer (such as a metal layer) are subsequently stacked, a part of the top surface of the conductive layer is exposed as a contact pad area (bonding pad). pad region) R _B , as shown in Figure 1. According to some embodiments of the present disclosure, a double-layer protective layer is provided above the metal layer, such as the inner side of the upper protective layer (ie, the second protective layer 28 proposed in the following embodiments) as shown in Figure 1. The edge 28E _{I and the inner edge 27E I} of the underlying protective layer (ie, the first protective layer 27 proposed in the following embodiments) are used to prevent moisture corrosion, thereby improving the electrical performance and reliability of the semiconductor structure.

Notably, FIG. 1 shows only the first contact pad area R _B of a hexagon, but this is merely one example, the semiconductor structure may comprise a plurality of application of the contact pad region R _B, and contacting the embodiment planar shape and arrangement of the pad region R _B is not particularly limited, but to do the appropriate changes and adjustments depending on the needs of practical application.

FIGS. 2A-2G are schematic cross-sectional views showing various intermediate stages of forming the semiconductor structure shown in FIG. 1 according to some embodiments of the present disclosure. Figures 2A-2G are, for example, cross-sectional schematic diagrams at various stages of the manufacturing process drawn corresponding to the section line C-C in Figure 1. Furthermore, in order to simplify the drawings for clear description, FIGS. 2A-2G are drawn about a method for forming a double-layer protective layer in a contact pad region in a semiconductor structure according to some embodiments of the disclosure.

Please refer to Figure 2A, a substrate 20 is provided. One or more integrated circuit components (not shown) may be formed on the substrate 20. The integrated circuit components include, for example, transistors, and a dielectric layer 22 covers the integrated circuit components. In order to simplify the drawings for clear description, only the substrate 20 and the dielectric layer 22 on the substrate 20 are shown in FIGS. 2A-2G. In some embodiments, the material of the substrate 20 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon on an insulating layer, other suitable materials, or a combination of the foregoing.

Next, in some embodiments, a conductive layer 24 is formed on the dielectric layer 22. The conductive layer 24 may be a single-layer or multi-layer conductive structure, and may be metal-containing layers. In order to simplify the drawings for clear description, only a single-layer conductive layer 24 is shown in FIGS. 2A-2G, but the disclosure is not limited thereto. In some embodiments, the conductive layer 24 includes aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), a combination of the foregoing materials, or other similar materials.

Then, an anti-reflective material layer 260 is formed on the conductive layer 24. In some embodiments, the anti-reflective material layer 260 includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), a combination of the foregoing materials , Or other similar materials. In some embodiments, the anti-reflective material layer 260 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, Or similar process formation.

After that, a first passivation material layer 270 is formed on the anti-reflective material layer 260, and a first patterning process is performed on the first passivation material layer 270 and the anti-reflective material layer 260 to Define the first protective layer and the anti-reflective coating. The first patterning process is, for example, an optical lithography process.

In some embodiments, the material of the first protective material layer 270 is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, other protective materials, or a combination of the foregoing materials. In an example, the first protective material layer 270 includes silicon oxide, but the disclosure is not limited to this. Furthermore, the first protective material layer 270 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a high density plasma chemical vapor deposition (HDPCVD) process. , Or a combination of the foregoing processes.

As shown in FIG. 2A, in some embodiments, after the first protective material layer 270 is formed on the anti-reflective material layer 260, the first photoresist material layer 311 is formed on the first protective material layer 270, and the A mask 331 is above the first photoresist layer 311.

Please refer to FIG. 2B. Next, in some embodiments, the first photoresist material layer 311 (FIG. 2A) is patterned through the first mask 331, such as exposure and development processes, so that the first mask The pattern of 331 is transferred to the first photoresist material layer 311 to form a patterned first photoresist layer 31.

Please refer to FIG. 2C. Then, according to the patterned first photoresist layer 31, the underlying first protective material layer 270 and the anti-reflective material layer 260 are patterned to form the first protective layer 27 and the anti-reflective coating 26 , And exposes the first region (first region) R ₁ of the top surface 24 a of the conductive layer 24. In some embodiments, for example, in the same manufacturing process, an appropriate etching gas is selected according to the materials of the first protective material layer 270 and the anti-reflective material layer 260 to perform the patterning process.

Please refer to FIG. 2D, and then, for example, an ashing process is performed to remove the patterned first photoresist layer 31.

As shown in FIG. 2D, in some embodiments, after the patterning process shown in FIG. 2C, the inner edge 27E _{I of the first protective layer 27 and the inner edge 26E I of the} anti-reflective coating 26 are approximately Align on top (or coplanar). As shown in Figure 2D, the anti-reflective coating 26 includes a first opening 26P having a first inner diameter (first diameter) D1, and the first protective layer 27 includes a second inner diameter D2.的 second opening 27P. In addition, the positions of the first opening 26P of the anti-reflective coating 26 and the second opening 27P of the first protective layer 27 correspond to the contact pad area formed subsequently. In this example, the second opening 27P and the first opening 26P have the same size (/area), and both are larger than the opening size (/area) of the subsequently formed contact pad area.

Please refer to FIG. 2E. Next, in some embodiments, a second passivation material layer 280 is deposited on the first passivation layer 27, and the second passivation material layer 280 is along the first passivation layer 27. The inner edge 27E _{I of a protective layer 27 and the inner edge 26E I of the} anti-reflective coating 26 are _{deposited to cover the first region R 1} exposed by the top surface 24 a of the conductive layer 24.

In some embodiments, the material of the second protective material layer 280 is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, other protective materials, or a combination of the foregoing materials. The second protective material layer 280 can be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma chemical vapor deposition (HDPCVD) process, or the foregoing Formed by a combination of manufacturing processes.

Furthermore, compared to the first protective material layer 270, a material having a higher ability to block moisture can be selected to form the second protective material layer 280. In one example, the second protective material layer 280 includes silicon nitride, and the first protective material layer 270 includes silicon oxide, but the disclosure is not limited thereto.

After that, a second patterning process is performed on the second protective material layer 280 to form the second protective layer and form a contact pad region of the semiconductor structure of some embodiments of the disclosure.

Referring to FIG. 2F, in some embodiments, a patterned second photoresist layer 32 is formed on the second protective material layer 280. The forming method is, for example, first forming a second photoresist material layer (not shown) on the second protective material layer 280, and providing a second mask 332 above the second photoresist material layer, and then using the second mask 332 patterning the second photoresist material layer to form the patterned second photoresist layer 32. To simplify the drawing, FIG. 2F only shows the patterned second photoresist layer 32 and the second mask 332 above the second protective material layer 280. Furthermore, in some embodiments, the pattern of the first mask 331 may be different from the pattern of the second mask 332.

Please refer to FIG. 2G. Next, in some embodiments, a second patterning process is performed on the second protective material layer to form the second protective layer 28 and expose the top surface 24a of the conductive layer 24 The second region (second region) R ₂ . In some embodiments, the second region R ₂ is located in the aforementioned first region R ₁ and overlaps the first region R ₁ , and the area of the second region R ₂ is smaller than that of the first region R ₁ . The second region R _{2 formed here is a contact pad region R B} of the semiconductor structure of some embodiments of the disclosure shown in FIG. 1. After that, for example, an ashing process is performed to remove the patterned second photoresist layer 32.

As shown in FIG. 2G, according to some embodiments, after performing the aforementioned second patterning process, the second protective layer 28 includes a third opening 28P having a third diameter D3. Moreover, the third opening 28P is smaller than the second opening 27P of the first protective layer 27 and also smaller than the first opening 26P of the anti-reflective coating 26. Furthermore, in some embodiments, the second protective layer 28, the first protective layer 27, and the anti-reflective coating 26 may form a stacked structure 29, and the stacked structure 29 may expose the contact pads on the top surface 24a of the conductive layer 24 region, and the third opening 28P is the stacked structure 29 exposed by the contact conductive layer formed here the top surface 24a of the pad region 24 of R _B.

Generally speaking, after the semiconductor components are manufactured and packaged, a series of component reliability tests are required, such as high/low temperature operating life tests (high/low temperature operating life), high temperature and high humidity tests, etc. A variety of related tests to simulate the reliability of semiconductor components under certain humidity and temperature conditions before use (such as storage) and after use.

Take the accelerated temperature, humidity and bias test (THB) as an example. Its purpose is to evaluate the resistance of component products to moisture under high temperature, high humidity, and bias conditions, and accelerate their failure process; its test The conditions are, for example, under the conditions of a temperature of 85°C and a relative humidity of 85%, a bias voltage of 1.1 V _{CC is} applied, and tests such as 168 hours, 5000 hours, and 1000 hours are performed to evaluate the ability of the sample to resist the long-term penetration of water vapor.

Take the Highly Accelerated Stress Test (HAST) as an example. Its purpose is to evaluate the resistance of component products to humidity under high temperature, high humidity, and high air pressure conditions under bias, and accelerate its failure process; For example, the test condition is a HAST test at a temperature of 130° C., a relative humidity of 85% and an air pressure of 2.3 atm, with a bias of 1.1 V _CC applied, for example, two separate 96 hours, plus a total of 192 hours. Compared with the THB test, the HAST test is a test conducted in a high-density water vapor high-pressure environment above 100°C. The HAST uses the water vapor pressure in the test tank to be much higher than the water vapor partial pressure inside the sample. Features: It can accelerate the penetration of moisture into the sample to evaluate the sealing performance of the component.

As shown in FIG. 2G, the anti-reflective coating 26 on the metal layer 24 is easily corroded if it is invaded by moisture, and the material may deteriorate and spread beyond the original forming position after the device is used for a period of time. Taking the titanium nitride layer as the anti-reflection coating 26 as an example, titanium nitride may produce titanium oxynitride (silver or silver white solid) under the intrusion of moisture. The chemical reaction formula is as follows.

2TiN _(S) +4H ₂ O _(g) → 2TiON _X(S) +2NH _3(g) +H _2(g)

If you perform detailed inspection with an electron microscope, you can observe the precipitated and diffused silver or silver-white titanium oxynitride.

Please refer to Figure 1 and Figure 2G at the same time. According to some embodiments, the anti-reflective coating 26 in the stack structure 29 directly contacts the conductive layer 24, and the first protective layer 27 is disposed on the anti-reflective coating 26 and directly contacts the top surface 26 a of the anti-reflective coating 26. Furthermore, the second protective layer 28 directly contacts and completely covers the top surface 27a of the first protective layer 27, the inner edge 27E _{I of the} first protective layer 27, and the inner edge 26E _{I of the} anti-reflective coating 26. According to some embodiments of the present disclosure, by forming a two-layer protective layer, including a first protective layer 27 and a second protective layer 28, and the second protective layer 28 further covers the first protective layer 27 and the anti-reflective coating 26 the side walls can be effectively prevented second region R ₂ / R _B the contact pad region 26 and penetrating into the antireflective coating caused by corrosion, the semiconductor structure to solve the traditional anti-reflective coating 26 due to corrosion by water vapor since water vapor is discolored, The problem of precipitation caused defects in the overall structure. According to actual inspection tests, the semiconductor structure according to some embodiments of the present disclosure can pass multiple high temperature and high humidity tests, including the aforementioned accelerated temperature, humidity and bias test (THB) and high pressure accelerated temperature, humidity and bias test (HAST).

In some embodiments, the second protective layer 28 and the first protective layer 27 may include different materials. For example, compared to the first protective layer 27, the second protective layer 28 may include a material having a higher ability to block moisture. But this disclosure is not limited to this. The second protective layer 28 may also contain the same material as the first protective layer 27. For example, the same material with good moisture blocking ability is used for the production of the protective layer.

Furthermore, as shown in Figure 2G, the thickness of the second protective layer 28 covering the top surface 27a of the first protective layer 27 is t1, and the second protective layer 28 covers the inner edge 27E _{I of the} first protective layer 27 and anti-reflection The thickness of the inner edge 26E _{I of the coating 26 is t2.} In some embodiments, the thickness t2 may be less than or substantially equal to the thickness t1, which is not limited in the present disclosure. The thickness of the second protective layer 28 covers the first protective layer 27 and thicker anti-reflective coating 26, may block the entry of moisture corrosion antireflective coating 26, the thickness t2 of not affecting the desired contact of the contact pad region R _B The area and other components are mainly set. In some embodiments, the thickness t2 of the second protective layer 28 covering the inner edge 27E _{I of the} first protective layer 27 and the inner edge 26E _I of the anti-reflective coating 26 is greater than or equal to about 3 μm. In some other embodiments, the thickness t2 is greater than or equal to about 5 μm. In some other embodiments, the thickness t2 is in the range of about 3 μm to about 8 μm. It should be noted that the foregoing thickness values and/or ranges are only part of the exemplary aspect, and the present disclosure is not limited to the foregoing values and/or ranges.

Furthermore, the semiconductor structure of the embodiment of the present disclosure can also be slightly modified or changed according to actual design requirements. FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the disclosure. The same or similar components in FIG. 3 and FIG. 2G use the same or similar reference numerals, and in order to simplify the description, the components that are the same or similar to those in the foregoing illustration and the forming process steps thereof will not be described in detail here.

As shown in FIG. 3, in some embodiments, a transistor 21 is formed on the substrate 20, and the dielectric layer 22 covers the transistor 21. In this example, the transistor 21 includes, for example, a gate electrode G, a gate dielectric layer GD between the gate electrode G and the substrate 20, a source electrode S formed in the substrate 20 and located on both sides of the gate electrode G, and Dip pole D. Of course, the transistor 21 shown in Figure 3 is only one example, and other structure types or/and a greater number of integrated circuit elements can also be applied to the semiconductor structure of the embodiment, and the present disclosure does not apply to this. Don't make any restrictions.

Furthermore, a conductive layer 24 is formed on the dielectric layer 22. In this example, the conductive layer 24 includes a multi-layer conductive structure, for example, a first conductive layer 241 located above the dielectric layer 22, a second conductive layer 242 located above the first conductive layer 241, and a second conductive layer 242 located above. The upper third conductive layer 243. The first conductive layer 241, the second conductive layer 242, and the third conductive layer 243 include aluminum (Al), copper (copper, Cu), titanium (Ti), titanium nitride (TiN), the aforementioned Combination of materials, or other similar materials.

The semiconductor structure shown in FIG. 3 further includes the aforementioned stacked structure 29 formed on the third conductive layer 243, and the stacked structure 29 can expose the contact pad area of the top surface 24a of the conductive layer 24. In some embodiments, the stacked structure 29 sequentially includes the second protective layer 28, the first protective layer 27, and the anti-reflective coating 26 from top to bottom. Wherein, the anti-reflective coating 26 includes a first opening 26P having a first inner diameter D1, the first protective layer 27 includes a second opening 27P having a second inner diameter D2, and the second protective layer 28 includes a third inner diameter D3. The third opening 28P. As shown in Figure 3, the second opening 27P and the first opening 26P have approximately the same size, and the third opening 28P is smaller than the second opening 27P of the first protective layer 27 and the first opening 27P smaller than the anti-reflective coating 26 Opening 26P. _{The region R 2 of} the top surface of the third conductive layer 243 exposed by the third opening 28P is _{a contact pad region (such as the contact pad region R B} shown in FIG. 1) of the semiconductor structure of some embodiments of the disclosure. Furthermore, the above-mentioned conductive layer 24 can be electrically connected to the transistor 21, and the contact pad area on the top surface of the conductive layer 24 (/third conductive layer 243) exposed by the stacked structure 29 is used as the contact pad ( bonding pad) and can be connected to a wire (not shown).

Based on the above, the semiconductor structure and formation method proposed according to some embodiments of the present disclosure have many advantages. By forming a two-layer protective layer, for example, the above-mentioned first protective layer 27 and the second protective layer 28 are included, and the second protective layer 28 more completely covers the sidewalls of the first protective layer 27 and the anti-reflective coating 26, such as The second protective layer 28 shown in Figures 2G and 3 completely covers the inner edge 27E _{I of the} first protective layer 27 and the inner edge 26E _{I of the} anti-reflective coating 26 to effectively prevent moisture from contacting the _{second region R 2 /} pad region R _B permeation caused by corrosion of the antireflective coating 26 into the anti-reflective coating 26, to solve the problem of a conventional semiconductor structure 26 by the antireflection coating due to corrosion and discoloration of the water vapor, so that the overall resulting structure precipitated defects, Furthermore, the electrical performance and reliability of the manufactured semiconductor structure are greatly improved. Furthermore, the method for forming the semiconductor structure proposed in the embodiments of the present disclosure can simply complete the fabrication of the semiconductor structure, and is compatible with the existing process, without increasing the complexity of the process or/and greatly increasing the production cost, but It can also significantly improve the electrical performance and reliability of the prepared semiconductor structure. Therefore, the semiconductor structure and formation method proposed in the embodiments of the present disclosure have great application value.

Although the present invention has been disclosed in several preferred embodiments as described above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make any changes and modifications without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

20: Base

21: Transistor

22: Dielectric layer

24: conductive layer

24a: The top surface of the conductive layer

241: first conductive layer

242: second conductive layer

243: third conductive layer

26: Anti-reflective coating

260: Anti-reflective material layer

26P: first opening

26a: Top surface of anti-reflective coating

27: The first protective layer

270: The first protective material layer

27P: second opening

27a: The top surface of the first protective layer

28: The second protective layer

280: second protective material layer

28P: third opening

26E _I , 27E _I , 28E _I : inside edge

29: Stacked structure

31: Patterned first photoresist layer

311: first photoresist material layer

331: first mask

32: Patterned second photoresist layer

332: second mask

D1: first inner diameter

D2: second inner diameter

D3: Third inner diameter

R _B: contact pad area

R ₁ : The first region

R ₂ : second area

t1, t2: thickness

G: Gate

GD: gate dielectric layer

S: source

D: Dip pole

FIG. 1 is a top view of a contact pad region in a semiconductor structure according to some embodiments of the disclosure. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are schematic cross-sectional views showing various intermediate stages of forming the semiconductor structure shown in FIG. 1, according to some embodiments of the present disclosure. Among them, the 2A-2G drawing corresponds to the section line C-C of the first drawing. FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the disclosure.

20: Base

22: Dielectric layer

24: conductive layer

24a: The top surface of the conductive layer

26: Anti-reflective coating

26a: Top surface of anti-reflective coating

27: The first protective layer

27a: The top surface of the first protective layer

28: The second protective layer

28P: third opening

26E _I , 27E _I : inside edge

29: Stacked structure

D3: Third inner diameter

R ₂ : second area

t1, t2: thickness

Claims (20)

A semiconductor structure includes: a dielectric layer located above a substrate; a conductive layer located above the dielectric layer; a stacked structure located on the conductive layer and exposing at least one of the top surface of the conductive layer Area, the stacked structure includes: an anti-reflective coating layer (ARC layer) located above the conductive layer; and a first passivation layer (first passivation layer) located above the anti-reflective coating; And a second passivation layer located above the first passivation layer, the second passivation layer extending and covering the top surface of the first passivation layer and the inner edge of the first passivation layer And the inner edge of the anti-reflective coating, and the second protective layer exposes at least the area of the top surface of the conductive layer. The semiconductor structure of claim 1, wherein the inner edge of the first protective layer is coplanar with the inner edge of the anti-reflection coating. The semiconductor structure of claim 1, wherein the anti-reflection coating directly contacts the conductive layer, the second protection layer directly contacts the top surface of the first protection layer, the inner edge of the first protection layer, and the anti-reflection The inner edge of the coating. The semiconductor structure of claim 1, wherein the anti-reflection coating includes a first opening having a first diameter (first diameter), and the first opening corresponds to the conductive layer exposed by the stacked structure Of the area. The semiconductor structure of claim 4, wherein the first protection layer includes a second opening having a second inner diameter (second diameter), and the second opening corresponds to the region of the conductive layer exposed by the stacked structure. The semiconductor structure of claim 5, wherein the second protective layer includes a third opening having a third diameter, the third opening being smaller than the second opening and smaller than the first opening. The semiconductor structure of claim 5, wherein the second opening and the first opening have the same size and corresponding positions. The semiconductor structure of claim 1, wherein the conductive layer located above the dielectric layer is a single-layer or multi-layer metal-containing layer. The semiconductor structure of claim 1, wherein the second protective layer and the first protective layer comprise different materials. The semiconductor structure of claim 1, wherein the thickness of the second protective layer covering the inner edge of the first protective layer and the inner edge of the anti-reflection coating is greater than or equal to 3 μm. A method for forming a semiconductor structure includes: providing a substrate, and forming a dielectric layer above the substrate; forming a conductive layer above the dielectric layer; forming a stack structure on the conductive layer, and the stack The structure exposes at least one bonding pad region (bonding pad region) on the top surface of the conductive layer, and the stacked structure includes: an anti-reflective coating layer (ARC layer) located above the conductive layer; A first passivation layer (first passivation layer) located above the anti-reflective coating; and a second passivation layer (second passivation layer) located above the first protective layer, and the second protective layer is further from the The top surface of the first protective layer extends to the inner edge of the first protective layer and the inner edge of the anti-reflective coating, and covers the top surface of the first protective layer and the inner side of the first protective layer Edge and the inner edge of the anti-reflective coating, and the second protective layer exposes at least the contact pad area of the top surface of the conductive layer. The method for forming a semiconductor structure of claim 11, wherein forming the stacked structure includes: forming an anti-reflective material layer on top of the conductive layer; forming a first passivation material layer layer) above the anti-reflective material layer; perform a first patterning process on the first protective material layer and the anti-reflective material layer to form the first protective layer and the anti-reflective coating, and The first region (first region) of the top surface of the conductive layer is exposed. The method for forming a semiconductor structure according to claim 12, wherein the inner edge of the first protective layer is aligned with the inner edge of the anti-reflection coating. The method for forming a semiconductor structure according to claim 12, wherein the first patterning process includes: forming a first photoresist material layer on the first protective material layer; and providing a first mask on the first photoresist material layer Above; pattern the first photoresist material layer with the first mask to form a patterned first Photoresist layer; according to the patterned first photoresist layer, a patterning process is performed on the underlying first protective material layer and the anti-reflective material layer to expose the first area and form the first protective layer and the anti-reflective material layer Reflective coating; and removing the patterned first photoresist layer. The method for forming a semiconductor structure according to claim 14, wherein the anti-reflective coating includes a first opening having a first inner diameter (first diameter) corresponding to the contact pad region, and the first protective layer includes A second opening with two second diameters corresponds to the contact pad area, the second opening and the first opening have the same size, and both the second opening and the first opening are larger than the contact pad area. The method for forming a semiconductor structure according to claim 14, wherein after forming the first protective layer and the anti-reflective coating, forming the stacked structure further comprises: depositing a second passivation material layer on the second passivation material layer Above a protective layer, and the second protective material layer is deposited along the inner edge of the first protective layer and the inner edge of the anti-reflective coating and covers the first area of the top surface of the conductive layer; and A second patterning process is performed on the second protective material layer to form the second protective layer and expose the second region (second region) of the top surface of the conductive layer; wherein, the first The second area is located in the first area and smaller than the first area, and the second area is the aforementioned contact pad area. According to claim 16, the method for forming a semiconductor structure, wherein the second patterning process includes: Forming a second photoresist material layer on the second protective material layer; providing a second mask above the second photoresist material layer; patterning the second photoresist material layer with the second mask , To form a patterned second photoresist layer; perform a patterning process on the second protective material layer underneath according to the patterned second photoresist layer to expose the second area and form the second protective layer; And removing the patterned second photoresist layer. The method for forming a semiconductor structure of claim 17, wherein the anti-reflective coating directly contacts the conductive layer, and the second protective layer directly contacts and completely covers the top surface of the first protective layer and the first protective layer The inner edge and the inner edge of the anti-reflective coating. The method for forming a semiconductor structure of claim 11, wherein the thickness of the second protective layer covering the inner edge of the first protective layer and the inner edge of the anti-reflection coating is greater than or equal to 3 μm. The method for forming a semiconductor structure of claim 11, wherein the thickness of the second protective layer covering the inner edge of the first protective layer and the inner edge of the anti-reflective coating is in the range of 3 μm to 8 μm.

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