TW201513233A - 層疊式封裝結構及其製法 - Google Patents

層疊式封裝結構及其製法 Download PDF

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TW201513233A
TW201513233A TW102134972A TW102134972A TW201513233A TW 201513233 A TW201513233 A TW 201513233A TW 102134972 A TW102134972 A TW 102134972A TW 102134972 A TW102134972 A TW 102134972A TW 201513233 A TW201513233 A TW 201513233A
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layer
package
dielectric layer
line
metal
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TW102134972A
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TWI517269B (zh
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林邦群
王維賓
李春源
唐紹祖
蔡瀛洲
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矽品精密工業股份有限公司
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Priority to TW102134972A priority Critical patent/TWI517269B/zh
Priority to CN201310478867.3A priority patent/CN104517922B/zh
Priority to US14/290,145 priority patent/US9362217B2/en
Publication of TW201513233A publication Critical patent/TW201513233A/zh
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Publication of TWI517269B publication Critical patent/TWI517269B/zh

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Abstract

一種層疊式封裝結構及其製法，該製法係包括：提供第一封裝件，其係包括：介電層，係具有相對之第一表面與第二表面；層疊線路層，係嵌埋於該介電層中，且外露於該第一表面與第二表面；複數金屬柱，係設於該介電層的第一表面上，且電性連接該層疊線路層；半導體晶片，係接置於該介電層的第一表面上，且電性連接該層疊線路層；及封裝膠體，係形成於該介電層的第一表面上，並包覆該半導體晶片與金屬柱，且具有複數對應外露該金屬柱之頂端的封裝膠體開孔；以及於該封裝膠體上接置第二封裝件，使該第二封裝件電性連接該等金屬柱。本發明能有效增進產能與良率。

Description

層疊式封裝結構及其製法
本發明係有關於一種封裝結構及其製法，尤指一種層疊式封裝結構及其製法。
隨著電子產品逐漸朝微型化發展，印刷電路板(PCB)表面可供設置半導體封裝件的面積越來越小，因此遂發展出一種半導體封裝件之立體堆疊技術，其係於一半導體封裝件上疊置另一半導體封裝件，而成為一層疊式封裝結構(package on package，簡稱POP)，以符合小型表面接合面積與高密度元件設置之要求。
第1圖所示者，係習知之層疊式封裝結構的剖視圖。
如圖所示，其係於底封裝件11上形成封裝膠體111後，以雷射燒灼形成複數貫穿且外露電性連接墊112之封裝膠體開孔1110，接著，在該封裝膠體開孔1110中的電性連接墊112上接置導電元件113，另一方面，在頂封裝件12的底面接置複數銲球121，然後，將該頂封裝件12接置於該底封裝件11上，使該頂封裝件12的銲球121電性連接該底封裝件11的導電元件113。
惟，前述習知之層疊式封裝結構須使用雷射將該封裝膠體打穿，即雷射鑽孔的深度較深，進而拉長製程時間，降低產能；此外，隨著電子產品的數入/輸出(I/O)數量增加，電性連接墊之間的間距隨之縮小，而容易在堆疊封裝件時發生銲料橋接(solder bridge)現象，降低整體良率。
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種層疊式封裝結構之製法，係包括：提供第一封裝件，其係包括：介電層，係具有相對之第一表面與第二表面；層疊線路層，係嵌埋於該介電層中，且外露於該第一表面與第二表面；複數金屬柱，係設於該介電層的第一表面上，且電性連接該層疊線路層；半導體晶片，係接置於該介電層的第一表面上，且電性連接該層疊線路層；及封裝膠體，係形成於該介電層的第一表面上，並包覆該半導體晶片與金屬柱，且具有複數對應外露該金屬柱之頂端的封裝膠體開孔；以及於該封裝膠體上接置第二封裝件，使該第二封裝件電性連接該等金屬柱。
於本實施例之製法中，該第一封裝件之製作步驟係包括：於一具有相對之第三表面與第四表面的承載板的第四表面上形成具有第一阻層開孔的第一阻層，形成該承載板之材質係為金屬板或導電材料；於該第一阻層開孔中形成第一線路；於該第一阻層與第一線路上形成具有第二阻層 開孔的第二阻層；於該第二阻層開孔中形成第二線路，該第一線路與第二線路係構成該層疊線路層；移除該第一阻層與第二阻層；形成包覆該第一線路與第二線路且外露該第二線路的該介電層；形成貫穿該承載板的承載板開孔，並使剩餘該承載板構成該等金屬柱；於該介電層的第一表面上接置電性連接該層疊線路層的該半導體晶片；於該介電層的第一表面上形成包覆該半導體晶片與金屬柱的該封裝膠體；以及形成複數對應外露該金屬柱之頂端的該封裝膠體開孔。
所述之層疊式封裝結構之製法中，該第一封裝件之製作步驟係包括：於一具有相對之第三表面與第四表面的承載板中形成複數貫穿之承載板通孔，形成該承載板之材質係為金屬板或導電材料；於各該承載板通孔中形成該金屬柱；於該承載板之第四表面上形成具有第一阻層開孔的第一阻層；於該第一阻層開孔中形成第一線路；於該第一阻層與第一線路上形成具有第二阻層開孔的第二阻層；於該第二阻層開孔中形成第二線路，該第一線路與第二線路係構成該層疊線路層；移除該第一阻層與第二阻層；形成包覆該第一線路與第二線路且外露該第二線路的該介電層；移除該承載板，並留下該等金屬柱；於該介電層的第一表面上接置電性連接該層疊線路層的該半導體晶片；於該介電層的第一表面上形成包覆該半導體晶片與金屬柱的該封裝膠體；以及形成複數對應外露該金屬柱之頂端的該封裝膠體開孔。
於本發明之製法中，形成該封裝膠體開孔之方式係以雷射燒灼該封裝膠體，且該第二封裝件復包括用以對應連接該金屬柱之頂端的導電元件。
依前所述之製法，該導電元件係為銲球，且於提供該第一封裝件之後，復包括對該第一封裝件進行切單步驟。
本發明復提供一種層疊式封裝結構，係包括：第一封裝件，其係包括：介電層，係具有相對之第一表面與第二表面；層疊線路層，係嵌埋於該介電層中，且外露於該第一表面與第二表面；複數金屬柱，係設於該介電層的第一表面上，且電性連接該層疊線路層；半導體晶片，係接置於該介電層的第一表面上，且電性連接該層疊線路層；及封裝膠體，係形成於該介電層的第一表面上，並包覆該半導體晶片與金屬柱，且具有複數對應外露該金屬柱之頂端的封裝膠體開孔；以及第二封裝件，係接置於該封裝膠體上，且電性連接該等金屬柱。
於本實施例之層疊式封裝結構中，該第二封裝件復包括用以對應連接該金屬柱之頂端的導電元件，且該導電元件係為銲球。
由上可知，本發明係於第一封裝件上形成有複數金屬柱，並於接置晶片與包覆封裝膠體後，形成外露該金屬柱之頂端的封裝膠體開孔，由於本發明之封裝膠體開孔的深度較淺，故可有效減少製程時間，增進產能。
11‧‧‧底封裝件
111、26‧‧‧封裝膠體
1110‧‧‧封裝膠體開孔
112‧‧‧電性連接墊
113、31‧‧‧導電元件
12‧‧‧頂封裝件
121、27‧‧‧銲球
20、40‧‧‧承載板
200‧‧‧承載板開孔
201、41‧‧‧金屬柱
202‧‧‧支撐部
20a、40a‧‧‧第三表面
20b、40b‧‧‧第四表面
21‧‧‧第一阻層
210‧‧‧第一阻層開孔
22a‧‧‧第一線路
22b‧‧‧第二線路
22‧‧‧層疊線路層
23‧‧‧第二阻層
230‧‧‧第二阻層開孔
24‧‧‧介電層
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧半導體晶片
260‧‧‧封裝膠體開孔
2‧‧‧第一封裝件
3‧‧‧第二封裝件
400‧‧‧承載板通孔
第1圖所示者係習知之層疊式封裝結構的剖視圖； 第2A至2N圖所示者係本發明之層疊式封裝結構及其製法的剖視圖；以及第3A至3G圖所示者係本發明之層疊式封裝結構之第一封裝件的另一製法的剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「頂端」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
第2A至2N圖所示者，係本發明之層疊式封裝結構及其製法的剖視圖。
如第2A圖所示，提供一具有相對之第三表面20a與第四表面20b的承載板20，形成該承載板20之材質可為 金屬板或其他導電材質，於一較佳實施例中，形成該承載板20之材質係為鐵或冷軋鋼卷(Steel-Plate-ColdRolled-Coil，SPCC)。
如第2B圖所示，於該承載板20的第四表面20b上形成具有第一阻層開孔210的第一阻層21。
如第2C圖所示，於該第一阻層開孔210中形成第一線路22a。
如第2D圖所示，於該第一阻層21與第一線路22a上形成具有第二阻層開孔230的第二阻層23。
如第2E圖所示，於該第二阻層開孔230中形成第二線路22b，該第一線路22a與第二線路22b係構成層疊線路層22。
如第2F圖所示，移除該第一阻層21與第二阻層23。
如第2G圖所示，形成包覆該第一線路22a與第二線路22b的介電層24。
如第2H圖所示，移除部分厚度之該介電層24，該介電層24係具有相對之第一表面24a與第二表面24b，使該第二線路22b外露於該介電層24之第二表面24b，且移除該介電層24之方式可為研磨。
如第2I圖所示，形成貫穿該承載板20的承載板開孔200，並使剩餘該承載板20構成複數金屬柱201及用以維持整體剛性的支撐部202，形成該承載板開孔200之方式可為蝕刻，惟此係所屬技術領域具有通常知識者依據本說明書所能瞭解，故不在此贅述。
如第2J圖所示，於該介電層24的第一表面24a上接置電性連接該層疊線路層22的半導體晶片25。
如第2K圖所示，於該介電層24的第一表面24a上形成包覆該半導體晶片25、金屬柱201與支撐部202的封裝膠體26。
如第2L圖所示，以雷射燒灼方式形成複數對應外露該金屬柱201之頂端的封裝膠體開孔260，並於該介電層24之第二表面24b接置複數銲球27。
如第2M圖所示，進行切單步驟，並移除該支撐部202，至此即完成一第一封裝件2。
如第2N圖所示，於該封裝膠體26上接置第二封裝件3，該第二封裝件3係包括用以對應連接該金屬柱201之頂端的導電元件31，該導電元件31係例如為銲球，使該第二封裝件3電性連接該等金屬柱201。
第二實施例
第3A至3G圖所示者，係本發明之層疊式封裝結構之第一封裝件的另一製法的剖視圖。
如第3A圖所示，於一具有相對之第三表面40a與第四表面40b的承載板40中形成複數貫穿之承載板通孔400，形成該承載板40之材質可為金屬板或其他導電材質，於較佳實施例中，形成該承載板40之材質係為鐵或冷軋鋼卷(Steel-Plate-ColdRolled-Coil，SPCC)。
如第3B圖所示，於各該承載板通孔400中形成金屬柱41。
如第3C圖所示，於該承載板40之第四表面40b上形成具有第一阻層開孔210的第一阻層21，於該第一阻層開孔210中形成第一線路22a。
如第3D圖所示，於該第一阻層21與第一線路22a上形成具有第二阻層開孔230的第二阻層23，於該第二阻層開孔230中形成第二線路22b，該第一線路22a與第二線路22b係構成層疊線路層22。
如第3E圖所示，移除該第一阻層21與第二阻層23。
如第3F圖所示，形成包覆該第一線路22a與第二線路22b且外露該第二線路22b的介電層24。
如第3G圖所示，移除該承載板40，並留下該等金屬柱41。後續可再進行如第2J至2N圖之步驟，在此將不再贅述。
本發明復提供一種層疊式封裝結構，係包括：第一封裝件2，其係包括：介電層24，係具有相對之第一表面24a與第二表面24b；層疊線路層22，係嵌埋於該介電層24中，且外露於該第一表面24a與第二表面24b；複數金屬柱201，係設於該介電層24的第一表面24a上，且電性連接該層疊線路層22；半導體晶片25，係接置於該介電層24的第一表面24a上，且電性連接該層疊線路層22；及封裝膠體26，係形成於該介電層24的第一表面24a上，並包覆該半導體晶片25與金屬柱201，且具有複數對應外露該金屬柱201之頂端的封裝膠體開孔260；以及第二封裝件3，係接置於該封裝膠體26上，且電性連接該等金屬柱201。
於本實施例之層疊式封裝結構中，該第二封裝件3復包括用以對應連接該金屬柱201之頂端的導電元件31，該導電元件31係為銲球。
要補充說明的是，於該層疊線路層22之外露表面上復可形成有表面處理層(例如鎳/金)(未圖示)或有機保焊劑(Organic Solderability Preservative，OSP)(未圖示)，惟此係所屬技術領域具有通常知識者依據本說明書所能瞭解，故不在此贅述。
綜上所述，相較於習知技術，本發明係於移除承載板時留下複數金屬柱，並於接置晶片與包覆封裝膠體後，形成外露該金屬柱之頂端的封裝膠體開孔，故可有效減少該封裝膠體開孔的深度，進而減少製程時間，增進產能；此外，本發明之電性連接第一封裝件與第二封裝件所需的導電元件較小，可降低橋接的風險，提高良率，且減少整體堆疊厚度；再者，本發明以層疊線路層取代習知的封裝基板，故能薄化整體封裝件的厚度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧第一封裝件
201‧‧‧金屬柱
22a‧‧‧第一線路
22b‧‧‧第二線路
22‧‧‧層疊線路層
24‧‧‧介電層
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧半導體晶片
26‧‧‧封裝膠體
260‧‧‧封裝膠體開孔
27‧‧‧銲球
3‧‧‧第二封裝件
31‧‧‧導電元件

Claims (11)

  1. 一種層疊式封裝結構之製法，係包括：提供第一封裝件，其係包括：介電層，係具有相對之第一表面與第二表面；層疊線路層，係嵌埋於該介電層中，且外露於該第一表面與第二表面；複數金屬柱，係設於該介電層的第一表面上，且電性連接該層疊線路層；半導體晶片，係接置於該介電層的第一表面上，且電性連接該層疊線路層；及封裝膠體，係形成於該介電層的第一表面上，並包覆該半導體晶片與金屬柱，且具有複數對應外露該金屬柱之頂端的封裝膠體開孔；以及於該封裝膠體上接置第二封裝件，使該第二封裝件電性連接該等金屬柱。
  2. 如申請專利範圍第1項所述之層疊式封裝結構之製法，其中，該第一封裝件之製作步驟係包括：於一具有相對之第三表面與第四表面的承載板的第四表面上形成具有第一阻層開孔的第一阻層；於該第一阻層開孔中形成第一線路；於該第一阻層與第一線路上形成具有第二阻層開孔的第二阻層；於該第二阻層開孔中形成第二線路，該第一線路與第二線路係構成該層疊線路層； 移除該第一阻層與第二阻層；形成包覆該第一線路與第二線路且外露該第二線路的該介電層；形成貫穿該承載板的承載板開孔，並使剩餘該承載板構成該等金屬柱；於該介電層的第一表面上接置電性連接該層疊線路層的該半導體晶片；於該介電層的第一表面上形成包覆該半導體晶片與金屬柱的該封裝膠體；以及形成複數對應外露該金屬柱之頂端的該封裝膠體開孔。
  3. 如申請專利範圍第1項所述之層疊式封裝結構之製法，其中，該第一封裝件之製作步驟係包括：於一具有相對之第三表面與第四表面的承載板中形成複數貫穿之承載板通孔；於各該承載板通孔中形成該金屬柱；於該承載板之第四表面上形成具有第一阻層開孔的第一阻層；於該第一阻層開孔中形成第一線路；於該第一阻層與第一線路上形成具有第二阻層開孔的第二阻層；於該第二阻層開孔中形成第二線路，該第一線路與第二線路係構成該層疊線路層；移除該第一阻層與第二阻層； 形成包覆該第一線路與第二線路且外露該第二線路的該介電層；移除該承載板，並留下該等金屬柱；於該介電層的第一表面上接置電性連接該層疊線路層的該半導體晶片；於該介電層的第一表面上形成包覆該半導體晶片與金屬柱的該封裝膠體；以及形成複數對應外露該金屬柱之頂端的該封裝膠體開孔。
  4. 如申請專利範圍第2或3項所述之層疊式封裝結構之製法，其中，形成該承載板之材質係為金屬板或導電材料。
  5. 如申請專利範圍第2或3項所述之層疊式封裝結構之製法，其中，形成該封裝膠體開孔之方式係以雷射燒灼該封裝膠體。
  6. 如申請專利範圍第1項所述之層疊式封裝結構之製法，其中，該第二封裝件復包括用以對應連接該金屬柱之頂端的導電元件。
  7. 如申請專利範圍第6項所述之層疊式封裝結構之製法，其中，該導電元件係為銲球。
  8. 如申請專利範圍第1項所述之層疊式封裝結構之製法，其中，於提供該第一封裝件之後，復包括對該第一封裝件進行切單步驟。
  9. 一種層疊式封裝結構，係包括： 第一封裝件，其係包括：介電層，係具有相對之第一表面與第二表面；層疊線路層，係嵌埋於該介電層中，且外露於該第一表面與第二表面；複數金屬柱，係設於該介電層的第一表面上，且電性連接該層疊線路層；半導體晶片，係接置於該介電層的第一表面上，且電性連接該層疊線路層；及封裝膠體，係形成於該介電層的第一表面上，並包覆該半導體晶片與金屬柱，且具有複數對應外露該金屬柱之頂端的封裝膠體開孔；以及第二封裝件，係接置於該封裝膠體上，且電性連接該等金屬柱。
  10. 如申請專利範圍第9項所述之層疊式封裝結構，其中，該第二封裝件復包括用以對應連接該金屬柱之頂端的導電元件。
  11. 如申請專利範圍第10項所述之層疊式封裝結構，其中，該導電元件係為銲球。
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