CN104733415A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN104733415A
CN104733415A CN201410012336.XA CN201410012336A CN104733415A CN 104733415 A CN104733415 A CN 104733415A CN 201410012336 A CN201410012336 A CN 201410012336A CN 104733415 A CN104733415 A CN 104733415A
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conductive
semiconductor package
particle
primer
building brick
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CN104733415B (zh
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李百渊
林畯棠
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：第一电子组件；多个导电组件，其形成于该第一电子组件的表面上；具有多个导电凸块的第二电子组件，藉由该多个导电凸块设置于该第一电子组件上，且该导电凸块对应电性连接至该导电组件；以及形成于该第二电子组件与第一电子组件间的底胶，以包覆该导电凸块及导电组件，其中，该底胶包括多个粒径介于0.1至1μm的导电颗粒及多个粒径介于1至10μm的绝缘颗粒，藉由该导电颗粒以避免第二电子组件与第一电子组件间电性连接不良的问题，而能提升整体半导体封装件的电气效能。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种能提升电气效能的半导体封装件。
背景技术
随着电子产业的蓬勃发展，许多高阶电子产品都逐渐朝往轻、薄、短、小等高集积度方向发展，集成电路的积集度的增加，芯片的封装技术也越来越多样化。
其中，覆晶接合技术(Flip Chip Interconnect Technology，简称FC)具有缩小芯片封装体积及缩短讯号传输路径等优点，目前已经广泛应用于芯片封装领域，例如应用于芯片尺寸封装(Chip ScalePackage,CSP)等等。
详言之，覆晶接合技术，是利用面数组的方式将多个焊垫配置于电子组件的表面上，并在该等焊垫上形成导电凸块，并以回焊的方式让电子组件上的多个导电凸块与承载件上的多个焊料分别对应接合，以使电子组件与承载件可透过这些导电凸块与这些焊料来相互电性与机械性连接。
应用覆晶接合技术接合的芯片尺寸封装的种类繁多，其中一种是直接在晶圆上完成封装的晶圆级芯片尺寸封装(WLCSP)。晶圆级芯片尺寸封装的特征在芯片表面上形成重分布层(ReDistribution Layer，RDL)，藉以将原先排列于电子组件四周的焊垫，以面数组的方式重新分布于电子组件的表面上，故可增加焊垫间的间距，可对应符合印刷电路板I/O数少、接点间距宽的需求。
此外，更以人工或自动化的方式，将焊料装配于上述的焊垫，使得电子组件得以藉由焊垫的焊料，而与印刷电路板上的接点相电性连接。
然而，在回焊的过程中，由于这些导电凸块会与这些焊料熔接，相邻的导电凸块或焊料因熔化而产生互相接触，导致产品良率不佳的问题，因此在芯片相邻的焊垫间须预留一定宽度或者减少焊料的用量，以避免在回焊之后相邻导电凸块桥接的缺点。
此外，由于电子组件与承载件之间可能因热膨胀系数不匹配而产生热应力，因此电子组件与承载件之间通常会填入一底胶(underfill)，使其包覆导电凸块及焊料，以避免导电凸块在长时间受到电子组件与承载件间的热应力的反复作用下，发生横向断裂的现象。
举例而言，如图1所示的现有半导体封装件1，包括：承载件10；具有多个导电凸块110的电子组件11，其设置并电性连接于该承载件10上；形成于多个该导电凸块110与承载件10间的焊料12，且多个该导电凸块110藉由焊料12电性与机械性连接该承载件10；以及底胶13，形成于该电子组件11与承载件10间，使多个该导电凸块110与焊料12嵌埋于其中。然而，近几年来，为了避免回焊后相邻凸块发生桥接的问题，除了增加电子组件的焊垫间的间距外，更减少了减少焊料的用量，使焊料12’与导电凸块110无法电性或机械性连接，而衍生出更严重的不沾锡(Non-wetting)的缺点。
此外，业界还研发出使用压迫异方性导电膜(AnisotropicConductive Film，ACF)的覆晶接合技术，该异方性导电膜包含以绝缘薄膜91包覆导电晶球92构成的复合颗粒9(如图1’所示)。覆晶接合时，以压迫异方性导电膜的方式使该复合颗粒9破裂，以露出导电晶球92，藉此进行导通，然而，压迫异方性导电膜的电阻较高、需于高压下固化、该复合颗粒的价格昂贵，且导电晶球92的大小若设计不良更可能发生桥接的问题品质不稳定，而导致生产成本相对的提高，遂难以普及至电子产业。
因此，如何提供在焊料较少的情况下能够避免发生不沾锡的缺失，又能有效避免桥接，更能防止导电凸块断裂的半导体封装件，实为业界迫切待开发的方向。
发明内容
鉴于上述现有技术的缺失，本发明的目的为提供一种半导体封装件及其制法，能提升整体半导体封装件的电气效能。
本发明的半导体封装件，包括：第一电子组件；形成于该第一电子组件的表面上的多个导电组件；第二电子组件，其具有多个导电凸块，以供该第二电子组件藉由该多个导电凸块设置于该第一电子组件上，且该导电凸块对应电性连接至该导电组件；以及形成于该第二电子组件与第一电子组件间的底胶，且该底胶包覆该导电凸块及导电组件，其中，该底胶包括：多个粒径介于0.1至1μm的导电颗粒；及多个粒径介于1至10μm的绝缘颗粒。
本发明还提供一种半导体封装件的制法，包括：将第二电子组件藉由多个导电凸块设置于该第一电子组件上的导电组件；以及填充底胶于该第二电子组件与第一电子组件之间，以包覆该导电凸块及导电组件，其中，该底胶包括：多个粒径介于0.1至1μm的导电颗粒；及多个粒径介于1至10μm的绝缘颗粒。
前述的半导体封装件及其制法中，该底胶中还包括聚合物，且以该底胶的总重量计，该聚合物的含量介于35至50重量%。
前述的半导体封装件中，当部分该导电凸块无法电性连接至该导电组件时，填充于部分该导电凸块与导电组件间的底胶中，该导电颗粒的含量大于该绝缘颗粒的含量。
于前述的半导体封装件的制法中，部分该导电凸块与其对应的该导电组件间具有间隙，故该底胶还填充于部分该导电凸块与其对应的该导电组件间，且于填充于部分该导电凸块与导电组件间的底胶中，该导电颗粒的含量大于该绝缘颗粒的含量。
于前述的半导体封装件的制法中，还包括于填充底胶于该第一电子组件与第二电子组件间后，以100至200℃烘烤该半导体封装件，并藉此使该导电凸块与导电组件的电位差改变，俾使该底胶中所含的导电颗粒趋向于部分该导电凸块与其对应的该导电组件间，达到提升部分该导电凸块与其对应的该导电组件间所填充的底胶中的导电颗粒的含量的效果。
于前述的半导体封装件及其制法中，该导电颗粒的尺寸小于该绝缘颗粒的尺寸。
于前述的半导体封装件及其制法中，以该底胶的总重量计，该导电颗粒的含量介于5至20重量%。
于前述的半导体封装件及其制法中，以该底胶的总重量计，该绝缘颗粒的含量介于45至60重量%。
于前述的半导体封装件及其制法中，以该底胶的总重量计，该聚合物的含量介于35至50重量%。
于前述的半导体封装件及其制法中，该导电凸块的材质为铜，且该导电组件的材质为锡/铅合金。
于前述的半导体封装件及其制法中，该第一电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
于前述的半导体封装件及其制法中，该第二电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
由上可知，本发明藉由于底胶中加入粒径小于绝缘颗粒的导电颗粒，因此，当该导电凸块与导电组件间机械性接合效果不佳时，得以藉由该导电颗粒使该导电凸块与导电组件电性连接。
此外，本发明更藉由烘烤该形成有底胶的半导体封装件，使该导电颗粒、导电凸块与导电组件产生电位差，使该导电颗粒相互吸引并朝导电凸块与导电组件间凝聚，更可降低该设置该导电凸块与导电组件间的底胶中所含的导电颗粒的电阻，进而提升整体导电效能。
附图说明
图1为显示现有半导体封装件的示意图；
图1’为显示异方性导电膜内的复合颗粒的剖面示意图；
图2A至图2C为显示本发明的半导体封装件的制法示意图；以及
图3A及图3B为本发明半导体封装件的制法的图2B至图2C步骤的局部放大示意图。
主要组件符号说明
具体实施方式
以下藉由特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。本发明也可藉由其它不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。本文用以界定数值范围的术语“介于”，包含该数值范围的上限及下限二临界值，并非仅限于该数值的中间范围，举例而言，本说明书所述多个粒径介于0.1至1μm的导电颗粒，是指该导电颗粒的粒径介于0.1至1μm，且包含0.1及1μm的粒径。同时，本说明书中所引用的如“上”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2C为显示本发明的半导体封装件的制法示意图。
如图2A所示，本发明半导体封装件的制法包括：将第二电子组件21藉由多个导电凸块210设置于表面上形成有多个导电组件22的第一电子组件20上。
于本发明中，该第二电子组件包括，但不限于半导体芯片、晶圆、经封装或未经封装的半导体组件。于本发明中，该第一电子组件包括，但不限于基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。于本实施例中，该导电凸块的材质可为铜，且该导电组件的材质可为锡/铅合金。
此外，于一实施例中，部分该导电组件22’未与该导电凸块210机械性连接。
如图2B所示，于该第二电子组件21与第一电子组件20间形成包覆该导电凸块210及导电组件22的底胶23，其中，该底胶23包括：多个粒径介于0.1至1μm的导电颗粒232；以及多个粒径介于1至10μm的绝缘颗粒231。
于本实施例中，以该底胶的总重量计，该导电颗粒的含量介于5至20重量%，该绝缘颗粒的含量介于45至60重量%。于本发明中，对于该底胶中的导电颗粒的材料并未有特殊限制，仅需为可导电的导电材料即可。
此外，于本实施例中，是由于部分该导电凸块210与其对应的该导电组件22’间发生不沾锡(Non-wetting)，因而部分该导电凸块210与其对应的该导电组件22’之间填充有该底胶23’。
如图2C所示，于形成该底胶23,23’后，以100至200℃烘烤，使该底胶23,23’固化，得到该半导体封装件2。
于本实施例中，经烘烤后填充于部分该导电凸块210与导电组件22’间的底胶23’中，该导电颗粒232的含量大于该绝缘颗粒231的含量。
请参阅图2C，本发明的半导体封装件2，包括第一电子组件20；多个导电组件22，其形成于该第一电子组件20的表面上；具有多个导电凸块210的第二电子组件21，其藉由该多个导电凸块210设置于该第一电子组件20上，且该导电凸块210对应电性连接至该导电组件22；以及形成于该第二电子组件21与第一电子组件20间，并包覆于该导电凸块210及导电组件22的底胶23，其中，该底胶23包括：多个粒径介于0.1至1μm的导电颗粒232；以及多个粒径介于1至10μm的绝缘颗粒231。
于本实施例中，该底胶中还包括聚合物，以该底胶的总重量计，该聚合物的含量介于35至50重量%，且该聚合物为胶材。于本实施例中，该聚合物为环氧树脂，又对于底胶所使用的聚合物的选择为本领域常用的技术手段，于此不再赘述。
更详而言，请参阅图3A至图3B，本发明半导体封装件的制法的图2B至图2C步骤的局部放大示意图。
如图3A所示，于填充底胶23’后，部分该导电凸块210与其对应的该导电组件22’间填充有该底胶23’，且该底胶23’中具有导电颗粒232。
于本实施例中，由于导电颗粒的粒径较小，因此可以经由点胶时随胶的流动进入部分导电凸块与导电组件间(即，不沾锡的空隙)，当该导电颗粒进入后就可以电性连接该部分导电凸块与导电组件，得以在半导体封装件发生不沾锡的缺失时，仍可具有较佳的电性连接效果。又，由于该绝缘颗粒231的尺寸较大，因此相较该导电颗粒232，该绝缘颗粒231较不易进入该导电凸块210与导电组件22’间的空隙中，因此虽于该底胶23中，该导电颗粒231与绝缘颗粒232均匀分布，然而在该导电凸块210与导电组件22’间的底胶23’中，该导电颗粒232的含量大于该绝缘颗粒231。
如图3B所示，以100至200℃烘烤该半导体封装件2后，该导电凸块210与导电组件22’间的底胶23’中，该导电颗粒232的含量大于该绝缘颗粒231。
于本实施例中，由于金属(如，导电凸块、导电组件及导电颗粒等)本身有电位上的差异，且经高温烘烤后，该些金属的电位差会因为温度上升而剧烈反应，进而产生正负极的极性，如图3B所示。
举例而言，于本实施例中，该导电凸块的材质为铜，该导电凸块经加热产生正极电压(+0.34V)，该导电组件的材质为锡/铅合金，经加热而产生负极电压(-0.138V)，使该导电凸块与导电组件间产生电位差，而产生局部的电场效应，进而吸引导电颗粒靠近，遂增加该导电凸块与导电组件间的空隙中的导电颗粒的含量。
此外，加热前由于进入空隙中的导电颗粒较少，因此在接触面积较小的情况下，虽可使该导电组件与导电凸块电性导通，却会有电阻较大的问题，而无法承受过大的电流。惟，藉由正负极的电流作用会带来局部的电场效应，而吸引在空隙周围的导电颗粒进入空隙中，与原本就填入的少量导电颗粒因磁场吸引而集结，而增加导电颗粒与导电组件间的导电效能，进而降低该导电颗粒与导电组件的电阻，因此在底胶固化后使原本不沾锡的缺失迎刃而解。
于本发明的半导体封装件及其制法中，使用具有特定粒径范围的导电颗粒与绝缘颗粒的所组成的底胶，藉由金属的电位差产生磁场吸引导电颗粒凝聚，得以在发生不沾锡缺失时，仍可维持原有的导电特性，且仅需于使用一般回焊制程即可完成，不需额外繁杂的工序，即可在焊料较少的情况下，不仅不需要使用昂贵且工序繁杂的ACF的覆晶接合方式，即能克服因不沾锡而导致的断路缺失，又能有效避免桥接，更能防止导电凸块断裂。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (21)

1.一种半导体封装件，包括：
第一电子组件；
多个导电组件，其形成于该第一电子组件的表面上；
第二电子组件，其具有多个导电凸块，以供该第二电子组件藉由该多个导电凸块设置于该第一电子组件上，且该导电凸块对应电性连接至该导电组件；以及
底胶，其形成于该第二电子组件与第一电子组件间，并包覆该导电凸块及导电组件，其中，该底胶包括：
多个粒径介于0.1至1μm的导电颗粒；
多个粒径介于1至10μm的绝缘颗粒；及
聚合物。
2.根据权利要求1所述的半导体封装件，其特征在于，该导电颗粒的尺寸小于该绝缘颗粒的尺寸。
3.根据权利要求1所述的半导体封装件，其特征在于，以该底胶的总重量计，该导电颗粒的含量介于5至20重量%。
4.根据权利要求1所述的半导体封装件，其特征在于，以该底胶的总重量计，该绝缘颗粒的含量介于45至60重量%。
5.根据权利要求1所述的半导体封装件，其特征在于，以该底胶的总重量计，该聚合物的含量介于35至50重量%。
6.根据权利要求1所述的半导体封装件，其特征在于，当部分该导电凸块无法电性连接至该导电组件时，填充于该导电凸块与导电组件间的底胶中，该导电颗粒的含量大于该绝缘颗粒的含量。
7.根据权利要求1所述的半导体封装件，其特征在于，该导电凸块的材质为铜。
8.根据权利要求1所述的半导体封装件，其特征在于，该导电组件的材质为锡/铅合金。
9.根据权利要求1所述的半导体封装件，其特征在于，该第一电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
10.根据权利要求1所述的半导体封装件，其特征在于，该第二电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
11.一种半导体封装件的制法，包括：
将第二电子组件藉由多个导电凸块设置于该第一电子组件上的导电组件；以及
填充底胶于该第二电子组件与第一电子组件之间，以包覆该导电凸块及导电组件，其中，该底胶包括：
多个粒径介于0.1至1μm的导电颗粒；
多个粒径介于1至10μm的绝缘颗粒；以及
聚合物。
12.根据权利要求11所述的半导体封装件的制法，其特征在于，该导电颗粒的尺寸小于该绝缘颗粒的尺寸。
13.根据权利要求11所述的半导体封装件的制法，其特征在于，以该底胶的总重量计，该导电颗粒的含量介于5至20重量%。
14.根据权利要求11所述的半导体封装件的制法，其特征在于，以该底胶的总重量计，该绝缘颗粒的含量介于45至60重量%。
15.根据权利要求11所述的半导体封装件的制法，其特征在于，以该底胶的总重量计，该聚合物的含量介于35至50重量%。
16.根据权利要求11所述的半导体封装件的制法，其特征在于，该底胶还填充于部分该导电凸块与其对应的该导电组件间，且于填充于部分该导电凸块与导电组件间的底胶中，该导电颗粒的含量大于该绝缘颗粒的含量。
17.根据权利要求16所述的半导体封装件的制法，其特征在于，该制法还包括于填充该底胶于该第一电子组件与第二电子组件间后，以100至200℃烘烤该半导体封装件。
18.根据权利要求11所述的半导体封装件的制法，其特征在于，该导电凸块的材质为铜。
19.根据权利要求11所述的半导体封装件的制法，其特征在于，该导电组件的材质为锡/铅合金。
20.根据权利要求11所述的半导体封装件的制法，其特征在于，该第一电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
21.根据权利要求11所述的半导体封装件的制法，其特征在于，该第二电子组件为基板、半导体芯片、晶圆、经封装或未经封装的半导体组件。
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