CN101904230B - 焊料球的无助熔剂微穿孔方法和所得的装置 - Google Patents

焊料球的无助熔剂微穿孔方法和所得的装置 Download PDF

Info

Publication number
CN101904230B
CN101904230B CN200880121032.XA CN200880121032A CN101904230B CN 101904230 B CN101904230 B CN 101904230B CN 200880121032 A CN200880121032 A CN 200880121032A CN 101904230 B CN101904230 B CN 101904230B
Authority
CN
China
Prior art keywords
solder ball
integrated structure
perforation
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200880121032.XA
Other languages
English (en)
Other versions
CN101904230A (zh
Inventor
李德庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN101904230A publication Critical patent/CN101904230A/zh
Application granted granted Critical
Publication of CN101904230B publication Critical patent/CN101904230B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114Guiding structures outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81208Compression bonding applying unidirectional static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20105Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20106Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0315Oxidising metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0369Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

本发明揭示一种方法,其包括:在衬底上方形成导电材料层;在所述导电材料层上方形成掩蔽层;在所述掩蔽层处于适当位置的情况下在所述导电材料层上执行第一蚀刻工艺;移除所述掩蔽层;以及在移除所述掩蔽层之后,在所述导电材料层上执行各向同性蚀刻工艺,借此界定位于所述衬底上的多个穿孔结合结构。

Description

焊料球的无助熔剂微穿孔方法和所得的装置
技术领域
本标的物大体上针对微电子装置的领域,且更特定来说,针对焊料球的无助熔剂微穿孔方法,和所得的装置。
背景技术
使用板上芯片(Chip-on-board)和芯片上板(board-on-chip)(BOC)技术将半导体裸片附接到介入层(interposer)或其它载体衬底(例如印刷电路板(PCB))。可经由倒装芯片附接、线结合或卷带式自动结合(“TAB”)来实现附接。倒装芯片附接通常利用球状栅格阵列(ball grid array,BGA)技术。BGA组件(裸片)包括通常呈焊料球或凸块形式的以栅格图案布置在裸片的有效表面上的导电外部触点,其准许将裸片倒装芯片安装到介入层或其它载体衬底(例如,PCB)。
在倒装芯片附接中,BGA组件的球与载体衬底上的端子对准,且通过回流焊料球来连接。可用固化的导电聚合物替代焊料球。接着将电介质底填料(dielectric underfill)插入于倒装芯片裸片与载体物质的表面之间以嵌入焊料球且使BGA组件与载体衬底机械耦合。
线结合和TAB附接一般涉及以适当粘合剂(例如,环氧树脂)或带将裸片的后侧附接到载体衬底的表面。在线结合的情况下,使结合线附接到裸片上的每一结合衬垫且结合到载体衬底(例如,介入层)上的对应端子衬垫。在TAB的情况下,使柔性绝缘带(例如聚酰亚胺)上载有的金属引线的末端附接到裸片上的结合衬垫且附接到载体衬底上的端子衬垫。一般使用电介质(例如,硅或环氧树脂)来覆盖结合线或金属带引线以防止损坏。
倒装芯片附接已提供改进的电性能且允许较大的封装密度。然而,球状栅格阵列技术的发展已产生球被制成为较小且具有较紧密间距的阵列。随着球变得较小且较接近地置于一起,其引起关于倒装芯片裸片上的导电凸块与衬底或介入层上的结合衬垫的相互对准的问题。倒装芯片附接还可能导致高成本和处理难题。举例来说,要求倒装芯片安装工精确地对准裸片与介入层或衬底。
在倒装芯片封装中,固态熔接、粘合和焊接常用于接合互连系统。这些结合技术面临众多组装挑战。焊接由于其高组装良率、经由回流消除探测标记的能力、对在组装之后的返工的允许、电稳定性和由于自对准效应的在置放精确性上的高容限而为优选的结合技术。然而,对于焊接组装来说,仍存在一些挑战,例如较长的处理时间和为了可焊性而基于助熔剂来移除氧化物和烃的需要。举例来说,归因于用以在周围环境中制造焊料球的制造过程,焊料球通常具有在球的外表面上形成的氧化物层。
在制成到这些焊料球的导电连接的过程中,归因于氧化物层的存在而使用助熔剂,即,使用助熔剂来移除这些氧化物。处理时间由于助熔剂应用、精确对准所需的视觉时间和对用以提供足够润湿时间以便焊接的回流过程的需要而延长。氧化物的助熔剂移除留下对封装可靠性不利的不合需要的残余物。陷入的残余物还造成可导致过早接合失效的粗大(gross)焊接空隙。尽管氯氟碳化物(CFC)在移除助熔剂残余物方面为有效的,但其对环境造成危害且并不呈现长期的解决方案。因此,助熔剂的使用和其清洁过程对于在微电子系统、光电子系统和微机电系统的封装和整合中的倒装芯片部署设置障碍。另一方面,无助熔剂焊接过程依赖于受控气氛以还原氧化物以便焊接,但此在大量实施中是麻烦的。显然,高度需要用于倒装芯片组装的在环境气氛中进行即时无助熔剂焊接的方法。
本标的物针对可解决或至少减少上述问题中的一些或所有问题的各种方法和装置。
发明内容
本发明的一个方面涉及一种方法,其包含:在衬底上方形成导电材料层;在所述导电材料层上方形成掩蔽层;在所述掩蔽层处于适当位置的情况下在所述导电材料层上执行第一蚀刻工艺;移除所述掩蔽层;以及在移除所述掩蔽层之后,在所述导电材料层上执行各向同性蚀刻工艺,借此界定位于所述衬底上的多个穿孔结合结构。
本发明的另一方面涉及一种方法,其包含:提供具有多个焊料球的集成电路裸片,所述焊料球中的每一者具有在所述球的外表面上的氧化物层;执行加热工艺以加热至少所述焊料球;以及施加力,所述力致使衬底上的多个穿孔结合结构中的每一者将所述焊料球中的一者和其相关联的氧化物层穿孔,借此在所述焊料球与所述穿孔结合结构之间建立导电连接。
本发明的又一方面涉及一种装置,其包含:集成电路裸片,其具有导电地耦合到所述裸片上的结合衬垫的多个焊料球,所述焊料球中的每一者具有在其外表面上的氧化物层;以及衬底,其包含多个穿孔结合结构,其中所述穿孔结合结构中的每一者至少部分穿透且延伸到对应焊料球中,借此在所述焊料球与所述穿孔结合结构之间建立导电连接,且所述穿孔结合结构穿透所述氧化物层。
附图说明
可参考结合附图而进行的以下描述来理解本文中所揭示的标的物,附图中相同参考数字识别相同元件,且附图中:
图1A到图1D为本文中所述的说明性装置的各种视图;
图2A到图2B描绘可使用本文中揭示的穿孔结合结构而实现的减小的间距;
图3将本文中揭示的穿孔结合结构描绘为与不同尺寸的焊料球啮合;
图4描绘本文中揭示的穿孔结合结构的多种说明性末端配置;且
图5A到图5D描绘用于形成本文中揭示的穿孔结合结构的一个说明性工艺流程。
尽管本文中所述的标的物容易受到各种修改和替代形式,但其特定实施例已以实例方式展示于图式中且在本文中得到详细描述。然而应理解,特定实施例在本文中的描述并不意欲将本发明限于所揭示的特定形式,相反,意图为涵盖处于由所附权利要求书界定的本发明的精神和范围内的所有修改、等效物和替代物。
具体实施方式
下文描述本发明的标的物的说明性实施例。为了清楚起见,在本说明书中并未描述实际实施的所有特征。当然,应了解,在任何所述实际实施例的开发中,均必须作出众多实施特定决策以实现开发者的特定目标,例如,遵守将在各实施方案之间变化的系统相关和商业相关约束。另外,应了解,此开发努力可能为复杂且耗时的,但对于受益于本发明的所属领域的技术人员来说将仍然为例行任务。
尽管将图式中所示的各种区域和结构描绘为具有极精确的明确配置和轮廓,但所属领域的技术人员认识到,实际上,这些区域和结构并不如图式中所指示的一样精确。另外,与制成的装置上的那些特征或区域的尺寸相比,图式中所描绘的各种特征和掺杂区域的相对尺寸可能被夸示或缩减。然而,包括附图以描述且解释本文中所揭示的标的物的说明性实例。
图1A到图1B描绘根据本标的物的一个方面的装置10的说明性实施例。装置10包含附接到介入层或衬底14(例如,印刷电路板)的裸片12。术语“衬底”和“介入层”在本文中将可互换使用,且应将其理解为指代集成电路裸片可安装到的任何类型的结构。裸片12包含导电地耦合到导电衬垫17的多个示意性描绘的焊料球16。焊料球16具有归因于经执行以形成焊料球16的制造工艺而形成于其外表面上的说明性氧化物层20,例如,氧化锡。在衬底14上形成多个穿孔结合结构22。使穿孔结合结构22导电地耦合到延伸穿过形成于衬底14中的通孔26的说明性导线迹线或线24。导线路线24导电地耦合到形成于衬底14上的说明性接触衬垫28。还提供电介质材料层30以使衬底14上的各种电组件电隔离。在穿孔结合结构22上提供至少一个抗氧化膜23(参见图1C)。
图1A描绘在附接之前裸片12定位于最接近衬底14处的情况。可使用多种已知技术(例如,粘合剂、环氧树脂等)使裸片12耦合到衬底14。在所描绘的实例中,将一定量的非导电膏32定位于衬底14上。在一些应用中,可施加非导电膜来代替非导电膏32。
图1B描绘在制造时的装置10,其中已借助于在穿孔结合结构22与焊料球16之间的导电啮合,使裸片12导电地耦合到衬底14。穿孔结合结构22将氧化物层20和焊料球16穿孔以借此建立此导电连接。还请注意,图1B描绘需要时可用以确保裸片12定位于距衬底14一固定距离处的说明性孤立结构(standoff structure)34。
在将裸片12附接到衬底14的过程中,对装置10加热且施加说明性向下力40。向下力40的量值可视特定应用而变化。在一个说明性实施例中,向下力40可在约2kg到12kg的范围内。在一些特定应用中,可采用约8kg的向下力40。将装置10加热到焊料球16的材料的熔点以上的温度,例如,加热到在约190℃到210℃的范围内的温度。视特定应用而定,可施加向下力40并持续0.5秒到2秒的持续时间。标题为“在环境气氛中Au与Pb-Sn的即时无助熔剂结合(Instantaneous Fluxless Bonding of Au with Pb-SnSolder in Ambient Atmosphere)”(Journal of Applied Physics,第98卷,034904(2005))的文章在此以其全文引用的方式并入。
图1C到图1D为说明性焊料球16和穿孔结合结构22在啮合之前(图1C)和在啮合之后(图1D)的放大视图。如先前所提及,穿孔结合结构22具有在结构22上形成的一个或一个以上抗氧化层23以防止在穿孔结合结构22上形成氧化膜。在图1C到图1D中所描绘的说明性实例中,抗氧化层23包含金层23A和镍层23B。当然,可采用其它材料。金层23A可具有约2.5μm的厚度,而镍层23B可具有约0.3μm的厚度。
图2A到图2B示意性地描绘可通过使用本文中所揭示的穿孔结合结构22而产生的邻近导电结构之间的减小的间距。图2A示意性地描绘通常使用已知技术形成的说明性导电结合结构90。常规结合结构90具有实质上平面的上表面或接触表面92。在图2A中,将接触表面92的宽度指定为“A”,将倾斜侧壁94(归因于用以形成结构90的蚀刻工艺的各向同性的性质)的宽度指定为“B”,且将结构90之间的间隔指定为“C”。因此,导电结构90的间距“P”将为A+2B+C。相反地,在图2B中所示的穿孔结合结构22之间的间距(“P1”)将等于2B+C。简而言之,通过使用本文中所揭示的技术和穿孔结合结构22,导电结合结构(如本文中所揭示的穿孔结合结构22)之间的间距与采用具有实质上平面或非穿孔上表面92的结合结构的现有技术装置(如图2A中所示)相比可实质上较小。举例来说,通过使用本文中所述的穿孔结合结构22,间距“P1”最小可为约60μm。
如图3中所示,可与不同尺寸的焊料球16A、16B、16C一起采用本文中所揭示的方法和穿孔结合结构22。因此,可与多种不同连接技艺和技术一起采用本文中所述的穿孔结合结构22。
还可采用本标的物来控制裸片12与印刷电路板14之间的偏移。一般来说,在所有其它事物均相等的情况下,向下力40越大,裸片12与印刷电路板14之间的距离越小。还可采用啮合工艺期间的温度来控制裸片12与印刷电路板14之间的间隔。一般来说,温度越高,裸片12与印刷电路板14之间的间隔越小。
如图4中所示,穿孔结合结构22对于结构22的穿孔端22A来说可具有多种配置。举例来说,穿孔端22A可为尖的、圆的,或可包含多个尖峰,如在图4中的穿孔结合结构22上所描绘(从左向右)。
图5A到图5D描绘形成本文中所述的穿孔结合结构22的一个说明性工艺流程。如图5A中所示,最初在导电材料层82上方形成掩蔽层80。掩蔽层80可包含多种材料(例如,光致抗蚀剂材料),且其可通过使用传统光刻技术而形成。导电材料层80可包含多种不同材料(例如,金),且其可通过多种已知技术(例如,电镀)而形成。
如图5B中所示,执行各向异性蚀刻工艺84以部分界定具有倾斜侧壁87的导电结构86。蚀刻工艺84可在一时间点停止,以使得导电材料层80的一部分88未被完全蚀刻掉。在一些应用中,可能不需要停止蚀刻工艺84以便留下导电材料层82的剩余部分88。如图5C中所示,移除掩蔽层80,且执行各向同性蚀刻工艺89直到形成图5D中所描绘的穿孔结合结构22时为止。请注意,在本文中描绘的说明性实施例中,穿孔结合结构22具有实质上三角形的横截面配置和实质上尖的末端22A。穿孔结合结构22的末端22A一般是非平面的或非平坦的,但其可呈现其它配置。举例来说,图4描绘穿孔结合结构22的末端22A的各种说明性配置。
因为可以对受益于本文中的教示的所属领域的技术人员来说为显而易见的不同但等效的方式修改和实践本发明,所以上文所揭示的特定实施例仅为说明性的。举例来说,可以不同次序执行上文阐述的工艺步骤。另外,除了在所附权利要求书中所描述的之外,不希望限于本文中所示的构造或设计的细节。因此,显然可更改或修改上文所揭示的特定实施例且认为所有此类变化均在本发明的范围和精神内。因此,在本文中寻求的保护正如在所附权利要求书中所阐述。

Claims (22)

1.一种无助熔剂微穿孔方法,其包含:
在衬底上方形成导电材料层;
在所述导电材料层上方形成掩蔽层;
在所述掩蔽层处于适当位置的情况下在所述导电材料层上执行第一蚀刻工艺;
移除所述掩蔽层;
在移除所述掩蔽层之后,在所述导电材料层上执行各向同性蚀刻工艺,借此通过移除两个或更多个穿孔结合结构之间的所述导电材料层来至少部分地暴露所述衬底以界定位于所述衬底上的多个穿孔结合结构;以及
在衬底上设置非导电膏或非导电膜。
2.根据权利要求1所述的方法,其进一步包含:
提供具有多个焊料球的集成电路裸片,所述焊料球中的每一者具有在所述球的外表面上的氧化物层;
加热至少所述焊料球;以及
施加力,所述力致使具有至少一个抗氧化层的所述多个穿孔结合结构中的每一者将上面形成有所述氧化物层的所述焊料球中的一者穿孔,且借此在所述焊料球与所述穿孔结合结构之间建立导电连接。
3.根据权利要求2所述的方法,其中在周围含氧环境中执行在权利要求2中所述的步骤。
4.根据权利要求2所述的方法,其中加热至少所述焊料球包含将至少所述焊料球加热到高于所述焊料球的材料的熔点的温度。
5.根据权利要求2所述的方法,其中施加所述力包含施加在5Kg到12Kg的范围内的力并持续在0.5秒到2秒的范围内的持续时间。
6.根据权利要求2所述的方法,其中在不将助熔剂施加到所述多个焊料球的情况下执行在权利要求2中所述的步骤。
7.根据权利要求1所述的方法,其中所述第一蚀刻工艺为各向异性蚀刻工艺。
8.根据权利要求3所述的方法,其中所述衬底包含印刷电路板。
9.根据权利要求1所述的方法,其中所述多个穿孔结合结构中的每一者具有实质上三角形的横截面配置。
10.一种无助熔剂微穿孔方法,其包含:
提供具有多个焊料球的集成电路裸片,所述焊料球中的每一者具有在所述球的外表面上的氧化物层;
在具有多个穿孔结合结构的衬底上设置非导电膏或非导电膜;
执行加热工艺以加热至少所述焊料球;以及
施加力,所述力致使所述衬底上的所述穿孔结合结构将对应的焊料球和其相关联的氧化物层穿孔,借此在所述焊料球与所述穿孔结合结构之间建立导电连接,
其中所述穿孔结合结构具有至少一个抗氧化层。
11.根据权利要求10所述的方法,其中在周围含氧环境中执行在权利要求10中所述的步骤。
12.根据权利要求10所述的方法,其中执行所述加热工艺包含将至少所述焊料球加热到高于所述焊料球的材料的熔点的温度。
13.根据权利要求10所述的方法,其中施加所述力包含施加在5Kg到12Kg的范围内的力并持续在0.5秒到2秒的范围内的持续时间。
14.根据权利要求11所述的方法,其中在不将助熔剂施加到所述多个焊料球的情况下执行在权利要求10中所述的步骤。
15.根据权利要求12所述的方法,其中所述衬底包含印刷电路板。
16.根据权利要求13所述的方法,其中所述多个穿孔结合结构中的每一者具有实质上三角形的横截面配置。
17.一种用于附接半导体裸片的装置,其包含:
集成电路裸片,其具有导电地耦合到所述裸片上的结合衬垫的多个焊料球,所述焊料球中的每一者具有在其外表面上的氧化物层;
衬底,其包含具有至少一个抗氧化层的多个穿孔结合结构,所述穿孔结合结构中的每一者至少部分穿透且延伸到对应焊料球中,借此通过所述焊料球的再凝固在所述焊料球与所述穿孔结合结构之间建立永久的导电连接,所述穿孔结合结构穿透所述氧化物层;以及
在所述集成电路裸片和所述衬底之间的非导电膏或非导电膜。
18.根据权利要求17所述的装置,其中所述穿孔结合结构具有非平坦的末端。
19.根据权利要求17所述的装置,其中所述穿孔结合结构中的每一者包含形成于所述穿孔结合结构的外表面上的至少一个抗氧化层。
20.根据权利要求19所述的装置,其中所述至少一个抗氧化层包含多个材料层。
21.根据权利要求20所述的装置,其中所述多个层包含形成于所述穿孔结合结构的暴露表面上的含金层和形成于所述含金层上的含镍层。
22.根据权利要求17所述的装置,其中所述多个穿孔结合结构具有实质上三角形的横截面配置。
CN200880121032.XA 2007-12-18 2008-12-03 焊料球的无助熔剂微穿孔方法和所得的装置 Active CN101904230B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/958,842 US7749887B2 (en) 2007-12-18 2007-12-18 Methods of fluxless micro-piercing of solder balls, and resulting devices
US11/958,842 2007-12-18
PCT/US2008/085433 WO2009079214A1 (en) 2007-12-18 2008-12-03 Methods of fluxless micro-piercing of solder balls, and resulting devices

Publications (2)

Publication Number Publication Date
CN101904230A CN101904230A (zh) 2010-12-01
CN101904230B true CN101904230B (zh) 2015-07-29

Family

ID=40329135

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880121032.XA Active CN101904230B (zh) 2007-12-18 2008-12-03 焊料球的无助熔剂微穿孔方法和所得的装置

Country Status (6)

Country Link
US (5) US7749887B2 (zh)
EP (2) EP2232964B1 (zh)
KR (1) KR101156819B1 (zh)
CN (1) CN101904230B (zh)
TW (1) TWI487045B (zh)
WO (1) WO2009079214A1 (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749887B2 (en) * 2007-12-18 2010-07-06 Micron Technology, Inc. Methods of fluxless micro-piercing of solder balls, and resulting devices
US8424748B2 (en) * 2009-12-21 2013-04-23 Intel Corporation Solder in cavity interconnection technology
TW201208007A (en) * 2010-08-02 2012-02-16 Advanced Semiconductor Eng Semiconductor package
TWI542260B (zh) 2010-12-24 2016-07-11 Lg伊諾特股份有限公司 印刷電路板及其製造方法
DE102011000866A1 (de) * 2011-02-22 2012-08-23 Friedrich-Alexander-Universität Erlangen-Nürnberg Elektrisches Bauelement mit einer elektrischen Verbindungsanordnung und Verfahren zu dessen Herstellung
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US9064781B2 (en) * 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US20130234317A1 (en) * 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US9768137B2 (en) 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US20130301561A1 (en) * 2012-05-08 2013-11-14 Futurewei Technologies, Inc. System and Method for Antenna Port Association
US9779969B2 (en) 2014-03-13 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method
WO2016031067A1 (ja) * 2014-08-29 2016-03-03 千住金属工業株式会社 はんだ材料、はんだ継手及びはんだ材料の製造方法
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9576922B2 (en) * 2015-05-04 2017-02-21 Globalfoundries Inc. Silver alloying post-chip join
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
US11495560B2 (en) * 2015-08-10 2022-11-08 X Display Company Technology Limited Chiplets with connection posts
US10531575B2 (en) * 2016-04-01 2020-01-07 Intel Corporation Systems and methods for replaceable bail grid array (BGA) packages on board substrates
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
US11131689B2 (en) 2017-05-25 2021-09-28 International Business Machines Corporation Low-force wafer test probes
US10989735B2 (en) 2019-08-21 2021-04-27 Facebook Technologies, Llc Atomic force microscopy tips for interconnection
JP7316192B2 (ja) * 2019-10-29 2023-07-27 タイコエレクトロニクスジャパン合同会社 ソケット

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6613662B2 (en) * 1997-03-26 2003-09-02 Micron Technology, Inc. Method for making projected contact structures for engaging bumped semiconductor devices

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4483720A (en) * 1981-11-27 1984-11-20 S R I International Process for applying thermal barrier coatings to metals
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4912545A (en) * 1987-09-16 1990-03-27 Irvine Sensors Corporation Bonding of aligned conductive bumps on adjacent surfaces
US4865245A (en) * 1987-09-24 1989-09-12 Santa Barbara Research Center Oxide removal from metallic contact bumps formed on semiconductor devices to improve hybridization cold-welds
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same
US4989400A (en) * 1989-09-01 1991-02-05 Snapper Power Equipment, Division Of Fuqua Industries, Inc. Disposable bag and mounting apparatus for a lawn mower
US5878943A (en) * 1990-02-19 1999-03-09 Hitachi, Ltd. Method of fabricating an electronic circuit device and apparatus for performing the method
US5341980A (en) * 1990-02-19 1994-08-30 Hitachi, Ltd. Method of fabricating electronic circuit device and apparatus for performing the same method
US5207585A (en) * 1990-10-31 1993-05-04 International Business Machines Corporation Thin interface pellicle for dense arrays of electrical interconnects
US5326428A (en) * 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
DE4442960C1 (de) * 1994-12-02 1995-12-21 Fraunhofer Ges Forschung Lothöcker für die Flip-Chip-Montage und Verfahren zu dessen Herstellung
JP2830903B2 (ja) * 1995-07-21 1998-12-02 日本電気株式会社 半導体デバイスの製造方法
JPH09148693A (ja) * 1995-11-20 1997-06-06 Shinko Electric Ind Co Ltd フリップチップ実装用基板及びその製造方法
US5719440A (en) * 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
KR100197074B1 (ko) * 1996-04-30 1999-06-15 김춘호 칩형 소자의 실장 구조 및 그 방법
JPH1032223A (ja) * 1996-07-15 1998-02-03 Mitsubishi Electric Corp 半導体装置
US6179198B1 (en) * 1996-09-18 2001-01-30 Matsushita Electric Industrial Co., Ltd. Method of soldering bumped work by partially penetrating the oxide film covering the solder bumps
US5801452A (en) * 1996-10-25 1998-09-01 Micron Technology, Inc. Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
JP3553300B2 (ja) * 1996-12-02 2004-08-11 富士通株式会社 半導体装置の製造方法及び半導体装置の実装方法
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
JPH10303252A (ja) * 1997-04-28 1998-11-13 Nec Kansai Ltd 半導体装置
US5796163A (en) * 1997-05-23 1998-08-18 Amkor Technology, Inc. Solder ball joint
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6083773A (en) * 1997-09-16 2000-07-04 Micron Technology, Inc. Methods of forming flip chip bumps and related flip chip bump constructions
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
US6130148A (en) * 1997-12-12 2000-10-10 Farnworth; Warren M. Interconnect for semiconductor components and method of fabrication
US6140827A (en) * 1997-12-18 2000-10-31 Micron Technology, Inc. Method and apparatus for testing bumped die
KR100274991B1 (ko) * 1997-12-26 2001-01-15 윤종용 Csp와그실장방법및csp의전극돌기패턴형성용치공구
US6426636B1 (en) * 1998-02-11 2002-07-30 International Business Machines Corporation Wafer probe interface arrangement with nonresilient probe elements and support structure
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
JPH11312711A (ja) * 1998-04-30 1999-11-09 Murata Mfg Co Ltd 電子部品の接続方法
US6537854B1 (en) * 1999-05-24 2003-03-25 Industrial Technology Research Institute Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed
US6562545B1 (en) 1999-09-17 2003-05-13 Micron Technology, Inc. Method of making a socket assembly for use with a solder ball
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
US6529027B1 (en) * 2000-03-23 2003-03-04 Micron Technology, Inc. Interposer and methods for fabricating same
TW445612B (en) * 2000-08-03 2001-07-11 Siliconware Precision Industries Co Ltd Solder ball array structure to control the degree of collapsing
US6537482B1 (en) * 2000-08-08 2003-03-25 Micron Technology, Inc. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
US6641406B1 (en) * 2000-11-03 2003-11-04 Cray Inc. Flexible connector for high density circuit applications
US6795250B2 (en) * 2000-12-29 2004-09-21 Lenticlear Lenticular Lens, Inc. Lenticular lens array
SG99877A1 (en) * 2001-01-04 2003-11-27 Inst Materials Research & Eng Forming an electrical contact on an electronic component
JP2002222832A (ja) * 2001-01-29 2002-08-09 Nec Corp 半導体装置及び半導体素子の実装方法
JP2002344126A (ja) 2001-05-14 2002-11-29 Nec Corp プリント基板及びlsiチップの実装構造
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
JP4044769B2 (ja) * 2002-02-22 2008-02-06 富士通株式会社 半導体装置用基板及びその製造方法及び半導体パッケージ
SG115459A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
US6975035B2 (en) * 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
US6583517B1 (en) * 2002-04-09 2003-06-24 International Business Machines Corporation Method and structure for joining two substrates with a low melt solder joint
KR100597734B1 (ko) 2002-06-25 2006-07-07 삼성전자주식회사 메모리드라이브 및 그 제어방법
US6669173B1 (en) 2002-09-27 2003-12-30 James R. Dunn Dual purpose pneumatic floor covering device
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
JP2004265888A (ja) * 2003-01-16 2004-09-24 Sony Corp 半導体装置及びその製造方法
TWI233190B (en) 2003-02-11 2005-05-21 Via Tech Inc Structure of chip package and process thereof
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
TWI226689B (en) 2003-02-25 2005-01-11 Via Tech Inc Chip package and process for forming the same
KR20040078807A (ko) * 2003-03-05 2004-09-13 삼성전자주식회사 볼 그리드 어레이 적층 패키지
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
TW591780B (en) * 2003-03-21 2004-06-11 Univ Nat Central Flip chip Au bump structure and method of manufacturing the same
US20050120553A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Method for forming MEMS grid array connector
US7244125B2 (en) * 2003-12-08 2007-07-17 Neoconix, Inc. Connector for making electrical contact at semiconductor scales
JP4104490B2 (ja) * 2003-05-21 2008-06-18 オリンパス株式会社 半導体装置の製造方法
US6849944B2 (en) * 2003-05-30 2005-02-01 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
JP3994924B2 (ja) * 2003-06-02 2007-10-24 セイコーエプソン株式会社 回路基板の製造方法
KR100604334B1 (ko) 2003-11-25 2006-08-08 (주)케이나인 플립칩 패키징 공정에서 접합력이 향상된 플립칩 접합 방법
FR2876243B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant a protuberances conductrices ductiles enterrees et procede de connexion electrique entre ce composant et un composant muni de pointes conductrices dures
FR2876244B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant muni d'un ensemble de micropointes conductrices dures et procede de connexion electrique entre ce composant et un composant muni de protuberances conductrices ductiles
JP2006107854A (ja) 2004-10-04 2006-04-20 Nec Electronics Corp Icソケット
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP2008535225A (ja) * 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US7691675B2 (en) * 2005-10-24 2010-04-06 Hewlett-Packard Development Company, L.P. Encapsulating electrical connections
DE102006001254B4 (de) * 2005-11-30 2015-03-19 Globalfoundries Inc. Verfahren zur Herstellung von Lotkugeln mit einer stabilen Oxidschicht durch Steuern der Aufschmelzumgebung
US8067267B2 (en) 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US20080185705A1 (en) * 2005-12-23 2008-08-07 Tessera, Inc. Microelectronic packages and methods therefor
TWI282612B (en) * 2006-03-20 2007-06-11 Phoenix Prec Technology Corp Method for fabricating a metal protecting layer on electrically connecting pad of circuit board
US7674651B2 (en) * 2006-12-26 2010-03-09 International Business Machines Corporation Mounting method for semiconductor parts on circuit substrate
JP4431606B2 (ja) * 2007-10-05 2010-03-17 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造
US7749887B2 (en) 2007-12-18 2010-07-06 Micron Technology, Inc. Methods of fluxless micro-piercing of solder balls, and resulting devices
JP2009158593A (ja) * 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US7838954B2 (en) * 2008-01-16 2010-11-23 International Business Machines Corporation Semiconductor structure with solder bumps
US7863724B2 (en) * 2008-02-12 2011-01-04 International Business Machines Corporation Circuit substrate having post-fed die side power supply connections
KR100969412B1 (ko) * 2008-03-18 2010-07-14 삼성전기주식회사 다층 인쇄회로기판 및 그 제조방법
TWI405361B (zh) * 2008-12-31 2013-08-11 Ind Tech Res Inst 熱電元件及其製程、晶片堆疊結構及晶片封裝結構
US8922004B2 (en) * 2010-06-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump structures having sidewall protection layers
KR101736984B1 (ko) * 2010-09-16 2017-05-17 삼성전자 주식회사 벌집형 범프 패드를 갖는 반도체 패키지 기판용 인쇄회로기판 및 이를 포함하는 반도체 패키지
FR2971081B1 (fr) * 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue
US8288871B1 (en) * 2011-04-27 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Reduced-stress bump-on-trace (BOT) structures
US9200883B2 (en) * 2011-05-05 2015-12-01 International Business Machines Corporation Transferable probe tips
TWI576869B (zh) * 2014-01-24 2017-04-01 精材科技股份有限公司 被動元件結構及其製作方法
US10330701B2 (en) * 2014-02-22 2019-06-25 International Business Machines Corporation Test probe head for full wafer testing
US9070586B1 (en) * 2014-02-22 2015-06-30 International Business Machines Corporation Method of forming surface protrusions on an article and the article with the protrusions attached
KR102212827B1 (ko) * 2014-06-30 2021-02-08 엘지이노텍 주식회사 인쇄회로기판, 패키지 기판 및 이의 제조 방법
US9929230B2 (en) * 2016-03-11 2018-03-27 International Business Machines Corporation Air-core inductors and transformers
US10001508B2 (en) * 2016-06-17 2018-06-19 International Business Machines Corporation Integrated self-coining probe

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6613662B2 (en) * 1997-03-26 2003-09-02 Micron Technology, Inc. Method for making projected contact structures for engaging bumped semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Instantaneous fluxless bonding of Au with Pb–Sn solder in ambient;Teck Kheng Lee;《American Institute of Physics》;20050804;第98卷;参见第1页右栏第1段,第2页右栏第1段 *

Also Published As

Publication number Publication date
EP2232964B1 (en) 2018-08-01
WO2009079214A1 (en) 2009-06-25
US20100264541A1 (en) 2010-10-21
EP3410830A1 (en) 2018-12-05
US20090152719A1 (en) 2009-06-18
US7749887B2 (en) 2010-07-06
US10163840B2 (en) 2018-12-25
TW200937547A (en) 2009-09-01
US20130234328A1 (en) 2013-09-12
US10515918B2 (en) 2019-12-24
TWI487045B (zh) 2015-06-01
CN101904230A (zh) 2010-12-01
US8669173B2 (en) 2014-03-11
KR20100077049A (ko) 2010-07-06
US8436478B2 (en) 2013-05-07
KR101156819B1 (ko) 2012-06-18
US20150008577A1 (en) 2015-01-08
EP2232964A1 (en) 2010-09-29
US20190019774A1 (en) 2019-01-17

Similar Documents

Publication Publication Date Title
CN101904230B (zh) 焊料球的无助熔剂微穿孔方法和所得的装置
KR100336329B1 (ko) 반도체장치의제조방법
JP4502690B2 (ja) 実装基板
JP2008288489A (ja) チップ内蔵基板の製造方法
JP5272922B2 (ja) 半導体装置及びその製造方法
US20110100549A1 (en) Method for manufacturing component-embedded module
KR100629663B1 (ko) 반도체 장치 및 그 제조 방법
KR20020044577A (ko) 개선된 플립-칩 결합 패키지
JP5061668B2 (ja) 2種類の配線板を有するハイブリッド基板、それを有する電子装置、及び、ハイブリッド基板の製造方法
JP4835406B2 (ja) 実装構造体とその製造方法および半導体装置とその製造方法
WO2010070779A1 (ja) 異方性導電樹脂、基板接続構造及び電子機器
US8598692B2 (en) Semiconductor device and method for manufacturing same
US8168525B2 (en) Electronic part mounting board and method of mounting the same
JP5024009B2 (ja) 電子回路の実装方法及び実装構造
JP2006237367A (ja) プリント配線板
JP3450838B2 (ja) 電子部品の実装体の製造方法
JP4215685B2 (ja) 電子回路素子の製造方法
JP2008277594A (ja) 半導体装置、およびその製造方法、並びにその製造方法に用いるリードフレーム
JP2014216454A (ja) 電子装置の実装構造および電子装置の製造方法
JP2006005208A (ja) 半導体装置およびその実装方法
JP2007180593A (ja) 半導体装置の製造方法
JP2009021531A (ja) 電子回路素子およびその製造方法、並びに該電子回路素子を備えたデバイス
JP2005012239A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant