TWI508258B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI508258B
TWI508258B TW102147135A TW102147135A TWI508258B TW I508258 B TWI508258 B TW I508258B TW 102147135 A TW102147135 A TW 102147135A TW 102147135 A TW102147135 A TW 102147135A TW I508258 B TWI508258 B TW I508258B
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conductive
semiconductor package
electronic component
primer
particles
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TW102147135A
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TW201526199A (zh
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李百淵
林畯棠
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矽品精密工業股份有限公司
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Priority to TW102147135A priority Critical patent/TWI508258B/zh
Priority to CN201410012336.XA priority patent/CN104733415B/zh
Priority to US14/183,872 priority patent/US20150179597A1/en
Publication of TW201526199A publication Critical patent/TW201526199A/zh
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Publication of TWI508258B publication Critical patent/TWI508258B/zh

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種能提升電氣效能之半導體封裝件。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，積體電路之積集度的增加，晶片的封裝技術也越來越多樣化。
其中，覆晶接合技術(Flip Chip Interconnect Technology，簡稱FC)具有縮小晶片封裝體積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如應用於晶片尺寸封裝(Chip Scale Package,CSP)等等。
詳言之，覆晶接合技術，係利用面陣列的方式將複數個銲墊配置於電子元件之表面上，並在該等銲墊上形成導電凸塊，並以迴銲的方式讓電子元件上之複數導電凸塊與承載件上之多個銲料分別對應接合，以使電子元件與承載件可透過這些導電凸塊與這些銲料來相互電性與機械性連接。
應用覆晶接合技術接合之晶片尺寸封裝的種類繁多，其中一種是直接在晶圓上完成封裝的晶圓級晶片尺寸封裝(WLCSP)。晶 圓級晶片尺寸封裝的特徵係在晶片表面上形成重分佈層(ReDistribution Layer，RDL)，藉以將原先排列於電子元件四周的銲墊，以面陣列的方式重新分佈於電子元件之表面上，故可增加銲墊間的間距，可對應符合印刷電路板I/O數少、接點間距寬的需求。
此外，更以人工或自動化的方式，將銲料裝配於上述之銲墊，使得電子元件得以藉由銲墊的銲料，而與印刷電路板上的接點相電性連接。
然而，在迴銲的過程中，由於這些導電凸塊會與這些銲料熔接，相鄰的導電凸塊或銲料因熔化而產生互相接觸，導致產品良率不佳之問題，因此在晶片相鄰的銲墊間須預留一定寬度或者減少銲料之用量，以避免在迴銲之後相鄰導電凸塊橋接之缺點。
此外，由於電子元件與承載件之間可能因熱膨脹係數不匹配而產生熱應力，因此電子元件與承載件之間通常會填入一底膠(underfill)，使其包覆導電凸塊及銲料，以避免導電凸塊在長時間受到電子元件與承載件間之熱應力的反覆作用下，發生橫向斷裂的現象。
舉例而言，如第1圖所示之習知半導體封裝件1，係包括：承載件10；具有複數導電凸塊110之電子元件11，係設置並電性連接於該承載件10上；形成於複數該導電凸塊110與承載件10間之銲料12，且複數該導電凸塊110係藉由銲料12電性與機械性連接該承載件10；以及底膠13，形成於該電子元件11與承載件10間，使複數該導電凸塊110與銲料12嵌埋於其中。然而，近幾年來，為了避免迴銲後相鄰凸塊發生橋接之問題，除了增加電子 元件之銲墊間之間距外，更減少了減少銲料之用量，使銲料12’與導電凸塊110無法電性或機械性連接，而衍生出更嚴重的不沾錫(Non-wetting)的缺點。
此外，業界亦研發出使用壓迫異方性導電膜(Anisotropic Conductive Film，ACF)之覆晶接合技術，該異方性導電膜係包含以絕緣薄膜91包覆導電晶球92構成之複合顆粒9(如第1’圖所示)。覆晶接合時，以壓迫異方性導電膜之方式使該複合顆粒9破裂，以露出導電晶球92，藉此進行導通，然而，壓迫異方性導電膜之電阻較高、需於高壓下固化、該複合顆粒之價格昂貴，且導電晶球92的大小若設計不良更可能發生橋接之問題品質不穩定，而導致生產成本相對的提高，遂難以普及至電子產業。
因此，如何提供在銲料較少的情況下能夠避免發生不沾錫之缺失，又能有效避免橋接，更能防止導電凸塊斷裂之半導體封裝件，實為業界迫切待開發之方向。
鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：第一電子元件；形成於該第一電子元件之表面上之複數導電元件；第二電子元件，係具有複數導電凸塊，以供該第二電子元件藉由該複數導電凸塊設置於該第一電子元件上，且該導電凸塊係對應電性連接至該導電元件；以及形成於該第二電子元件與第一電子元件間之底膠，且該底膠係包覆該導電凸塊及導電元件，其中，該底膠係包括：複數粒徑介於0.1至1μm之導電顆粒；及複數粒徑介於1至10μm之絕緣顆粒。
本發明復提供一種半導體封裝件之製法，係包括：將第二電 子元件藉由複數導電凸塊設置於該第一電子元件上之導電元件；以及填充底膠於該第二電子元件與第一電子元件之間，以包覆該導電凸塊及導電元件，其中，該底膠係包括：複數粒徑介於0.1至1μm之導電顆粒；及複數粒徑介於1至10μm之絕緣顆粒。
前述之半導體封裝件及其製法中，該底膠中復包括聚合物，且以該底膠之總重量計，該聚合物之含量係介於35至50重量%。
前述之半導體封裝件中，當部分該導電凸塊無法電性連接至該導電元件時，填充於部分該導電凸塊與導電元件間之底膠中，該導電顆粒之含量係大於該絕緣顆粒之含量。
於前述之半導體封裝件之製法中，部分該導電凸塊與其對應之該導電元件間具有間隙，故該底膠復填充於部分該導電凸塊與其對應之該導電元件間，且於填充於部分該導電凸塊與導電元件間之底膠中，該導電顆粒之含量係大於該絕緣顆粒之含量。
於前述之半導體封裝件之製法中，復包括於填充底膠於該第一電子元件與第二電子元件間後，以100至200℃烘烤該半導體封裝件，並藉此使該導電凸塊與導電元件之電位差改變，俾使該底膠中所含之導電顆粒趨向於部分該導電凸塊與其對應之該導電元件間，達到提升部分該導電凸塊與其對應之該導電元件間所填充之底膠中的導電顆粒之含量之效果。
於前述之半導體封裝件及其製法中，該導電顆粒之尺寸係小於該絕緣顆粒之尺寸。
於前述之半導體封裝件及其製法中，以該底膠之總重量計，該導電顆粒之含量係介於5至20重量%。
於前述之半導體封裝件及其製法中，以該底膠之總重量計， 該絕緣顆粒之含量係介於45至60重量%。
於前述之半導體封裝件及其製法中，以該底膠之總重量計，該聚合物之含量係介於35至50重量%。
於前述之半導體封裝件及其製法中，該導電凸塊之材質為銅，且該導電元件之材質為錫/鉛合金。
於前述之半導體封裝件及其製法中，該第一電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
於前述之半導體封裝件及其製法中，該第二電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
由上可知，本發明係藉由於底膠中加入粒徑小於絕緣顆粒之導電顆粒，因此，當該導電凸塊與導電元件間機械性接合效果不佳時，得以藉由該導電顆粒使該導電凸塊與導電元件電性連接。
此外，本發明更藉由烘烤該形成有底膠之半導體封裝件，使該導電顆粒、導電凸塊與導電元件產生電位差，使該導電顆粒相互吸引並朝導電凸塊與導電元件間凝聚，更可降低該設置該導電凸塊與導電元件間之底膠中所含之導電顆粒之電阻，進而提升整體導電效能。
1、2‧‧‧半導體封裝件
10‧‧‧承載件
11‧‧‧電子元件
110、210‧‧‧導電凸塊
12、12’‧‧‧銲料
13、23、23’‧‧‧底膠
20‧‧‧第一電子元件
21‧‧‧第二電子元件
22、22’‧‧‧導電元件
231‧‧‧絕緣顆粒
232‧‧‧導電顆粒
9‧‧‧複合顆粒
91‧‧‧絕緣薄膜
92‧‧‧導電晶球
第1圖係顯示習知半導體封裝件之示意圖；第1’圖係顯示異方性導電膜內之複合顆粒的剖面示意圖；第2A至2C圖係顯示本發明之半導體封裝件之製法示意圖；以及第3A及3B圖係本發明半導體封裝件之製法的第2B至2C圖步驟之局部放大示意圖。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。本文用以界定數值範圍之術語「介於」，係包含該數值範圍的上限及下限二臨界值，並非僅限於該數值之中間範圍，舉例而言，本說明書所述複數粒徑介於0.1至1μm之導電顆粒，係意指該導電顆粒的粒徑介於0.1至1μm，且包含0.1及1μm之粒徑。同時，本說明書中所引用之如「上」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
請參閱第2A至2C圖係顯示本發明之半導體封裝件之製法示意圖。
如第2A圖所示，本發明半導體封裝件之製法係包括：將第二電子元件21藉由複數導電凸塊210設置於表面上形成有複數導電元件22之第一電子元件20上。
於本發明中，該第二電子元件係包括，但不限於半導體晶片、晶圓、經封裝或未經封裝之半導體元件。於本發明中，該第一電子元件係包括，但不限於基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。於本實施例中，該導電凸塊之材質可為銅，且該導電元件之材質可為錫/鉛合金。
此外，於一實施例中，部分該導電元件22’未與該導電凸塊210機械性連接。
如第2B圖所示，於該第二電子元件21與第一電子元件20間形成包覆該導電凸塊210及導電元件22之底膠23，其中，該底膠23係包括：複數粒徑介於0.1至1μm之導電顆粒232；以及複數粒徑介於1至10μm之絕緣顆粒231。
於本實施例中，以該底膠之總重量計，該導電顆粒之含量係介於5至20重量%，該絕緣顆粒之含量係介於45至60重量%。於本發明中，對於該底膠中之導電顆粒之材料並未有特殊限制，僅需為可導電之導電材料即可。
此外，於本實施例中，係由於部分該導電凸塊210與其對應之該導電元件22’間發生不沾錫(Non-wetting)，因而部分該導電凸塊210與其對應之該導電元件22’之間填充有該底膠23’。
如第2C圖所示，於形成該底膠23,23’後，以100至200℃烘烤，使該底膠23,23’固化，得到該半導體封裝件2。
於本實施例中，經烘烤後填充於部分該導電凸塊210與導電元件22’間之底膠23’中，該導電顆粒232之含量係大於該絕緣顆粒231之含量。
請參閱第2C圖，本發明之半導體封裝件2，係包括第一電子 元件20；複數導電元件22，係形成於該第一電子元件20之表面上；具有複數導電凸塊210之第二電子元件21，係藉由該複數導電凸塊210設置於該第一電子元件20上，且該導電凸塊210係對應電性連接至該導電元件22；以及形成於該第二電子元件21與第一電子元件20間，並包覆於該導電凸塊210及導電元件22之底膠23，其中，該底膠23係包括：複數粒徑介於0.1至1μm之導電顆粒232；以及複數粒徑介於1至10μm之絕緣顆粒231。
於本實施例中，該底膠中復包括聚合物，以該底膠之總重量計，該聚合物之含量係介於35至50重量%，且該聚合物為膠材。於本實施例中，該聚合物為環氧樹脂，又對於底膠所使用的聚合物之選擇為本領域常用之技術手段，於此不再贅述。
更詳而言，請參閱第3A至3B圖，本發明半導體封裝件之製法的第2B至2C圖步驟之局部放大示意圖。
如第3A圖所示，於填充底膠23’後，部分該導電凸塊210與其對應之該導電元件22’間填充有該底膠23’，且該底膠23’中具有導電顆粒232。
於本實施例中，由於導電顆粒之粒徑較小，因此可以經由點膠時隨膠的流動進入部分導電凸塊與導電元件間(即，不沾錫的空隙)，當該導電顆粒進入後就可以電性連接該部分導電凸塊與導電元件，得以在半導體封裝件發生不沾錫之缺失時，仍可具有較佳的電性連接效果。又，由於該絕緣顆粒231之尺寸較大，因此相較該導電顆粒232，該絕緣顆粒231較不易進入該導電凸塊210與導電元件22’間之空隙中，因此雖於該底膠23中，該導電顆粒231與絕緣顆粒232係均勻分布，然而在該導電凸塊210與導 電元件22’間之底膠23’中，該導電顆粒232之含量係大於該絕緣顆粒231。
如第3B圖所示，以100至200℃烘烤該半導體封裝件2後，該導電凸塊210與導電元件22’間之底膠23’中，該導電顆粒232之含量係大於該絕緣顆粒231。
於本實施例中，由於金屬(如，導電凸塊、導電元件及導電顆粒等)本身有電位上的差異，且經高溫烘烤後，該些金屬的電位差會因為溫度上升而劇烈反應，進而產生正負極的極性，如第3B圖所示。
舉例而言，於本實施例中，該導電凸塊之材質為銅，該導電凸塊經加熱產生正極電壓(+0.34V)，該導電元件之材質為錫/鉛合金，經加熱而產生負極電壓(-0.138V)，使該導電凸塊與導電元件間產生電位差，而產生局部的電場效應，進而吸引導電顆粒靠近，遂增加該導電凸塊與導電元件間之空隙中之導電顆粒的含量。
再者，加熱前由於進入空隙中的導電顆粒較少，因此在接觸面積較小之情況下，雖可使該導電元件與導電凸塊電性導通，卻會有電阻較大之問題，而無法承受過大的電流。惟，藉由正負極的電流作用會帶來局部的電場效應，而吸引在空隙周圍的導電顆粒進入空隙中，與原本就填入的少量導電顆粒因磁場吸引而集結，而增加導電顆粒與導電元件間之導電效能，進而降低該導電顆粒與導電元件之電阻，因此在底膠固化後使原本不沾錫的缺失迎刃而解。
於本發明之半導體封裝件及其製法中，使用具有特定粒徑範圍之導電顆粒與絕緣顆粒之所組成之底膠，藉由金屬之電位差產 生磁場吸引導電顆粒凝聚，得以在發生不沾錫缺失時，仍可維持原有的導電特性，且僅需於使用一般迴銲製程即可完成，不需額外繁雜的工序，即可在銲料較少的情況下，不僅不需要使用昂貴且工序繁雜的ACF之覆晶接合方式，即能克服因不沾錫而導致的斷路缺失，又能有效避免橋接，更能防止導電凸塊斷裂。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧第一電子元件
21‧‧‧第二電子元件
210‧‧‧導電凸塊
22、22’‧‧‧導電元件
23、23’‧‧‧底膠
231‧‧‧絕緣顆粒
232‧‧‧導電顆粒

Claims (21)

  1. 一種半導體封裝件，係包括：第一電子元件；複數導電元件，係形成於該第一電子元件之表面上；第二電子元件，係具有複數導電凸塊，以供該第二電子元件藉由該複數導電凸塊設置於該第一電子元件上，且該導電凸塊係對應電性連接至該導電元件；以及底膠，係形成於該第二電子元件與第一電子元件間，並包覆該導電凸塊及導電元件，其中，該底膠係包括：複數粒徑介於0.1至1μm之導電顆粒；複數粒徑介於1至10μm之絕緣顆粒；及聚合物。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電顆粒之尺寸係小於該絕緣顆粒之尺寸。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，以該底膠之總重量計，該導電顆粒之含量係介於5至20重量%。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，以該底膠之總重量計，該絕緣顆粒之含量係介於45至60重量%。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，以該底膠之總重量計，該聚合物之含量係介於35至50重量%。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，當部分該導電凸塊無法電性連接至該導電元件時，填充於該導電凸塊與導電元件間之底膠中，該導電顆粒之含量係大於該絕緣顆粒之含量。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電凸塊之材質為銅。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電元件之材質為錫/鉛合金。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
  10. 如申請專利範圍第1項所述之半導體封裝件，其中，該第二電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
  11. 一種半導體封裝件之製法，係包括：將第二電子元件藉由複數導電凸塊設置於該第一電子元件上之導電元件；以及填充底膠於該第二電子元件與第一電子元件之間，以包覆該導電凸塊及導電元件，其中，該底膠係包括：複數粒徑介於0.1至1μm之導電顆粒；複數粒徑介於1至10μm之絕緣顆粒；以及聚合物。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該導電顆粒之尺寸係小於該絕緣顆粒之尺寸。
  13. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，以該底膠之總重量計，該導電顆粒之含量係介於5至20重量%。
  14. 如申請專利範圍第11項所述之半導體封裝件之製法，其中， 以該底膠之總重量計，該絕緣顆粒之含量係介於45至60重量%。
  15. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，以該底膠之總重量計，該聚合物之含量係介於35至50重量%。
  16. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該底膠復填充於部分該導電凸塊與其對應之該導電元件間，且於填充於部分該導電凸塊與導電元件間之底膠中，該導電顆粒之含量係大於該絕緣顆粒之含量。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，復包括於填充該底膠於該第一電子元件與第二電子元件間後，以100至200℃烘烤該半導體封裝件。
  18. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該導電凸塊之材質為銅。
  19. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該導電元件之材質為錫/鉛合金。
  20. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該第一電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
  21. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該第二電子元件為基板、半導體晶片、晶圓、經封裝或未經封裝之半導體元件。
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