TWI541957B - 半導體封裝件及其封裝基板 - Google Patents

半導體封裝件及其封裝基板 Download PDF

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TWI541957B
TWI541957B TW101116800A TW101116800A TWI541957B TW I541957 B TWI541957 B TW I541957B TW 101116800 A TW101116800 A TW 101116800A TW 101116800 A TW101116800 A TW 101116800A TW I541957 B TWI541957 B TW I541957B
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layer
patterned metal
package substrate
metal layer
package
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TW101116800A
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TW201347112A (zh
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林長甫
蔡和易
姚進財
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矽品精密工業股份有限公司
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Priority to TW101116800A priority Critical patent/TWI541957B/zh
Priority to CN201210167790.3A priority patent/CN103390602B/zh
Priority to US13/546,281 priority patent/US9666453B2/en
Publication of TW201347112A publication Critical patent/TW201347112A/zh
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Priority to US15/499,446 priority patent/US10679932B2/en

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    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Description

半導體封裝件及其封裝基板
本發明係有關一種半導體封裝件，尤指一種具有特殊圖案化金屬層之半導體封裝件及其封裝基板。
在現行覆晶封裝技術中，如第1圖所示之半導體封裝件1，係將一具有防銲層(solder mask)102之封裝基板10藉由複數導電凸塊111結合一半導體晶片11，再形成底充材料12(Underfill)於該半導體晶片11與該封裝基板10之間，以包覆該些導電凸塊111，且該底充材料12與該防銲層102間的結合力佳，可避免該底充材料12與該封裝基板10分離。
隨著電子產業的蓬勃發展，電子產品逐漸邁向多功能、高性能的趨勢，且電子產品在型態上之設計也趨於輕薄短小，例如：一般具有細間距(fine pitch)線路的封裝基板10係同時整合有細線路(線寬約等於12um)與大尺寸之接地部(徑寬大於200um)及粗線路(線寬大於20um)。
然而，該封裝基板10上之防銲層102雖可防止介電層100(其材質為預浸材Prepreg,PP)表面上之線路層101氧化，卻也增加該封裝基板10之厚度，致使整體結構難以薄化。
因此，遂發展出另一種覆晶用之封裝基板，其上不需形成防銲層，藉以達到薄化需求。如第2A圖所示，習知半導體封裝件2中，係將一不具有防銲層之封裝基板20之電性連接墊201a藉由複數導電凸塊211結合一半導體晶片21，再形成底充材料22於該半導體晶片21與該封裝基板20之間，以包覆該些導電凸塊211，且該底充材料22直接覆蓋線路層201，以防止該線路層201氧化。
再者，為了提升散熱功效，該封裝基板20之表面上佈設有大面積之圖案化金屬層202，且該圖案化金屬層202亦可供該半導體晶片21作接地。
惟，因該底充材料22與該介電層200間的結合力佳，而該底充材料22與金屬材之結合力差，故當該底充材料22與該金屬材(線路層201與圖案化金屬層202)間的接觸面積過多時，容易造成脫層(delamination)，即該底充材料22與該封裝基板20分離。
因此，第7808113號美國專利係提供解決上述問題之方式，如第2B圖所示之半導體封裝件2’中，係於一封裝基板20’之線路層201’與金屬層202’上形成一助黏層(adhesion promoter layer)203，且該底充材料22與該助黏層203間的結合力佳，使該底充材料22僅與少部分之金屬材相結合，故可避免脫層。
然而，製作該助黏層203之其中一方式，係將所有金屬材(除了電性連接墊201a處)之表面粗糙化以形成有機金屬表面(organometallic surface)供作為助黏層203，導致成本高、製程複雜度高及製程時間長，而不利於產品量產化。
又，製作該助黏層203之另一方式係於該金屬材表面上沉積矽烷偶合劑(silane coupling agent)以作為助黏層203，但該線路層201’與金屬層202’之表面相當凹凸(例如：導電通孔201b)，導致沉積矽烷偶合劑時不易控制該助黏層203之厚度，且仍有成本高、製程複雜度高及製程時間長等問題，故不利於產品大量生產。
因此，如何克服上述習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：一封裝基板，係具有介電層、形成於該介電層之同一面上之至少一圖案化金屬層及線路層，該圖案化金屬層具有至少一開口；半導體晶片，係以覆晶方式結合於該封裝基板上，且電性連接該線路層；以及底充材料，如含環氧樹脂之底膠，係形成於該封裝基板與該半導體晶片之間，以結合該介電層、該半導體晶片、該線路層及至少一該圖案化金屬層。
本發明復提供一種半導體封裝件，係包括：一封裝基板，係具有介電層、形成於該介電層之同一面上之至少一圖案化金屬層及線路層，該圖案化金屬層具有至少一開口；半導體晶片，係以覆晶方式結合於該封裝基板上，且電性連接該些線路層，又該半導體晶片未覆蓋該圖案化金屬層；以及底充材料，如含環氧樹脂之底膠，係形成於該封裝基板與該半導體晶片之間，以結合該介電層、該線路層及該半導體晶片，又該底充材料未結合該圖案化金屬層。
本發明復提供一種封裝基板，係包括：一基板本體，係具有介電層；線路層，係設於該介電層之表面上；以及至少一圖案化金屬層，係設於該線路層所在之介電層同一面上，且該圖案化金屬層具有至少一開口。
前述之半導體封裝件及其封裝基板中，該開口於該圖案化金屬層上之所佔面積比例為35%至60%。
前述之半導體封裝件及其封裝基板中，該開口係外露該介電層表面。
前述之半導體封裝件及其封裝基板中，該開口係開設於該圖案化金屬層之側部。或者，該開口係開設於該圖案化金屬層邊緣內。
前述之半導體封裝件及其封裝基板中，至少一該圖案化金屬層係作為接地或散熱之用。
另外，前述之半導體封裝件及其封裝基板中，該封裝基板內係具有導電通孔，以電性連接該線路層，且該線路層具有複數電性連接墊，以供電性連接該半導體晶片。其中，該半導體晶片係藉由複數導電凸塊結合於該些電性連接墊上，且該底充材料包覆該些導電凸塊。
由上可知，本發明之半導體封裝件及其封裝基板中，係藉由在該封裝基板上之圖案化金屬層形成外露該介電層表面之開口，以減少該圖案化金屬層之面積，而增加該底充材料與該介電層之接觸面積，故相較於習知技術，本發明之結構中，可減少底充材料與該圖案化金屬層間之接觸面積，因而有效避免脫層之問題。
再者，該開口製程具有簡易性、步驟少、成本低、製程時間短等優點，因而利於產品大量生產。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第3圖，係為本發明之半導體封裝件3之剖面示意圖。如第3圖所示，該半導體封裝件3係包括：一封裝基板30、覆晶接合該封裝基板30之一半導體晶片31、以及形成於該封裝基板30與該半導體晶片31之間的底充材料32。
所述之封裝基板30係具有一基板本體30a、設於該基板本體30a上之至少一介電層300、設於該介電層300同一表面上之線路層301及至少一圖案化金屬層302，且該圖案化金屬層302具有至少一開口302a，又該圖案化金屬層302與該線路層301不相電性連接。
於本實施例中，該基板本體30a內係具有導電通孔(圖未示)以電性連接該線路層301，且該線路層301具有複數電性連接墊301a，而該圖案化金屬層302之材料包含銅或鋁，又該些開口302a係外露該介電層300表面。
再者，可於該些電性連接墊301a上形成表面處理層33，且形成該表面處理層33之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑(OSP)所組成之群組中之其中一者。
又，一併參閱第4A至4C圖，係為該圖案化金屬層302之佈設區域之上視示意圖，該圖案化金屬層302係作為提升散熱效率與電性改進(如接地)之用，故該圖案化金屬層302可視不同封裝應用需求而佈設於置晶區之不同區域上；但該圖案化金屬層302之佈設形狀並不限於圖中所示，且第4A至4C圖中該置晶區係定義為底充材料32所分佈之區域內。
另外，該基板本體30a係為壓合板材，其包含Bismaleimide和Triazine聚合而成之BT板材或含Ajinomoto build up film之ABF板材。
所述之半導體晶片31係具有複數電極墊310，該些電極墊310藉由複數導電凸塊311結合且電性連接於該些電性連接墊301a上，使該半導體晶片31覆晶接合該封裝基板30。
於本實施例中，該半導體晶片31與該圖案化金屬層302係為接地連接。
所述之底充材料32係包覆該些導電凸塊311，且結合該線路層301、圖案化金屬層302、介電層300表面及該開口302a中之介電層300表面。
於本實施例中，該底充材料32係為包含環氧樹脂之底膠。
本發明之半導體封裝件3藉由在該圖案化金屬層302上形成開口302a，以減少該圖案化金屬層302之面積，因而可降低該底充材料32與該金屬材的接觸面積，且增加該底充材料32與該介電層300之接觸面積，故有效克服習知技術中之脫層問題。
再者，該開口302a於該圖案化金屬層302上所佔之面積比例(即開口面積率)為35%至60%時，較利於防止脫層。其中，所述之開口面積率之定義如下：開口面積率=開口面積/金屬總面積
又，本發明僅需於該圖案化金屬層302上進行開口製程，即可克服脫層問題，且因有關開口製程之方法繁多，並且開口技術已相當成熟與普及，故相較於習知技術，本發明利用開口製程將使該半導體封裝件3之成本低、製程簡易及製程時間短，且不受該圖案化金屬層302之表面凹凸結構影響，因而有利於產品大量生產。
另外，於另一實施例中，如第4D圖所示，該圖案化金屬層302’係完全位於該置晶區外，使該半導體晶片31未覆蓋該圖案化金屬層302’，且該底充材料32未結合該圖案化金屬層302’，故仍可降低該底充材料32與金屬材的接觸面積。
請一併參閱第5A及5B圖，該開口302a開設於該圖案化金屬層302之同一側部，如第5A圖所示；或者，該開口302a係開設於該圖案化金屬層302之不同側部，如第5B圖所示。
再者，如第5C圖所示，該開口302a’亦可開設於該圖案化金屬層302邊緣內。
又，於本實施例中，係以L形的圖案化金屬層302作說明，而於其它實施例中，該圖案化金屬層302之形狀可任意設計，並無特別限制，亦即只要於該圖案化金屬層302上形成開口302a即可。
另外，該開口302a,302a’之端面輪廓形狀可為圓形、矩形、三角形、方形、長方形、十字形、星形、橢圓形、多邊形或任意形狀，並無特別限制。
綜上所述，本發明半導體封裝件及其封裝基板，主要藉由該封裝基板上之圖案化金屬層具有外露該介電層表面之開口，以減少該圖案化金屬層之面積，而增加該底充材料與該介電層之接觸面積，因而避免該底充材料與該金屬層間之脫層問題。
再者，開口製程因具有簡易性、步驟少、成本低、製程時間短等優點，故有利於產品大量生產。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’,3．．．半導體封裝件
10,20,20’,30．．．封裝基板
100,200,300．．．介電層
101,201,201’,301．．．線路層
102．．．防銲層
11,21,31．．．半導體晶片
111,211,311．．．導電凸塊
12,22,32．．．底充材料
201a,301a．．．電性連接墊
201b．．．導電通孔
202,202’．．．金屬層
203．．．助黏層
30a．．．基板本體
302,302’．．．圖案化金屬層
302a,302a’．．．開口
310．．．電極墊
33．．．表面處理層
第1圖係為習知半導體封裝件之剖視示意圖；
第2A及2B圖係為習知半導體封裝件之不同態樣之剖視示意圖；
第3圖係為本發明半導體封裝件之剖視示意圖；
第4A至4D圖係為本發明半導體封裝件之不同實施例之上視示意圖；以及
第5A、5B及5C圖係為本發明封裝基板之圖案化金屬層之不同態樣之局部上視示意圖。
3．．．半導體封裝件
30．．．封裝基板
30a．．．基板本體
300．．．介電層
301．．．線路層
301a．．．電性連接墊
302．．．圖案化金屬層
302a．．．開口
31．．．半導體晶片
310．．．電極墊
311．．．導電凸塊
32．．．底充材料
33．．．表面處理層

Claims (16)

  1. 一種半導體封裝件，係包括：一封裝基板，係具有介電層、形成於該介電層之同一面上之至少一圖案化金屬層及線路層，該圖案化金屬層具有至少一開口以外露該介電層，又該圖案化金屬層與該線路層不相電性連接；半導體晶片，係以覆晶方式結合於該封裝基板上，且電性連接該線路層；以及底充材料，係形成於該封裝基板與該半導體晶片之間，以結合該介電層、該半導體晶片、該線路層、外露於該開口中之介電層及至少一該圖案化金屬層。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該開口係開設於該圖案化金屬層之側部。
  3. 一種半導體封裝件，係包括：一封裝基板，係具有介電層、形成於該介電層之同一面上之至少一圖案化金屬層及線路層，該圖案化金屬層之側部係開設有至少一開口，又該圖案化金屬層與該線路層不相電性連接；半導體晶片，係以覆晶方式結合於該封裝基板上，且電性連接該些線路層，又該半導體晶片未覆蓋該圖案化金屬層；以及底充材料，係形成於該封裝基板與該半導體晶片之間，以結合該介電層、該線路層及該半導體晶片，又該底充材料未結合該圖案化金屬層。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該開口係外露該介電層表面。
  5. 如申請專利範圍第1或3項所述之半導體封裝件，其中，該開口於該圖案化金屬層上之所佔面積比例為35%至60%。
  6. 如申請專利範圍第1或3項所述之半導體封裝件，其中，該開口係開設於該圖案化金屬層邊緣內。
  7. 如申請專利範圍第1或3項所述之半導體封裝件，其中，至少一該圖案化金屬層係作為接地或散熱之用。
  8. 如申請專利範圍第1或3項所述之半導體封裝件，其中，該封裝基板內係具有導電通孔，以電性連接該線路層，且該線路層具有複數電性連接墊，以電性連接該半導體晶片。
  9. 如申請專利範圍第8項所述之半導體封裝件，其中，該半導體晶片係藉由複數導電凸塊結合於該些電性連接墊上，且該底充材料包覆該些導電凸塊。
  10. 如申請專利範圍第1或3項所述之半導體封裝件，其中，該底充材料之材質係包含環氧樹脂。
  11. 一種封裝基板，係包括：一基板本體，係具有介電層；線路層，係設於該介電層之表面上；以及至少一圖案化金屬層，係設於該線路層所在之介電層同一面上，且該圖案化金屬層之側部係開設有至少一開口，又該圖案化金屬層與該線路層不相電性連 接。
  12. 如申請專利範圍第11項所述之封裝基板，其中，該開口係外露該介電層表面。
  13. 如申請專利範圍第11項所述之封裝基板，其中，該開口於該圖案化金屬層上之所佔面積比例為35%至60%。
  14. 如申請專利範圍第11項所述之封裝基板，其中，該開口復開設於該圖案化金屬層邊緣內。
  15. 如申請專利範圍第11項所述之封裝基板，其中，至少一該圖案化金屬層係作為接地或散熱之用。
  16. 如申請專利範圍第11項所述之封裝基板，其中，該封裝基板內係具有導電通孔，以電性連接該線路層，且該線路層具有複數電性連接墊，以供電性連接半導體晶片。
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